IP Library Granted Patent US 10,354,873
Granted Patent B2
US 10,354,873 · App. 15/491,432 · Granted Jul 16, 2019

Organic mandrel protection process

Inventors: Akiteru Ko (Schenectady, NY); Angelique Raley (Halfmoon, NY); Sophie Thibaut (Troy, NV); Satoru Nakamura (Albany, NY); Nihar Mohanty (Clifton Park, NY)
Assignee: Tokyo Electron Limited
H01L21/0337H01L21/0228H01L21/0276H01L21/02164H01L21/02274H01L21/0332H01L21/0335H01L21/31116H01L21/31138H01L22/12H01L22/20H01L22/26
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Quick Facts
Patent No.
US 10,354,873
App. No.
15/491,432
Granted
Jul 16, 2019
Kind
B2
Abstract

Provided is a method of patterning spacers, the method comprising: providing an initial patterned structure in a substrate in a processing chamber, the initial patterned structure comprising an organic mandrel and an underlying layer; exposing the patterned structure in a direct current superposition (DCS) plasma treatment process, the process depositing a layer of a first material on the initial patterned structure; performing an atomic layer conformal deposition process using a second material, the first material providing protection to the organic mandrel at the beginning of the atomic layer conformal deposition process; performing a spacer etch mandrel pull process, the process creating a final patterned structure with a target final sidewall angle; concurrently controlling integration operating variables in the DCS plasma treatment process, the atomic layer conformal deposition process, and the spacer etch mandrel pull process in order to meet the target final sidewall angle and other integration objectives.

Claims (33)

1. A method of patterning spacers in a multi-patterning scheme, the method comprising:

providing an initial patterned structure on a substrate in a processing chamber, the initial patterned structure comprising an organic mandrel and an underlying layer;

exposing the initial patterned structure in a direct current superposition (DCS) plasma treatment process, the DCS plasma treatment process depositing a layer of a first material on the initial patterned structure configured to protect the initial patterned structure during subsequent operations;

performing an atomic layer conformal deposition process to deposit a second material, the first material providing protection to the organic mandrel at the beginning of the atomic layer conformal deposition process;

performing a spacer etch mandrel pull (SEMP) process, the SEMP process creating a final patterned structure with a target final sidewall angle;

concurrently controlling integration operating variables in the DCS plasma treatment process, the atomic layer conformal deposition process, and the SEMP process in order to meet integration objectives including the target final sidewall angle.

2. The method of claim 1 wherein the target final sidewall angle is in a range from 89 to 90 degrees, the first material is silicon and the second material is silicon oxide.

3. The method of claim 2 wherein the silicon is from a top electrode in a DCS plasma treatment device used in the DCS plasma treatment process, the silicon forming an atomic layer deposition protecting the top and sides of the initial patterned structure by forming a silicon oxide layer.

4. The method of claim 2 wherein the integration operating variables for the DCS plasma treatment process include the DCS voltage, H2 flowrate, Ar flowrate, process time, temperature, pressure, and high frequency power.

5. The method of claim 4 wherein the DCS voltage is in a range from 700 to 1100 V.

6. The method of claim 4 wherein the H2 flowrate is in the range from 80 to 119 sccm and/or the Ar flowrate is in the range from 80 to 119 sccm.

7. The method of claim 4 wherein the process time is in a range from 10 to 30 seconds.

8. The method of claim 4 wherein the temperature is in the range from 10 to 50 degrees C.

9. The method of claim 4 wherein the pressure is in the range from 80 to 100 mT and the high frequency power is in the range from 80 to 119 MHz.

10. The method of claim 4 , further comprising, prior to providing the initial patterned structure:

providing a resist layer, an intermediate layer, an organic layer, and the underlying layer; and

performing an organic open process to etch the intermediate layer and the organic layer, remove the resist layer, and remove the intermediate layer to thereby generate the initial patterned structure.

11. The method of claim 10 wherein the intermediate layer includes a silicon anti-reflective coating (SiARC), and the organic layer comprises one of an organic planarizing layer (OPL), an advanced pattern film (APF), or a spin-on hardmask (SOH).

12. The method of claim 11 wherein the APF includes chemical vapor deposition (CVD) amorphous carbon film containing hydrogen, the SOH includes spin-on organic polymer carbon content greater than 90%, and the OPL comprises a composition of C/H/O/N 81.6/4.6/9.9/3.9 wt % or C/H/O/N 85.4/5.8/6.0/2.9 wt %.

13. The method of claim 1 wherein the integration objectives include the target final sidewall angle in a range from 87 to 90 degrees.

14. The method of claim 1 wherein the integration objectives include a target line width roughness (LWR) of the final patterned structure in a range from 4.0 to 4.8 nm after the SEMP process.

15. The method of claim 1 wherein the integration objectives include a target line width roughness (LWR) of the final patterned structure in a range from 3.5 to 4.0 nm after the atomic layer conformal deposition process.

16. The method of claim 1 wherein the integration objectives include a target left-line edge roughness (L-LER) of the final patterned structure in a range from 2.2 to 2.8 nm after the SEMP process.

17. The method of claim 1 wherein the integration objectives include a target left-line edge roughness (L-LER) of the final patterned structure in a range from 2.2 to 3.0 nm after the atomic layer conformal deposition process.

18. The method of claim 1 :

wherein the integration objectives include a target edge placement error of the final patterned structure in a range from 0.1 to 3.0% or a range from −0.1 to −3.0%; and

wherein the integration operating variables are controlled to meet the target edge placement error.

19. The method of claim 1 wherein concurrently controlling integration operating variables in order to meet integration objectives includes:

performing measurements of integration operating variables; and

performing adjustments of one of more of the integration operating variables in order to meet the integration objectives; or

performing in situ online measurements of integration operating variables; and

performing in situ adjustments of one of more of the integration operating variables in order to meet the integration objectives, wherein the in situ adjustments are based on the in situ online measurements of the integration operating variables.

20. The method of claim 4 wherein the process time is in a range from 31 to 60 seconds.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 19, 2017
From: KO, AKITERU; RALEY, ANGELIQUE; THIBAUT, SOPHIE; NAKAMURA, SATORU; MOHANTY, NIHAR
To: TOKYO ELECTRON LIMITED
Reel/Frame 042064/0052 →
Continuity (3)
Provisional Application 62373500 · Aug 11, 2016
Provisional Application 62347460 · Jun 8, 2016
Related Publication 20170358450A1 · Dec 14, 2017
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