Semiconductor devices and method of manufacturing the same
A semiconductor device includes a first transistor in a first region of a substrate and a second transistor in a second region of the substrate. The first transistor includes multiple first semiconductor patterns; a first gate electrode; a first gate dielectric layer; a first source/drain region; and an inner-insulating spacer. The second transistor includes multiple second semiconductor patterns; a second gate electrode; a second gate dielectric layer; and a second source/drain region. The second gate dielectric layer extends between the second gate electrode and the second source/drain region and is in contact with the second source/drain region. The first source/drain region is not in contact with the first gate dielectric layer.
1. A semiconductor device comprising:
a substrate including a first region and a second region;
a first contact disposed on the first region of the substrate;
a second contact disposed on the second region of the substrate;
a plurality of nanowires disposed on the substrate, and including a first nanowire disposed on the first region of the substrate, a second nanowire disposed on the first nanowire, a third nanowire disposed on the second region of the substrate and a fourth nanowire disposed on the third nanowire;
a first source/drain disposed on the first region of the substrate, and contacting the first nanowire;
a second source/drain disposed on the second region of the substrate, and contacting the third nanowire;
a first gate structure including a first gate electrode that surrounds the second nanowire, a first gate dielectric layer disposed between the first gate electrode and the first source/drain, and an inner-insulating layer between the first gate electrode and the first source/drain; and
a second gate structure including a second gate electrode that surrounds the fourth nanowire, a second gate dielectric layer in direct contact with the second gate electrode and the second source/drain,
wherein each of the plurality of nanowires includes a channel region that is electrically isolated from the substrate.
2. The semiconductor device of claim 1 , wherein the first gate structure is a multi-gate structure.
3. The semiconductor device of claim 1 , wherein the second gate structure is a gate-all-around type structure.
4. The semiconductor device of claim 1 , wherein the first gate electrode surrounds the first nanowire.
5. The semiconductor device of claim 1 , wherein the first gate dielectric layer is disposed between the second nanowire and the first gate electrode.
6. The semiconductor device of claim 5 , wherein the first gate dielectric layer is a high-k gate dielectric layer.
7. The semiconductor device of claim 1 , wherein the first contact is disposed on the first source/drain.
8. The semiconductor device of claim 1 , further comprising a first channel separation region disposed between the first region of the substrate and the first gate electrode.
9. The semiconductor device of claim 1 , wherein the first contact is on an epitaxial region of the substrate.
10. The semiconductor device of claim 1 , wherein a width of an upper portion of the first contact is greater than a width of a lower portion of the first contact.