IP Library › Granted Patent US 12,342,608
Granted Patent B2
US 12,342,608 · App. 18/298,398 · Granted Jun 24, 2025

Semiconductor device

Inventor: Yuichi Harada (Matsumoto, JP)
Assignee: FUJI ELECTRIC CO., LTD.
H10D84/617H10D8/422H10D12/481H10D62/111H10D62/112H10D62/127H10D62/142H10D62/393H10D64/112H10D64/117
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Quick Facts
Patent No.
US 12,342,608
App. No.
18/298,398
Granted
Jun 24, 2025
Kind
B2
Abstract

Provided is a semiconductor device comprising a semiconductor substrate that includes a transistor region; an emitter electrode that is provided on the semiconductor substrate; a first dummy trench portion that is provided on the transistor region of the semiconductor substrate and includes a dummy conducting portion that is electrically connected to the emitter electrode; and a first contact portion that is a partial region of the transistor region, provided between an end portion of a long portion of the first dummy trench portion and an end portion of the semiconductor substrate, and electrically connects the emitter electrode and a semiconductor region with a first conductivity type provided in the transistor region.

Claims (52)

1. A semiconductor device comprising:

a top surface electrode that is provided above a top surface of a semiconductor substrate and is formed by material including metal;

a first trench portion that is provided in an active region and includes a first conductive portion that is electrically connected to the top surface electrode;

a semiconductor region with a first conductivity type that is provided in at least a part of a region between an end portion of a long portion of the first trench portion and an end portion of the semiconductor substrate; and

a contact portion that electrically connects the semiconductor region and the top surface electrode,

wherein a width of the contact portion in a second direction that is substantially orthogonal to a first direction in which the long portion extends, is greater than a width of the first trench portion in the second direction.

2. The semiconductor device according to claim 1 , further comprising:

a gate metal layer that is provided above the top surface of the semiconductor substrate; and

a second trench portion that is provided in the active region of the semiconductor substrate and includes a second conductive portion that is electrically connected to the gate metal layer.

3. The semiconductor device according to claim 2 , further comprising:

a base region with the first conductivity type that is provided in the active region of the semiconductor substrate and is configured to function as a channel formation region near the second trench portion;

wherein the semiconductor region is a high concentration region with a higher doping concentration than the base region.

4. The semiconductor device according to claim 3 , further comprising:

a connection layer that is a polysilicon layer that is electrically connected to the first conductive first conductive portion.

5. The semiconductor device according to claim 4 , further comprising:

a mesa portion that is a portion of the semiconductor substrate positioned between two adjacent the first trench portions,

wherein a width of the contact portion is greater than a width of the mesa portion, in the second direction.

6. The semiconductor device according to claim 4 , wherein

the connection layer includes a connection layer contact portion that is electrically connected to the top surface electrode, and

the contact portion is provided between the connection layer contact portion and an end portion of the top surface electrode, in the first direction.

7. The semiconductor device according to claim 5 , wherein

the contact portion extends in the second direction along the connection layer.

8. The semiconductor device according to claim 3 , wherein

the active region is, in an overhead view, a region inside an range in which the top surface electrode is provided.

9. The semiconductor device according to claim 8 , wherein

the contact portion is provided is provided between the end portion of the long portion of the first trench portion and an end portion of the semiconductor substrate.

10. The semiconductor device according to claim 5 , further comprising:

a drift region with the first conductivity type, at least a part of which is provided within the mesa portion; and

a first bottom surface region that is provided at least along an outer periphery of a bottom surface of the semiconductor substrate and having a higher doping concentration than the drift region,

wherein the first bottom surface region functions as a cathode of a diode.

11. The semiconductor device according to claim 10 , wherein,

the semiconductor region is in contact with the base region, and

the base region functions as an anode of the diode.

12. The semiconductor device according to claim 10 , further comprising:

a second bottom surface region with the first conductivity type that is provided discretely inside the first bottom surface region and includes a higher doping concentration than the base region,

on the bottom surface of the semiconductor substrate.

13. The semiconductor device according to claim 4 , further comprising:

an edge termination region that includes a structure formed by one or more of a combination of a guard ring, a filed plate and a RESURF,

wherein the semiconductor region is provided in the edge termination region.

14. The semiconductor device according to claim 4 , further comprising:

a well region with the first conductivity type, including a floor surface at a position that is deeper than a floor portion of the first trench portion,

wherein the semiconductor region is positioned above the well region.

15. The semiconductor device according to claim 14 , wherein,

the well region surrounds the end portion of the long portion of the first trench portion.

16. The semiconductor device according to claim 14 , further comprising:

an intermediate region with a second conductivity between the semiconductor region and the well region, below the contact portion,

wherein the intermediate region has a lower doping concentration than the semiconductor region and the well region.

17. The semiconductor device according to claim 16 , wherein,

the intermediate region is the base region.

18. The semiconductor device according to claim 2 , further comprising:

one or more peripheral longitudinal contact portions that are positioned farther outward than the first trench portion or the second trench portion positioned farthest outward in the second direction, and extend in the first direction.

19. A semiconductor device comprising: a top surface electrode that is provided above a top surface of a semiconductor substrate and is formed by material including metal; a first trench portion that is provided in an active region and includes a first conductive portion that is electrically connected to the top surface electrode; a semiconductor region with a first conductivity type that is provided in at least a part of a region between an end portion of a long portion of the first trench portion and an end portion of the semiconductor substrate; a contact portion that electrically connects the semiconductor region and the top surface electrode; and a connection layer that is a polysilicon layer that is electrically connected to the first conductive portion, wherein the contact portion extends along the connection layer in a second direction that is substantially orthogonal to a first direction in which the long portion extends.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 11, 2023
From: HARADA, YUICHI
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 063280/0033 →
Priority Claims (2)
JP 2017-221127 · Nov 16, 2017 · national
JP 2018-113413 · Jun 14, 2018 · national
Continuity (4)
Continuation 17452069 · Oct 25, 2021
Continuation 16664930 · Oct 27, 2019
Continuation PCTJP2018034933 · Sep 20, 2018
Related Publication 20230307446A1 · Sep 28, 2023
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