Granted Patent B2

US 12,585,158 · App. 18/592,933 · Granted Mar 24, 2026

Inventors: Toshikazu Kondo (Atsugi, JP); Jun Koyama (Sagamihara, JP); Shunpei Yamazaki (Setagaya, JP)

Assignee: Semiconductor Energy Laboratory Co., Ltd.

G02F1/1368G02F1/133345G02F1/136227G02F1/136286G09G3/3622H10D30/6755H10D64/62H10D86/423H10D86/443H10D86/60G02F1/13606G02F1/13624G02F1/136295G02F2202/10G09G2300/0426

Abstract

Claims (78)

1 . A semiconductor device comprising a display portion, the display portion comprising:

a first signal line;

a first scan line;

a second scan line adjacent to the first scan line;

a first transistor comprising:

an oxide semiconductor layer;

a gate insulating layer over the oxide semiconductor layer;

a gate electrode overlapping with the oxide semiconductor layer with the gate insulating layer provided therebetween, the gate electrode electrically connected to the first scan line;

a first insulating layer over the gate electrode; and

a source electrode and a drain electrode over the first insulating layer, the source electrode and the drain electrode being in contact with the oxide semiconductor layer through a first contact hole and a second contact hole provided in the first insulating layer;

a second insulating layer over the first insulating layer, the source electrode, and the drain electrode; and

a pixel electrode over the second insulating layer,

wherein the first signal line is electrically connected to one of the source electrode and the drain electrode,

wherein the oxide semiconductor layer comprises indium, gallium, and zinc,

wherein the first signal line intersects the first scan line at a first region of the first signal line,

wherein the first signal line intersects the second scan line at a second region of the first signal line,

wherein each of an upper surface of the first region and an upper surface of the second region has a convex shape,

wherein the first signal line has a third region between the first region and the second region, and

wherein an upper surface of the third region of the first signal line is flat.

2 . The semiconductor device according to claim 1 , wherein neither a conductive layer nor a semiconductor layer is provided under the third region of the first signal line.

3 . The semiconductor device according to claim 1 , wherein the gate electrode comprises copper.

4 . The semiconductor device according to claim 1 , wherein the first signal line comprises:

a first conductive layer comprising any one of titanium, molybdenum, and tungsten; and

a second conductive layer over the first conductive layer, the second conductive layer comprising copper.

5 . The semiconductor device according to claim 1 , wherein each of the first insulating layer and the second insulating layer comprises silicon and oxygen.

6 . A semiconductor device comprising a display portion, the display portion comprising:

a first signal line;

a first scan line;

a second scan line adjacent to the first scan line;

a first transistor comprising:

a base insulating layer over a substrate;

an oxide semiconductor layer over the base insulating layer;

a gate insulating layer over the oxide semiconductor layer;

a gate electrode overlapping with the oxide semiconductor layer with the gate insulating layer provided therebetween, the gate electrode electrically connected to the first scan line;

a first insulating layer over the gate electrode; and

a source electrode and a drain electrode over the first insulating layer, the source electrode and the drain electrode being in contact with the oxide semiconductor layer through a first contact hole and a second contact hole provided in the first insulating layer;

a second insulating layer over the first insulating layer, the source electrode, and the drain electrode; and

a pixel electrode over the second insulating layer,

wherein the first signal line is electrically connected to one of the source electrode and the drain electrode,

wherein the oxide semiconductor layer comprises indium, gallium, and zinc,

wherein the first signal line intersects the first scan line at a first region of the first signal line,

wherein the first signal line intersects the second scan line at a second region of the first signal line,

wherein each of an upper surface of the first region and an upper surface of the second region has a convex shape,

wherein the first signal line has a third region between the first region and the second region, and

wherein an upper surface of the third region of the first signal line is flat.

7 . The semiconductor device according to claim 6 , wherein the oxide semiconductor layer is formed by a sputtering method using a target having a composition ratio of In: Ga:Zn=1:1:1.

8 . The semiconductor device according to claim 6 , wherein neither a conductive layer nor a semiconductor layer is provided under the third region of the first signal line.

9 . The semiconductor device according to claim 6 , wherein the gate electrode comprises copper.

10 . The semiconductor device according to claim 6 , wherein the first signal line comprises:

a first conductive layer comprising any one of titanium, molybdenum, and tungsten; and

a second conductive layer over the first conductive layer, the second conductive layer comprising copper.

11 . The semiconductor device according to claim 6 , wherein each of the first insulating layer and the second insulating layer comprises silicon and oxygen.

12 . A semiconductor device comprising a display portion, the display portion comprising:

a first signal line;

a first scan line;

a second scan line adjacent to the first scan line;

a first transistor comprising:

an oxide semiconductor layer;

a gate insulating layer over the oxide semiconductor layer;

a gate electrode overlapping with the oxide semiconductor layer with the gate insulating layer provided therebetween, the gate electrode electrically connected to the first scan line;

a first insulating layer over the gate electrode; and

a source electrode and a drain electrode over the first insulating layer, the source electrode and the drain electrode being in contact with the oxide semiconductor layer through a first contact hole and a second contact hole provided in the first insulating layer;

a second insulating layer over the first insulating layer, the source electrode, and the drain electrode; and

a pixel electrode over the second insulating layer,

wherein the first signal line is electrically connected to one of the source electrode and the drain electrode,

wherein the oxide semiconductor layer comprises In, Ga, and Zn,

wherein the oxide semiconductor layer is formed by a sputtering method using a target having a composition ratio of In: Ga:Zn=1:1:1,

wherein the first signal line intersects the first scan line at a first region of the first signal line,

wherein the first signal line intersects the second scan line at a second region of the first signal line,

wherein each of an upper surface of the first region and an upper surface of the second region has a convex shape,

wherein the first signal line has a third region between the first region and the second region, and

wherein an upper surface of the third region of the first signal line is flat.

13 . The semiconductor device according to claim 12 , wherein neither a conductive layer nor a semiconductor layer is provided under the third region of the first signal line.

14 . The semiconductor device according to claim 12 , wherein the gate electrode comprises copper.

15 . The semiconductor device according to claim 12 , wherein the first signal line comprises:

a first conductive layer comprising any one of titanium, molybdenum, and tungsten; and

a second conductive layer over the first conductive layer, the second conductive layer comprising copper.

16 . The semiconductor device according to claim 12 , wherein each of the first insulating layer and the second insulating layer comprises silicon and oxygen.

Priority Claims (1)

Continuity (8)

References Cited (400)