Performance optimization by sizing gates and source/drain contacts differently for different transistors
A first transistor includes a first gate, a first source/drain, and a first source/drain contact disposed over the first source/drain. The first gate has a first dimension measured in a first lateral direction. The first source/drain contact has a second dimension measured in the first lateral direction. A second transistor includes a second gate, a second source/drain, and a second source/drain contact disposed over the second source/drain. The second gate has a third dimension measured in the first lateral direction. The second source/drain contact has a fourth dimension measured in the first lateral direction. A first ratio of the first dimension and the second dimension is different from a second ratio of the third dimension and the fourth dimension.
1 . A device, comprising:
a first transistor that comprises a first gate, a first source/drain, and a first source/drain contact disposed over the first source/drain, wherein:
the first gate has a first dimension measured in a first lateral direction, and
the first source/drain contact has a second dimension measured in the first lateral direction; and
a second transistor that comprises a second gate, a second source/drain, and a second source/drain contact disposed over the second source/drain, wherein:
the second gate has a third dimension measured in the first lateral direction,
the second source/drain contact has a fourth dimension measured in the first lateral direction,
a first ratio of the first dimension and the second dimension is different from a second ratio of the third dimension and the fourth dimension;
the first transistor is a part of an electronic memory storage device;
the second transistor is a part of a logic device that is not the electronic memory storage device;
the first dimension is greater than the third dimension; and
the second dimension is less than the fourth dimension.
2 . The device of claim 1 , wherein:
the electronic memory storage device comprises a static random access memory (SRAM) cell; and
the logic device comprises a controller for operating the SRAM cell.
3 . The device of claim 1 , wherein the first ratio is greater than the second ratio.
4 . The device of claim 1 , wherein the first transistor and the second transistor have different operational speeds.
5 . The device of claim 1 , wherein:
the first transistor is implemented in a first region of a wafer;
the second transistor is implemented in a second region of the wafer; and
the first region of the wafer and the second region of the wafer have different pattern densities.
6 . The device of claim 1 , wherein:
the first gate is separated from the first source/drain contact by a first distance in the first lateral direction;
the second gate is separated from the second source/drain contact by a second distance in the first lateral direction; and
the first distance is substantially equal to the second distance.
7 . A device, comprising:
a first gate disposed over a substrate;
a first source/drain disposed in a first portion of the substrate adjacent to the first gate;
a first source/drain contact disposed over the first source/drain;
a second gate disposed over the substrate;
a second source/drain disposed in a second portion of the substrate adjacent to the second gate; and
a second source/drain contact disposed over the second source/drain;
wherein:
the first gate is wider than the second gate in a first horizontal direction;
the first source/drain contact is narrower than the second source/drain contact in the first horizontal direction;
the first gate and the first source/drain are components of a first type of transistor;
the second gate and the second source/drain are components of a second type of transistor different from the first type of transistor;
the first type of transistor is part of a memory device; and
the second type of transistor is part of a non-memory device.
8 . The device of claim 7 , wherein:
the memory device comprises a Static Random Access Memory (SRAM) device; and
the non-memory device is a part of a microcontroller configured to control an operation of the SRAM device.
9 . The device of claim 7 , wherein:
the first type of transistor has a first operational speed; and
the second type of transistor has a second operational speed different from the first operational speed.
10 . The device of claim 7 , wherein:
the first gate and the first source/drain are implemented in a first region of the substrate;
the second gate and the second source/drain are implemented in a second region of the substrate; and
the first region of the substrate and the second region of the substrate have different pattern densities.
11 . The device of claim 7 , further comprising:
a first gate spacer disposed between the first gate and the first source/drain; and
a second gate spacer disposed between the second gate and the second source/drain; wherein the first gate spacer and the second gate spacer have substantially similar widths.
12 . The device of claim 7 , further comprising:
a first gate spacer disposed between the first gate and the first source/drain; and
a second gate spacer disposed between the second gate and the second source/drain, wherein a width of the first gate spacer is equal to a width of the second gate spacer in the first horizontal direction.
13 . A device, comprising:
a first gate disposed over a substrate;
a first source/drain disposed in a first portion of the substrate adjacent to the first gate;
a first source/drain contact disposed over the first source/drain;
a second gate disposed over the substrate;
a second source/drain disposed in a second portion of the substrate adjacent to the second gate; and
a second source/drain contact disposed over the second source/drain;
wherein:
the first gate is wider than the second gate in a first horizontal direction;
the first source/drain contact is narrower than the second source/drain contact in the first horizontal direction;
the first gate and the first source/drain are components of a first type of transistor;
the second gate and the second source/drain are components of a second type of transistor different from the first type of transistor;
the first type of transistor is part of a non-memory device; and
the second type of transistor is part of a memory device.
14 . The device of claim 13 , wherein:
the memory device comprises a Static Random Access Memory (SRAM) device.
15 . The device of claim 14 , wherein:
the non-memory device is a part of a microcontroller configured to control an operation of the SRAM device.
16 . The device of claim 13 , wherein:
the first type of transistor has a first operational speed; and
the second type of transistor has a second operational speed different from the first operational speed.
17 . The device of claim 13 , wherein:
the first gate and the first source/drain are implemented in a first region of the substrate;
the second gate and the second source/drain are implemented in a second region of the substrate; and
the first region of the substrate and the second region of the substrate have different pattern densities.
18 . The device of claim 13 , further comprising:
a first gate spacer disposed between the first gate and the first source/drain; and
a second gate spacer disposed between the second gate and the second source/drain; wherein the first gate spacer and the second gate spacer have substantially similar widths.
19 . The device of claim 13 , further comprising:
a first gate spacer disposed between the first gate and the first source/drain; and
a second gate spacer disposed between the second gate and the second source/drain, wherein a width of the first gate spacer is equal to a width of the second gate spacer in the first horizontal direction.
20 . The device of claim 13 , further comprising:
an interlayer dielectric overlying the first source/drain and in contact with the first source/drain.