Molded direct bonded and interconnected stack
Dies and/or wafers are stacked and bonded in various arrangements including stacks, and may be covered with a molding to facilitate handling, packaging, and the like. In various examples, the molding may cover more or less of a stack, to facilitate connectivity with the devices of the stack, to enhance thermal management, and so forth.
1 . A microelectronic assembly, comprising:
a plurality of adjacent stacks of multiple microelectronic elements, each stack comprising:
a first substrate having a first microelectronic circuit element in the first substrate;
a second substrate having a second microelectronic circuit element in the second substrate, the second substrate hybrid bonded to the first substrate, electrically coupling the first substrate to the second substrate without adhesive; and
a first encapsulant covering at least a side edge of the second substrate facing a side edge of an adjacent stack;
a base substrate, the plurality of stacks attached to the base substrate, the plurality of stacks laterally spaced from one another; and
a second encapsulant disposed in the lateral space between the plurality of adjacent stacks.
2 . The microelectronic assembly of claim 1 , wherein the second encapsulant has a different composition than the first encapsulant.
3 . The microelectronic assembly of claim 2 , wherein the second encapsulant comprises an organic material.
4 . The microelectronic assembly of claim 1 , wherein the first encapsulant comprises multiple layers of encapsulating material.
5 . The microelectronic assembly of claim 4 , wherein a first layer of the first encapsulant covers the side edge of the second substrate, and wherein a second layer of the first encapsulant is disposed adjacent to the first layer.
6 . The microelectronic assembly of claim 5 , wherein the second layer of the first encapsulant comprises silica.
7 . The microelectronic assembly of claim 1 , each stack further comprising:
a third substrate bonded over the second substrate without an intervening adhesive.
8 . The microelectronic assembly of claim 7 , at least one stack further comprising:
a first conductive via electrically coupled to the first microelectronic circuit element of the first substrate and extending at least partially through the first substrate providing electrical connectivity from the first substrate to the second substrate.
9 . The microelectronic assembly of claim 8 , wherein the base substrate comprises conductive features providing electrical connectivity from the base substrate to the second substrate.
10 . The microelectronic assembly of claim 1 , wherein the first encapsulant covers the side edge of the second substrate of at least one stack, but not the first substrate of the at least one stack.
11 . The microelectronic assembly of claim 1 , wherein the second substrate of at least one stack includes an etched portion at a perimeter, forming a recess at a perimeter edge of the second substrate.
12 . The microelectronic assembly of claim 1 , wherein at least the second substrate comprises a solid-state memory device.
13 . A microelectronic assembly, comprising:
a host element with a surface;
a first stack of hybrid bonded dies attached to the surface of the host element, the first stack of hybrid bonded dies including a first die hybrid bonded to a second die without an adhesive;
a second stack of hybrid bonded dies attached to the surface of the host element, the second stack laterally spaced from the first stack, the second stack of hybrid bonded dies including a third die hybrid bonded to a fourth die without an adhesive; and
a first encapsulant disposed in the lateral space between the first stack and the second stack.
14 . The microelectronic assembly of claim 13 , wherein the first encapsulant comprises an organic material.
15 . The microelectronic assembly of claim 13 , wherein the first die and the third die are bonded to the host element, wherein a fifth die and a sixth die are directly bonded to the first die, the fifth die laterally spaced from the sixth die.
16 . The microelectronic assembly of claim 15 , further comprising a second encapsulant disposed in the lateral space between the fifth die and the sixth die.
17 . The microelectronic assembly of claim 16 , wherein the second encapsulant has a different composition than the first encapsulant.
18 . The microelectronic assembly of claim 17 , wherein the second encapsulant comprises silicon oxide.
19 . The microelectronic assembly of claim 16 , wherein the second encapsulant comprises a first layer and a second layer with a different composition than the first layer.
20 . An interconnected stack comprising:
a first die comprising:
a first dielectric surface with a first plurality of conductive features embedded within and exposed at the first dielectric surface;
a first plurality of microelectronic devices embedded within the first die and in electrical communication with the first plurality of conductive features; and
an optical component located within the first die;
a second die directly bonded to the first die, the second die comprising:
a second dielectric surface with a second plurality of conductive features embedded within and exposed at the second dielectric surface, the second dielectric surface directly bonded to the first dielectric surface of the first die without an intervening adhesive such that the second plurality of conductive features is bonded to the first plurality of conductive features without an intervening adhesive;
a third surface opposite the second dielectric surface; and
a second plurality of microelectronic devices embedded within the second die, the second plurality of microelectronic devices in electrical connection with the second plurality of conductive features; and
a top die provided on the second die, the top die comprising:
a fourth surface provided over the third surface of the second die; and
a top surface opposite the fourth surface,
wherein at least a portion of the top surface of the top die is configured to be interconnected to the optical component located within the first die.
21 . The interconnected stack of claim 20 , wherein the top die comprises a semiconductor die.
22 . The interconnected stack of claim 20 , wherein the interconnected stack does not include conductive features at the top surface of the top die, and
wherein the top die does not comprise conductive vias.
23 . The interconnected stack of claim 20 , wherein the top die is directly bonded to a bonding layer on the second die.
24 . The interconnected stack of claim 20 , wherein the at least a portion of the top surface of the top die is configured to be optically interconnected to the optical component located within the first die.
25 . The interconnected stack of claim 20 , wherein the first plurality of microelectronic devices comprises traces.
26 . The interconnected stack of claim 20 , wherein the first die comprises a fifth dielectric surface opposite the first dielectric surface with a third plurality of conductive features embedded within and exposed at the fifth dielectric surface, and wherein the interconnected stack further comprises a host layer with a sixth surface attached to the fifth surface of the first die.
27 . The interconnected stack of claim 26 , wherein the host layer further comprises:
a fourth plurality of conductive features embedded within and exposed at the sixth surface, the fourth plurality of conductive features in physical and electrical contact with the third plurality of conductive features of the first die;
a third plurality of microelectronic devices embedded within the host layer; and
a plurality of vias electrically connecting the third plurality of microelectronic features with the fourth plurality of conductive features.
28 . The interconnected stack of claim 26 , wherein the host layer has a back surface opposite the sixth surface, the back surface bonded to a terminal.
29 . The interconnected stack of claim 28 , wherein the terminal is in electrical communication with the first plurality of conductive features.
30 . The interconnected stack of claim 29 , wherein the terminal is bonded to another circuit using adhesive.
31 . An interconnected stack comprising:
a first die comprising:
a first dielectric surface;
a first plurality of microelectronic devices embedded within the first die; and
an optical component located within the first die;
a second die directly bonded to the first die, the second die comprising:
a second plurality of microelectronic devices embedded within the second die;
a second dielectric surface directly bonded to the first dielectric surface of the first die without an intervening adhesive such that the second plurality of microelectronic devices is in electrical communication with the first plurality of microelectronic devices; and
a third surface opposite the second dielectric surface; and
a top die provided on the second die, the top die comprising:
a fourth surface provided over the third surface of the second die; and
a top surface opposite the fourth surface,
wherein at least a portion of the top surface of the top die is configured to be interconnected to the optical component located within the first die.
32 . The interconnected stack of claim 31 , wherein the top die comprises a semiconductor die.
33 . The interconnected stack of claim 31 , wherein the interconnected stack does not include conductive features at the top surface of the top die, and wherein the top die does not comprise conductive vias.
34 . The interconnected stack of claim 31 , wherein the top die is directly bonded to a bonding layer on the second die.
35 . The interconnected stack of claim 31 , wherein the at least a portion of the top surface of the top die is configured to be optically interconnected to the optical component located within the first die.