IP Library › Assignment 005270/0725
Patent Assignment
Reel/Frame 005270/0725

Merger Effective on 12/31/1987DE

Recorded: 1989-09-11 Pages: 11
Assignors
Assignee
Covered Properties (160)
Dual Tone Multiple Frequency Generator
Patent: 4,061,886 →
Application: 05/617,955 →
Mosfet Random Access Memory Chip
Patent: 4,156,938 →
Application: 05/644,854 →
Clock Generator and Delay Stage
Patent: 4,061,933 →
Application: 05/644,855 →
Mosfet Buffer for Ttl'logic Input and Method of Operation
Patent: 4,096,402 →
Application: 05/644,856 →
Dynamic Random Access Memory System
Patent: 4,061,999 →
Application: 05/644,857 →
Series Read Only Memory Structure
Patent: 4,142,176 →
Application: 05/726,579 →
Dynamic Random Access Memory System
Patent: 4,061,954 →
Application: 05/741,720 →
Symmetrical Cell Layout for Static Ram
Patent: 4,125,854 →
Application: 05/746,665 →
High Performance Integrated Circuits and Method for Making Same
Patent: 4,135,102 →
Application: 05/816,363 →
Integrated Circuit with Threshold Regulation
Patent: 4,142,114 →
Application: 05/816,364 →
Integrated Circuit with Power Supply Voltage Level Detection
Patent: 4,142,118 →
Application: 05/825,602 →
Depletion Controlled Switch
Patent: 4,204,131 →
Application: 05/840,679 →
One Transistor-One Capacitor Memory Cell
Patent: 4,392,210 →
Application: 05/937,272 →
Method for Making a Semiconductor Device
Patent: 4,179,311 →
Application: 05/945,361 →
Extremely Low Current Load Device for Integrated Circuit
Patent: 4,251,876 →
Application: 05/957,587 →
Integrated Circuit Chip Telephone Communication System
Patent: 4,315,108 →
Application: 06/002,424 →
Extremely Low Current Load Device for Integrated Circuit
Patent: 4,297,721 →
Application: 06/043,419 →
Method of Making an Extremely Low Current Load Device for Integrated Circuit
Patent: 4,290,185 →
Application: 06/043,420 →
Programmable Read Only Memory Integrated Circuit with Bit-Check and Deprogramming Modes and Methods for Programming and Testing Said Circuit
Patent: 4,301,535 →
Application: 06/053,880 →
And-Gate Clock
Patent: 4,289,973 →
Application: 06/066,147 →
High Voltage Clock Generator
Patent: 4,354,123 →
Application: 06/066,148 →
Refresh Counter
Patent: 4,296,480 →
Application: 06/066,149 →
Low Sensitivity Switched-Capacitor Ladder Filter Using Monolithic Mos Chip
Patent: 4,338,571 →
Application: 06/105,004 →
Method for Making a Depletion Controlled Switch
Patent: 4,317,275 →
Application: 06/110,949 →
Dynamic Ratioless Circuitry for Random Logic Applications
Patent: 4,316,106 →
Application: 06/111,274 →
Memory Protection System
Patent: 4,332,009 →
Application: 06/113,621 →
Mos Memory Cell
Patent: 4,308,594 →
Application: 06/117,223 →
Timing of Active Pullup for Dynamic Semiconductor Memory
Patent: 4,291,392 →
Application: 06/119,292 →
Low-Power Battery Backup Circuit for Semiconductor Memory
Patent: 4,288,865 →
Application: 06/119,293 →
Backup Power Circuit for Biasing Bit Lines of a Static Semiconductor Memory
Patent: 4,337,524 →
Application: 06/119,538 →
Bandgap Voltage Reference Employing Sub-Surface Current Using a Standard Cmos Process
Patent: 4,317,054 →
Application: 06/119,539 →
Single Electrode Sense Circuit for Charge-Coupled Transversal Filters
Patent: 4,330,769 →
Application: 06/119,578 →
Active Refresh Circuit for Dynamic Mos Circuits
Patent: 4,291,393 →
Application: 06/120,268 →
Block Redundancy for Memory Array
Patent: 4,281,398 →
Application: 06/120,929 →
Three Layer Floating Gate Memory Transistor with Erase Gate Over Field Oxide Region
Patent: 4,331,968 →
Application: 06/130,853 →
High Density Read Only Memory
Patent: 4,328,563 →
Application: 06/136,588 →
Analog/Digital Converter Utililizing a Single Column of Analog Switches
Patent: 4,354,175 →
Application: 06/145,550 →
Variable Delay Circuit for Emulating Word Line Delay
Patent: 4,425,633 →
Application: 06/194,334 →
Method of Making a Plurality of Mosfets Having Different Threshold Voltages
Patent: 4,472,871 →
Application: 06/208,378 →
Decoder Circuit for Semiconductor Memory
Patent: 4,360,901 →
Application: 06/227,053 →
Shared Quiet Line Flip-Flop
Patent: 4,406,954 →
Application: 06/227,054 →
Semiconductor Memory Decoder with Nonselected Row Line Hold Down
Patent: 4,360,902 →
Application: 06/231,240 →
Single Chip Mos/Lsi Microcomputer
Patent: 4,348,743 →
Application: 06/234,174 →
Integrated Circuit Package
Patent: 4,342,069 →
Application: 06/234,400 →
Refresh Counter Test
Patent: 4,347,589 →
Application: 06/235,180 →
Placement of Clock Circuits for Semiconductor Memory
Patent: 4,506,347 →
Application: 06/236,239 →
Low Power Differential Amplifier
Patent: 4,379,267 →
Application: 06/252,972 →
Delay Stage for a Clock Generator
Patent: 4,379,974 →
Application: 06/261,121 →
Data Compression, Encryption, and in-Line Transmission System
Patent: 4,386,416 →
Application: 06/261,123 →
Socket for Housing a Plurality of Integrated Circuits
Patent: 4,364,620 →
Application: 06/261,236 →
Tone Generator Circuit
Patent: 4,390,754 →
Application: 06/265,983 →
Buffer Circuit for Semiconductor Memory
Patent: 4,347,448 →
Application: 06/265,984 →
Method for Fabricating a Semiconductor Read Only Memory
Patent: 4,356,042 →
Application: 06/265,986 →
Clocking System for a Self-Refreshed Dynamic Memory
Patent: 4,360,903 →
Application: 06/265,994 →
Low Voltage Low Power Rc Oscillator Circuit
Patent: 4,479,097 →
Application: 06/270,528 →
Circuit for Detecting Loss of Supply Voltage
Patent: 4,386,281 →
Application: 06/273,841 →
On-Hook/Off-Hook Detector Circuit
Patent: 4,337,378 →
Application: 06/273,842 →
Multipin Coupler
Patent: 4,387,946 →
Application: 06/273,843 →
Row Driver Circuit for Semiconductor Memory
Patent: 4,338,679 →
Application: 06/273,845 →
Single Layer Burn-in Tape for Integrated Circuit
Patent: 4,386,389 →
Application: 06/273,847 →
Integrated Circuit Package
Patent: 4,441,119 →
Application: 06/273,848 →
Current Limiting Mos Transistor Driver Circuit
Patent: 4,347,447 →
Application: 06/275,056 →
Semiconductor Memory Cell Margin Test Circuit
Patent: 4,418,403 →
Application: 06/275,057 →
Tape Burn-in Circuit
Patent: 4,380,805 →
Application: 06/277,652 →
Reference Voltage Circuit
Patent: 4,359,680 →
Application: 06/278,905 →
Circuit for Generating Analog Signals
Patent: 4,446,436 →
Application: 06/278,906 →
Static Ram Memory Cell
Patent: 4,380,055 →
Application: 06/278,907 →
Dynamic Random Access Memory
Patent: 4,397,003 →
Application: 06/282,181 →
Method and Apparatus for Aligning an Integrated Circuit
Patent: 4,406,949 →
Application: 06/282,858 →
Method and Apparatus for Focusing a Laser Beam on an Integrated Circuit
Patent: 4,358,659 →
Application: 06/282,865 →
Mosfet Fabrication Process for Reducing Overlap Capacitance and Lowering Interconnect Impedance
Patent: 4,445,266 →
Application: 06/290,833 →
Semiconductor Memory for Use in Conjunction with Error Detection and Correction Circuit
Patent: 4,412,314 →
Application: 06/292,122 →
Method and Apparatus for Programmed Circuit Elements in Integrated Circuits
Patent: 4,387,503 →
Application: 06/292,512 →
Test Apparatus for Circuits Having a Multiplex Input/Output Terminal Including a Load Connected to the Terminal Together with Circuitry for Monitoring the Current Flow Through the Load When Inputting a Signal to the Terminal
Patent: 4,472,678 →
Application: 06/292,918 →
Multi-Bit Read Only Memory Circuit
Patent: 4,388,702 →
Application: 06/294,831 →
Semiconductor Memory Address Buffer Having Power Down Mode
Patent: 4,385,369 →
Application: 06/294,841 →
Semiconductor Memory Circuit with Depletion Data Transfer Transistor
Patent: 4,389,705 →
Application: 06/294,842 →
Self-Loading Bootstrap Circuit
Patent: 4,398,270 →
Application: 06/300,609 →
Semiconductor Memory Circuit
Patent: 4,388,705 →
Application: 06/307,641 →
Lead Frame Embedding Fixture
Patent: 4,386,463 →
Application: 06/308,492 →
Temperature Compensated Reference Circuit
Patent: 4,419,594 →
Application: 06/319,045 →
Nonvolatile Static Random Access Memory Cell
Patent: 4,460,978 →
Application: 06/322,915 →
Mos Bootstrapped Buffer for Voltage Level Conversion with Fast Output Rise Time
Patent: 4,408,136 →
Application: 06/328,375 →
Bootstrapped Clock Driver Including Delay Means
Patent: 4,472,644 →
Application: 06/329,586 →
Loop Length Compensation Circuit
Patent: 4,453,037 →
Application: 06/335,142 →
Sidetone Circuit
Patent: 4,445,002 →
Application: 06/335,144 →
Low Loop Current Switch Latch Circuit
Patent: 4,439,637 →
Application: 06/335,145 →
Current Supplementation Circuit for Power Supply
Patent: 4,408,153 →
Application: 06/335,147 →
Directly-Coupled and Capacitively Coupled Nonvolatile Static Ram Cell
Patent: 4,408,303 →
Application: 06/335,160 →
Multi-Bit Read Only Memory Circuit
Patent: 4,495,602 →
Application: 06/335,164 →
Vertical Semiconductor Furnace
Patent: 4,412,812 →
Application: 06/335,170 →
Compensated Amplifier Having Pole Zero Tracking
Patent: 4,458,212 →
Application: 06/335,628 →
Dynamic Random Access Memory Cell with Increased Signal Margin
Patent: 4,491,936 →
Application: 06/346,605 →
Bit Operation Method and Circuit for Microcomputer
Patent: 4,451,885 →
Application: 06/353,602 →
Functional Command for Semiconductor Memory
Patent: 4,507,761 →
Application: 06/370,172 →
Mosfet Random Access Memory Chip
Patent: 4,477,739 →
Application: 06/402,395 →
Offset Voltage Compensation Circuit
Patent: 4,492,927 →
Application: 06/430,446 →
User Reprogrammable Programmed Logic Array
Patent: 4,490,812 →
Application: 06/431,466 →
Fabrication of Isolation Oxidation for Mos Circuit
Patent: 4,407,696 →
Application: 06/453,214 →
Mos Random Access Memory Cell with Nonvolatile Storage
Patent: 4,510,584 →
Application: 06/454,418 →
Sense Amplifier for a Dynamic Ram
Patent: 4,669,063 →
Application: 06/454,754 →
Mos Transistor Circuits Having Matched Channel Width and Length Dimensions
Patent: 4,714,840 →
Application: 06/454,778 →
Address-Controlled Automatic Bus Arbitration and Address Modification
Patent: 4,649,471 →
Application: 06/471,095 →
A Method of Forming a Mosfet with Both Improved Breakdown Resistance and Less Hot-Electron Effects
Patent: 4,499,652 →
Application: 06/532,259 →
Recessed Metallization
Patent: 4,508,815 →
Application: 06/548,465 →
Power Supply Control for Integrated Circuit
Patent: 4,451,742 →
Application: 06/560,253 →
Integrated-Circuit Leadframe Adapted for a Simultaneous Bonding Operation
Patent: 4,722,060 →
Application: 06/592,144 →
Manipulation and Handling of Integrated Circuit Dice
Patent: 4,626,167 →
Application: 06/592,151 →
Chip Selection in Automatic Assembly of Integrated Circuit
Patent: 4,627,787 →
Application: 06/592,156 →
Automatic Assembly of Integrated Circuits
Patent: 4,627,151 →
Application: 06/592,185 →
Go/No Go Margin Test Circuit for Semiconductor Memory
Patent: 4,502,140 →
Application: 06/599,208 →
Zero Power Random Access Memory Package
Patent: 288,922 →
Application: 06/601,906 →
Fet Differential Amplifier
Patent: 4,716,380 →
Application: 06/633,375 →
Clamping Circuit Finding Particular Application Between a Single Sided Output of a Computer Memory and a Differental Amplifier Sensing Circuit
Patent: 4,634,890 →
Application: 06/648,092 →
Trip-Point Clamping Circuit for a Semiconductor Device
Patent: 4,626,713 →
Application: 06/648,093 →
Cmos Powerless Rom Code Mask Option Select
Patent: 4,687,989 →
Application: 06/667,182 →
Bit Line Gain Circuit for Read Only Memory
Patent: 4,661,926 →
Application: 06/674,103 →
Power Conserving Cmos Reference Voltage Source
Patent: 4,628,250 →
Application: 06/674,104 →
A Method of Fabricating Regions of a Bipolar Microwave Integratable Transistor
Patent: 4,651,410 →
Application: 06/683,152 →
Signal Sorting Element with Internal Signal Address Value Sorting Criterion
Patent: 4,758,981 →
Application: 06/686,180 →
Method and Network for Transmitting Addressed Signal Samples from Any Network Input to an Addressed Network Output
Patent: 4,685,128 →
Application: 06/686,314 →
High-Speed Parity Check Circuit
Patent: 4,646,306 →
Application: 06/686,331 →
Error-Correcting Circuit Having a Reduced Syndrome Word
Patent: 4,649,540 →
Application: 06/686,333 →
Multiple-Input Sense Amplifier with Two Cmos Differential Stages Driving a High-Gain Stage
Patent: 4,649,301 →
Application: 06/689,251 →
Cmos Memory Arrangement with Reduced Data Line Capacitance
Patent: 4,636,988 →
Application: 06/689,254 →
Programmable Mask or Reticle
Patent: 4,653,860 →
Application: 06/689,255 →
Cmos Memory Arrangement
Patent: 4,627,031 →
Application: 06/689,256 →
Sense Amplifier Bit Line Isolation Scheme
Patent: 4,651,305 →
Application: 06/700,571 →
Low Active-Power Address Buffer
Patent: 4,677,593 →
Application: 06/746,806 →
Method of Branding a Semiconductor Chip Package
Patent: 4,655,134 →
Application: 06/756,461 →
Method of Late Programing a Read Only Memory
Patent: 4,649,629 →
Application: 06/760,206 →
Semiconductor Chip Power Supply Monitor Circuit Arrangement
Patent: 4,714,843 →
Application: 06/771,319 →
Non-Volatile Memory Cell
Patent: 4,651,303 →
Application: 06/778,640 →
Programmable Access Memory
Patent: 4,835,733 →
Application: 06/781,584 →
Single- Chip Microcomputer with Internal Time- Multiplexed Address\ Data/Interrupt Bus
Patent: 4,626,985 →
Application: 06/783,261 →
Improved Nonvolatile Memory Circuit Using a Dual Node Floating Gate Memory Cell
Patent: 4,685,083 →
Application: 06/783,493 →
Method of Making a Trench Capacitor and Dram Memory Cell
Patent: 4,679,300 →
Application: 06/785,195 →
High Speed nor Gate
Patent: 4,645,952 →
Application: 06/797,546 →
Memory Cell Leakage Detection Circuit
Patent: 4,685,086 →
Application: 06/798,040 →
Integrated Circuit Package with Battery Housing
Patent: 4,998,888 →
Application: 06/846,510 →
Process of Forming Integrated Circuits with Contact Pads in a Stardard Array
Patent: 4,685,998 →
Application: 06/917,040 →
Doped Semiconductor Vias to Contacts
Patent: 4,722,913 →
Application: 06/920,251 →
Chip Selection in Automatic Assembly of Integrated Circuit
Patent: 4,759,675 →
Application: 06/923,315 →
Offset Bending of Curvaceously Planar Radiating Leadframe Leads in Semiconductor Chip Packaging
Patent: 4,743,956 →
Application: 06/941,691 →
Packaging Technique for Batteries
Patent: 4,759,771 →
Application: 07/053,141 →
Method of Making Mosfet by Multiple Implantations Followed by a Diffusion Step
Patent: 32,800 →
Application: 07/053,269 →
Screening of Gate Oxides on Semiconductors
Patent: 4,760,032 →
Application: 07/055,335 →
Method of Improving the Corrosion Resistance of Aluminum Contacts on Semiconductors
Patent: 4,818,727 →
Application: 07/065,344 →
Robotic Hand for Transporting Semiconductor Wafer Carriers
Patent: 4,816,732 →
Application: 07/086,278 →
Process for Manufacturing Ldd Cmos Devices
Patent: 4,771,014 →
Application: 07/099,144 →
Defective Element Disabling Circuit Having a Laser-Blown Fuse
Patent: 4,829,481 →
Application: 07/112,255 →
Rom Having Bit Lines Interlaced with Column Lines and Cell Column Selection According to Regularly Interlaced Logical Fields
Patent: 4,758,989 →
Application: 07/119,210 →
Screening of Gate Oxides on Semiconductors
Patent: 4,860,079 →
Application: 07/167,546 →
Uniform Leadframe Carrier
Patent: 4,815,595 →
Application: 07/170,069 →
Method of Improving the Corrosion Resistance of Aluminum Contacts on Semiconductors
Patent: 5,119,167 →
Application: 07/261,175 →
Universal Leadframe Carrier
Patent: 5,111,935 →
Application: 07/265,231 →
Pad Oxide Protect Sealed Interface Isolation Process
Patent: 4,981,813 →
Application: 07/279,343 →
Manipulation and Handling of Integrated Circuit Dice
Patent: 4,915,565 →
Application: 07/325,014 →
Integrated Circuit Package with Battery Housing
Patent: 5,055,704 →
Application: 07/389,538 →
Battery Package for Integrated Circuits
Patent: 4,992,987 →
Application: 07/397,643 →
Related Assignments (3)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignors Interest. Feb 20, 1981
From: EATON SARGENT S. JR.
To: MOSTEK CORPORATION
Reel/Frame 003829/0619 →
Assignment of Assignors Interest. Nov 4, 1987
From: CTU OF DELAWARE, INC., FORMERLY MOSTEK CORPORATION
To: THOMSON COMPONENTS-MOSTEK CORPORATION
Reel/Frame 004810/0156 →
Change of Name Effective on 11/15/1987 Sep 11, 1989
From: THOMSON COMPONENTS-MOSTEK CORPORATION
To: SGS-THOMSON MICROELECTRONICS, INC.
Reel/Frame 005270/0714 →