IP Library › Assignment 010884/0394
Patent Assignment
Reel/Frame 010884/0394

Amend to Add Properties Recorded on Reel 10247, Frame 0043.

Recorded: 1999-09-27 Pages: 19
Assignor
HARRIS CORPORATION
Executed: 1999-08-13
Assignee
INTERSIL CORPORATION
2401 PALM BAY ROAD N.E., PALM BAY, FLORIDA, 32905
Covered Properties (158)
Bias Current Modulation for Differentially Coupled Transistor Circuit
Application: 07/447,275 →
Thin, Dielectrically Isolated Island Resident Transistor Structure Having Low Collector Resistance
Application: 07/461,715 →
Wafer Bonding Using Trapped Oxidizing Vapor
Application: 07/476,322 →
Ferromagnetic Element with Temperature Regulation
Patent: 33,644 →
Application: 07/548,866 →
Silicon on Diamond Circuit Structure
Application: 07/789,219 →
Negative Biasing of Isolation Trench Fill to Attract Mobile Positive Ions Away from Bipolar Device Regions
Application: 07/811,169 →
Half-Band Filter and Method
Application: 07/930,167 →
Diamond Insulator Devices and Method of Fabrication
Application: 08/042,299 →
Semicondcuctor Device with Increased Maximum Terminal Voltage Voltage
Patent: 6,008,512 →
Application: 08/053,243 →
Trench Isolation Stress Relief
Application: 08/083,080 →
Comfet Switch and Method
Application: 08/153,907 →
Semiconductor Package and Method with Vertically Extended Electrode Leads
Application: 08/202,168 →
Bridge Control Circuit and Method
Application: 08/261,996 →
Cmos Integrated Circuit Architecture Incorporating Deep Implanted Emitter Region to Form Auxiliary Bipolar Transistor
Patent: 6,350,640 →
Application: 08/276,290 →
Jfet Structures for Semiconductor Devices with Complementary Bipolar Transistors and Method of Making
Application: 08/279,024 →
Capacitor Structure in a Bonded Wafer and Method of Fabrication
Application: 08/326,037 →
Bonded Wafer Processing
Application: 08/335,600 →
Circuit and Method for Synchronizing Outputs of Two Simultaneously Transmitting Devices in a Multiplexed Communication System
Application: 08/396,616 →
Sine/Cosine Generator and Method
Patent: 36,388 →
Application: 08/400,811 →
Complementary Multiplexer with Low Disabled-Output Capacitance, and Method
Application: 08/405,869 →
Method and Circuit for Preventing Forward Bias of a Parasitic Diode Inan Integrated Circuit
Application: 08/439,249 →
Plasma Cleaning Method for Improved Ink Brand Permanency on Ic Packages
Application: 08/487,746 →
Bandgap Voltage Generator
Application: 08/496,965 →
Low Distortion Feedback Ic Amplifier and Method
Application: 08/502,636 →
Current-Controlled Carrier Tracking Filter for Improved Spurious Signal Suppression
Patent: 5,953,379 →
Application: 08/606,958 →
Process Forming Trench Isolation Device
Patent: 5,933,746 →
Application: 08/637,937 →
Pre-Bond Cavity Air Bridge
Patent: 5,949,144 →
Application: 08/650,762 →
Semiconductor Packaging Apparatus
Patent: 5,965,933 →
Application: 08/654,316 →
Integrated Circuit Air Bridge Structures and Methods of Fabricating Same
Patent: 6,492,705 →
Application: 08/658,010 →
Up-Conversion Mechanism Employing Side Libe-Selective Pre- Distortion Felter and Frequency Repleca-Selecting Bandpass Filter Respectively Enstalled Upstream and Downstream of Digital- to-Analog Converter
Patent: 5,930,301 →
Application: 08/671,025 →
Negative Biasing of Isolation Trench Fill to Attract Mobile Positive Ions Away from Bipolar Device Regions
Application: 08/674,585 →
Analog-To-Digital Converter and Method of Fabrication
Patent: 5,994,755 →
Application: 08/739,898 →
Method of Metalizing a Semiconductor Power Device Ceramic Member
Application: 08/759,865 →
Interpolator Using a Plurality of Polynomial Equations and Associated Methods
Patent: 5,949,695 →
Application: 08/781,736 →
Integrated Circuit with Thin Film Resistors and a Method for Co-Patterning Thin Film Resistors with Different Compositions
Patent: 5,976,944 →
Application: 08/799,793 →
High Data Rate Spread Spectrum Transceiver and Associated Methods
Patent: 5,982,807 →
Application: 08/819,846 →
Contact Regions for Narrow Trenches in Semiconductor Devices and Method
Patent: 5,962,908 →
Application: 08/845,214 →
Circuit and Method for Synchronizing Outputs of Two Simultaneously Transmitting Devices in a Multiplexed Communication System
Patent: 6,108,352 →
Application: 08/854,681 →
Reduce Width, Differentially Doped Vertical Jfet Device
Patent: 5,945,699 →
Application: 08/855,385 →
One Mask, Power Semiconductor Device Fabrication Process
Patent: 6,110,763 →
Application: 08/861,562 →
Level Shifter Stage with Punch Through Diode
Patent: 5,929,502 →
Application: 08/868,813 →
Punch-Through Diodes and Applications
Patent: 5,929,503 →
Application: 08/868,815 →
Dynamic Regulator for a Dc-to-Dc Power Converter and Related Methods
Patent: 5,926,384 →
Application: 08/883,624 →
Low Voltage Rf Amplifier and Mixed with Single Bias Block and Method
Patent: 6,018,270 →
Application: 08/884,635 →
Silicon-Glass Bonded Wafers
Patent: 5,994,204 →
Application: 08/884,787 →
Method for Forming Complementary Wells and Self-Aligned Trench with a Single Mask
Patent: 5,956,583 →
Application: 08/885,707 →
Method of Making a Mos-Gated Semiconductor Device with a Single Diffusion
Patent: 6,080,614 →
Application: 08/885,877 →
Lifetime Control for Semiconductor Devices
Patent: 6,054,369 →
Application: 08/885,878 →
Trench Contact Process
Patent: 6,110,799 →
Application: 08/885,879 →
A Method of Fabricating Umos Semiconductor Devices Using a Self-Aligned, Reduced Mask Process
Patent: 5,940,689 →
Application: 08/885,921 →
Semiconductor Structures with Trench Contacts
Patent: 6,037,628 →
Application: 08/885,922 →
Hermetic Thin Oack Semiconductor Device
Patent: 6,157,076 →
Application: 08/885,923 →
Bonded Wafer Processing with Metal Silicidation
Application: 08/915,841 →
Digital-To-Analog Converter Including Current Cell Matrix with Enhanced Linearity and Associated Methods
Patent: 5,949,362 →
Application: 08/916,569 →
Electrical System with Small Signal Suppression Circuitry
Patent: 6,060,913 →
Application: 08/918,307 →
Constant Slew Rate Amplifier
Patent: 6,040,707 →
Application: 08/929,734 →
Knock Sensor System for Detecting and Responding to a Disconnect Condition
Patent: 5,942,677 →
Application: 08/931,340 →
Protection Device for Solid State Switched Power Electornics
Patent: 5,995,349 →
Application: 08/944,513 →
Inverted Thin Film Resistor
Patent: 6,034,411 →
Application: 08/960,337 →
Schmitt Trigger-Configured Esd Protection Circuit
Patent: 5,978,192 →
Application: 08/964,672 →
High Voltage Mosfet Structure
Patent: 6,081,009 →
Application: 08/966,867 →
Negative Biasing of Isolation Trench Fill to Attract Mobile Positive Ions Away from Bipolar Device Regions
Patent: 6,051,474 →
Application: 08/968,618 →
Low Distortion Current Feedback Amplifier with Dynamic Biasing
Patent: 5,977,829 →
Application: 08/972,887 →
Monolithic Class D Amplifier
Patent: 5,973,368 →
Application: 08/973,769 →
Multiple Output Dc-to-Dc Converter Having Enhanced Noise Margin and Related Methods
Patent: 6,058,030 →
Application: 08/974,862 →
Rf Communications System Operable in the Presence of a Repetitive Interference Source and Related Methods
Patent: 6,006,071 →
Application: 09/006,071 →
Class D Amplifier with Scaled Clock and Related Methods
Patent: 5,959,501 →
Application: 09/007,326 →
Adjustable Phase Clock Circuit Using Same and Related Methods
Patent: 5,990,713 →
Application: 09/019,241 →
Class D Amplifier with Reduced Clock Requirement and Related Methods
Patent: 6,014,055 →
Application: 09/020,178 →
Optimum Placement of Bypass Capacitors in a Network for Improving Electro-Magnetic Interference Response
Patent: 6,091,274 →
Application: 09/024,099 →
Trench Emitter Controlled Thyristor
Patent: 5,998,811 →
Application: 09/024,117 →
Ring Generator
Patent: 6,167,131 →
Application: 09/027,257 →
Igbt Gate Drive Circuit with Short Circuit Protection
Patent: 6,275,093 →
Application: 09/030,871 →
Advanced Methods for Making Semiconductor Devices by Low Temperature Direct Bonding
Patent: 6,153,495 →
Application: 09/036,815 →
Devices Formable by Low Temperature Direct Bonding
Patent: 6,274,892 →
Application: 09/036,838 →
Methods for Making Semiconductor Devices by Low Temperature Direct Bonding
Patent: 6,194,290 →
Application: 09/037,723 →
Semiconductor Power Pack
Patent: 6,060,795 →
Application: 09/040,112 →
Sample-And-Hold Circuit Having Reduced Subthreshold Conduction Effects and Related Methods
Patent: 6,069,502 →
Application: 09/055,528 →
Sample-And-Hold Circuit Having Reduced Parasitic Diode Effects and Related Methods
Patent: 6,002,277 →
Application: 09/055,561 →
Sample-And-Hold Circuit Having Reduced Amplifier Offset Effects and Related Methods
Patent: 6,016,067 →
Application: 09/055,562 →
Devices with Patterned Wells and Method for Forming Same
Patent: 6,555,894 →
Application: 09/062,964 →
Publication: US 2002/0158312
Sc-2 Based Pre-Thermal Treatment Wafer Cleaning Process
Patent: 5,932,022 →
Application: 09/064,029 →
Battery Switching Subscriber Loop Interface Circuit
Patent: 6,233,335 →
Application: 09/079,304 →
Defect Gettering by Induced Stress
Patent: 5,929,508 →
Application: 09/082,892 →
Methods of Forming Power Semiconductor Devices Having Merged Split-Well Body Regions Therein
Patent: 6,121,089 →
Application: 09/092,334 →
Trench Mos Gate Device
Patent: 6,368,920 →
Application: 09/096,217 →
High Performance Heat Exchanger and Method
Patent: 6,196,307 →
Application: 09/098,517 →
Decapsulating Method and Apparatus for Integrated Circuit Packages
Patent: 6,054,012 →
Application: 09/106,622 →
Heat Exchanging Chassis
Patent: 6,188,575 →
Application: 09/107,273 →
Method of Creating a Solderable Metal Layer on Glass or Ceramic
Patent: 6,159,663 →
Application: 09/107,475 →
Semiconductor Device Having Reduced Effective Substrate Resistivity and Associatd Methods
Patent: 6,104,062 →
Application: 09/107,721 →
Linear Voltage Regulator Compatible with Bipolar and Mosfet Pass Devices and Associated Methods
Patent: 6,005,303 →
Application: 09/108,059 →
High Voltage Semiconductor Structure
Patent: 6,066,878 →
Application: 09/108,962 →
Electrostatic Discharge Locating Apparatus and Method
Patent: 6,064,340 →
Application: 09/108,963 →
Flat Power Rack
Patent: 6,057,612 →
Application: 09/109,268 →
Surface Mount Die by Handle Replacement
Patent: 6,114,768 →
Application: 09/110,721 →
Parasitic Current Barriers
Patent: 6,278,186 →
Application: 09/139,932 →
Programmable Subscriber Loop Interface Circuit and Method
Patent: 6,665,398 →
Application: 09/145,182 →
Method of Making Shallow Well Mosfet Structure
Patent: 6,107,127 →
Application: 09/145,513 →
Analog-To-Digital Converter Having Enhanced Accuracy Gain Stage, and Associated Devices and Methods
Patent: 6,107,950 →
Application: 09/148,955 →
Digital-To-Analog Converter Including Current Sources Operable in a Predetermined Sequence and Associated Methods
Patent: 6,118,398 →
Application: 09/149,154 →
Device Containing Sample Preparation Sites for Transmission Electron Microscopic Analysis and Processes of Formation and Use
Patent: 6,140,652 →
Application: 09/150,429 →
Driver Circuit Having Load-Independent Slew Rate
Patent: 6,172,541 →
Application: 09/152,420 →
Pulsed Beacon-Based Interference Reduction Mechanism for Wireless Communication Networks
Patent: 6,377,608 →
Application: 09/163,802 →
Semiconductor Integrated Circuit with Temporarily Interconnected Bond Pads
Application: 09/166,416 →
Process for Forming High Voltage Junction Termination Extension Oxide
Patent: 6,309,952 →
Application: 09/167,177 →
Publication: US 2001/0041461
Power Module with Lowered Inductance and Reduced Voltage Overshoots
Patent: 6,069,403 →
Application: 09/167,203 →
Variable Frequency Class D Modulator with Built in Soft Clipping and Frequency Limiting
Patent: 6,107,875 →
Application: 09/173,111 →
Overcurrent Sensing Circuit and Self Adjusting Blanking.
Patent: 6,108,182 →
Application: 09/183,453 →
Start-Up Circuit for Self Oscillating Class D Modulator
Patent: 6,118,336 →
Application: 09/183,879 →
Integrated Circuit Air Bridge Structures and Methods of Fabricating Same
Patent: 6,211,056 →
Application: 09/199,292 →
Current Limited, Thermally Protected, Power Device
Patent: 6,055,149 →
Application: 09/203,700 →
Semiconductor Packaging Method
Patent: 6,114,191 →
Application: 09/204,904 →
Apparatus and Method for Testing Subscriber Loop Interface Circuits
Patent: 6,519,322 →
Application: 09/208,457 →
Dc-To-Dc Converter with Inductor Current Sensing and Related Methods
Patent: 5,982,160 →
Application: 09/220,780 →
Wireless Local Area Network Spread Spectrum Transceiver with Multipath Mitigation
Patent: 6,678,310 →
Application: 09/231,184 →
Spread Spectrum Transceiver for Use in Wireless Local Area Network and Having Multipath Mitigation
Patent: 6,603,801 →
Application: 09/231,228 →
Method of Performing Antenna Diversity in Spread Spectrum in Wireless Local Area Network
Patent: 6,563,858 →
Application: 09/231,608 →
Frequency Dependent Resistive Element
Patent: 5,999,080 →
Application: 09/246,815 →
Complementary Multiplexer with Low Disabled-Output Capacitance, and Method
Patent: 6,114,896 →
Application: 09/247,510 →
Method for Forming a Bonded Substrate Containing a Planar Intrinsic Gettering Zone and Substrate Formed by Said Method
Patent: 6,255,195 →
Application: 09/255,231 →
Mos-Gated Device Having a Buried Gate and Process for Forming Same
Patent: 6,351,009 →
Application: 09/260,411 →
Feedback-Controlled Low Voltage Current Sink/Source
Patent: 6,172,556 →
Application: 09/261,981 →
Integrated Circuit with Deep Trench Having Multiple Slopes
Patent: 6,198,150 →
Application: 09/266,066 →
Method for Fabricating Electrostatic Discharge Protection Device
Patent: 6,051,457 →
Application: 09/268,605 →
Wafer Trench Article and Process
Patent: 6,365,953 →
Application: 09/283,530 →
Publication: US 2001/0045614
High Density Mos-Gated Power Device and Process for Forming Same
Patent: 6,188,105 →
Application: 09/283,531 →
Power Trench Mos-Gated Device and Process for Forming Same
Application: 09/283,536 →
Publication: US 2001/0001494
Power Mos Device with Increased Channel Width and Process for Forming Same
Patent: 6,218,701 →
Application: 09/303,270 →
Process for Forming Mos-Gated Devices Having Self-Aligned Trenches
Patent: 6,238,981 →
Application: 09/307,879 →
Laser Decapsulation Method
Patent: 6,335,208 →
Application: 09/307,896 →
Mos-Gated Power Device Having Extended Trench and Doping Zone and Process for Forming Same
Patent: 6,198,127 →
Application: 09/314,323 →
Bonded Wafer with Metal Silicidation
Patent: 6,909,146 →
Application: 09/316,580 →
Trench-Gated Device Having Trench Walls Formed by Selective Epitaxial Growth and Process for Forming Device
Patent: 6,373,098 →
Application: 09/318,334 →
Low Voltage Dual-Well Mos Device Having High Ruggedness, Low on-Resistance, and Improved Body Diode Reverse Recovery
Patent: 6,137,139 →
Application: 09/324,553 →
Power Device
Patent: 6,078,077 →
Application: 09/330,437 →
Power Module with Lowered Inductance and Reduced Voltage Overshoots
Patent: 6,140,152 →
Application: 09/334,098 →
Self-Supported Ultrathin Silicon Wafer Process
Patent: 6,162,702 →
Application: 09/334,835 →
Defect Gettering by Induced Stress
Patent: 6,274,460 →
Application: 09/334,987 →
Current-Controlled Carrier Tracking Filter for Improved Spuriou Signal Suppression
Patent: 6,233,293 →
Application: 09/334,998 →
Sc-2 Based Pre-Thermal Treatment Wafer Cleaning Process
Application: 09/335,113 →
Publication: US 2002/0189640
Semiconductor Device Gate Structure for Thermal Overload Protection
Patent: 6,236,088 →
Application: 09/338,891 →
Method of Forming an Integrated Resistive Contacts with Mobility Spoiling Ions Including High Resistivity Contacts and Low Resistivity Silicide Contacts
Patent: 6,403,472 →
Application: 09/339,274 →
Backmetal Drain Terminal with Low Stress and Thermal Resistance
Patent: 6,211,550 →
Application: 09/339,356 →
Dual Mode Class D Amplifiers
Patent: 6,587,670 →
Application: 09/342,376 →
Rake Receiver with Embedded Decision Feedback Equalizer
Patent: 6,233,273 →
Application: 09/342,583 →
Brushless Multipass Silicon Wafer Cleaning Process for Post Chemical Mechanical Polishing Using Immersion
Patent: 6,526,995 →
Application: 09/342,948 →
Method of Manufacturing a Plated Electronic Termination
Patent: 7,174,626 →
Application: 09/343,845 →
Publication: US 2002/0029473
Potted Transducer Array with Matching Network in a Multiple Pass Configuration
Patent: 6,314,974 →
Application: 09/344,867 →
Method for Making a Diffused Back-Side Layer on a Bonded-Wafer with a Thick Bond Oxide
Patent: 6,362,075 →
Application: 09/345,261 →
Low Temperature Coefficient Resistor (Tcrl)
Patent: 6,351,021 →
Application: 09/345,929 →
Power Semiconductor Mounting Package Containing Ball Grid Array
Patent: 6,198,166 →
Application: 09/345,930 →
Process for Forming Vertical Semiconductor Device Having Increased Source Contact Area
Patent: 6,214,673 →
Application: 09/350,575 →
Class D Modulator with Digital Current Limit and Load Impedance Sensing Circuits
Application: 60/108,942 →
Class D Amplifier with Very Low Jitter Dead Time
Application: 60/108,943 →
Class D Amplifier with Bandwidth Independent of Load Impedance
Application: 60/109,085 →
Apparatus and Method for Minimizing Currents in Discrete Electrical Devices
Application: 60/127,612 →
Accessing Main Atx Outputs Without Monitoring All Outputs
Application: 60/130,828 →
Related Assignments (25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignors Interest. Dec 7, 1989
From: FURINO, JAMES P. JR.
To: HARRIS CORPORATION
Reel/Frame 005192/0151 →
Assignment of Assignors Interest. Jan 8, 1990
From: BEASOM, JAMES D.; LALCHANDANI, AMRIT K.
To: HARRIS CORPORATION, MELBOURNE, FL
Reel/Frame 005226/0528 →
Assignment of Assignors Interest. Feb 7, 1990
From: SHORT, JOHN P.; MCLACHLAN, CRAIG J.; ROUSE, GEORGE V.; ZIBRIDA, JAMES R.
To: HARRIS CORPORATION, A CORP. OF DE
Reel/Frame 005229/0313 →
Assignment of Assignors Interest. Nov 7, 1991
From: SCHRANTZ, GREGORY A.
To: HARRIS CORPORATION, A DE CORP.
Reel/Frame 005910/0607 →
Assignment of Assignors Interest. Dec 20, 1991
From: BEASOM, JAMES D.
To: HARRIS CORPORATION
Reel/Frame 005969/0846 →
Assignment of Assignors Interest. Feb 14, 1992
From: GAUL, STEPHEN J.
To: HARRIS CORPORATION A CORP. OF DELAWARE
Reel/Frame 006019/0443 →
Assignment of Assignors Interest. Oct 19, 1992
From: YOUNG, WILLIAM RONALD; MANION, CINDY CHARLENE; FROGGE, PERRY WESLEY; DAMEROW, DAVID H.
To: HARRIS SEMICONDUCTOR
Reel/Frame 006288/0109 →
Assignment of Assignor's Interest Apr 2, 1993
From: SCHRANTZ, GREG; LINN, JACK; BELCHER, RICHARD
To: HARRIS CORPORATION
Reel/Frame 006793/0671 →
Assignment of Assignor's Interest Apr 28, 1993
From: BEASOM, JAMES D.
To: HARRIS CORPORATION
Reel/Frame 006551/0017 →
Assignment of Assignor's Interest Jun 24, 1993
From: GAUL, STEPHEN JOSEPH; HEMMENWAY, DONALD FRANK
To: HARRIS CORPORATION
Reel/Frame 006606/0298 →
Corrective Assignment, Original Assignment Recorded at Reel 6288, Frame 009 to Correct Assignee Name on Cover Sheet. Nov 12, 1993
From: YOUNG, WILLIAM RONALD; MANION, CINDY CHARLES; FROGGE, PERRY WESLEY; DAMEROW, DAVID H.
To: HARRIS CORPORATION
Reel/Frame 006763/0175 →
Assignment of Assignor's Interest Nov 17, 1993
From: NEILSON, JOHN MANNING SAVIDGE; DIETZ, WOLFGANG F.W.
To: HARRIS CORPORATION
Reel/Frame 006778/0977 →
Assignment of Assignor's Interest Feb 25, 1994
From: TEMPLE, VICTOR ALBERT KEITH
To: HARRIS CORPORATION
Reel/Frame 006892/0672 →
Assignment of Assignor's Interest Jun 17, 1994
From: FOGG, JOHN K.
To: HARRIS CORPORATION
Reel/Frame 007047/0600 →
Assignment of Assignor's Interest Jul 22, 1994
From: BEASOM, JAMES D.
To: HARRIS CORPORATION
Reel/Frame 007092/0933 →
Assignment of Assignor's Interest Sep 19, 1994
From: FULLER, ROBERT T.; MCCARTY, CHRIS; GASNER, JOHN T.; CHURCH, MICHAEL D.
To: HARRIS CORPORATION
Reel/Frame 007132/0438 →
Assignment of Assignor's Interest Oct 19, 1994
From: LINN, JACK H.; CROFT, GREGG D.
To: HARRIS CORPORATION
Reel/Frame 007196/0681 →
Assignment of Assignor's Interest Mar 17, 1995
From: JUNG, TAEWON
To: HARRIS CORPORATION
Reel/Frame 007399/0868 →
Assignment of Assignor's Interest Apr 4, 1995
From: SFERRAZZA, PAUL K.; HARMON, JOSEPH W.
To: HARRIS CORPORATION
Reel/Frame 007420/0317 →
Assignment of Assignor's Interest May 11, 1995
From: DESHAZO, THOMAS R., JR.
To: HARRIS CORPORATION
Reel/Frame 007483/0915 →
Assignment of Assignor's Interest Jun 7, 1995
From: LINN, JACK; HIGLEY, MIKE M.
To: HARRIS CORPORATION
Reel/Frame 007568/0241 →
Assignment of Assignor's Interest Jul 14, 1995
From: USCATEGUI, GABRIEL J.; WELLS, GLENN
To: HARRIS CORPORATION
Reel/Frame 007607/0209 →
Assignment of Assignor's Interest Sep 28, 1995
From: VULIH, SALOMON; WIETECHA, STANLEY F.; OLMSTEAD, JOHN A.; HOUSTEN, THOMAS D.
To: HARRIS CORPORATION
Reel/Frame 007653/0086 →
Assignment of Assignor's Interest Feb 23, 1996
From: MYERS, BRENT A.; GODFREY, PAUL J.
To: HARRIS CORPORATION
Reel/Frame 007947/0514 →
Assignment of Assignor's Interest Apr 23, 1996
From: BEGLEY, PATRICK A.; HEMMENWAY, DONALD F.; BAJOR, GEORGE; RIVOLI, ANTHONY L.
To: HARRIS CORPORATION
Reel/Frame 007975/0545 →