Interface structures and methods for forming same
A stacked and electrically interconnected structure is disclosed. The stacked structure can include a first element comprising a first contact pad and a second element comprising a second contact pad. The first contact pad and the second contact pad can be electrically and mechanically connected to one another by an interface structure. The interface structure can comprise a passive equalization circuit that includes a resistive electrical pathway between the first contact pad and the second contact pad and a capacitive electrical pathway between the first contact pad and the second contact pad. The resistive electrical pathway and the capacitive electrical pathway form an equivalent parallel resistor-capacitor (RC) equalization circuit.
1. A stacked and electrically interconnected structure comprising:
a first element comprising a first contact pad; and
a second element comprising a second contact pad, the first element and the second element directly bonded to one another without an intervening adhesive,
the first contact pad and the second contact pad being electrically and mechanically connected to one another by an interface structure, the interface structure disposed between a lower surface of the first contact pad and an upper surface of the second contact pad, the interface structure comprising a passive equalization circuit that includes a resistive electrical pathway between the first contact pad and the second contact pad and a capacitive electrical pathway between the first contact pad and the second contact pad, the capacitive electrical pathway comprising a dielectric feature between the first and second contact pads, the resistive electrical pathway at least partially embedded in the dielectric feature.
2. The structure of claim 1 , wherein the resistive electrical pathway comprises a conductive interface feature between the first contact pad and the second contact pad, and wherein the dielectric feature of the capacitive electrical pathway comprises a first dielectric gap between the first contact pad and the second contact pad.
3. The structure of claim 2 , wherein the first dielectric gap is disposed about the conductive interface feature.
4. The structure of claim 2 , wherein the conductive interface feature comprises an elongate interface feature in which a length of the elongate interface feature is greater than a width of the elongate interface feature.
5. The structure of claim 4 , wherein the passive equalizer comprises a second conductive interface feature between the first contact pad and the second contact pad, the second conductive interface feature comprising a second elongate interface feature disposed in a crossing orientation relative to the first conductive interface feature.
6. The structure of claim 5 , wherein the conductive interface feature is directly bonded to the second conductive interface feature without an intervening adhesive.
7. The structure of claim 2 , wherein the capacitive electrical pathway further comprises a second dielectric gap between the conductive interface feature and the second contact pad.
8. The structure of claim 2 , wherein the resistive electrical pathway defines a contact area on at least a portion of the conductive interface feature, and wherein the capacitive electrical pathway defines a capacitive area between overlapping portions of the first contact pad and the second contact pad, the capacitive area being greater than the contact area.
9. The structure of claim 8 , wherein a ratio of the capacitive area to the contact area is at least 50:1.
10. The structure of claim 9 , wherein the ratio is in a range of 150:1 to 50,000:1.
11. The structure of claim 2 , wherein the first dielectric gap comprises silicon oxide.
12. The structure of claim 2 , wherein the first dielectric gap has a dielectric constant in a range of 2 to 9.
13. The structure of claim 2 , wherein the conductive interface feature comprises a metal nitride barrier material.
14. The structure of claim 1 , wherein the first element comprises an integrated device die and the second element comprises an interposer.
15. The structure of claim 14 , wherein the integrated device die comprises one or more communications dies, one or more memory dies, or one or more processor dies.
16. The structure of claim 1 , wherein a major dimension of the first contact pad is in a range of 30 microns to 120 microns.
17. The structure of claim 1 , wherein the resistive electrical pathway has an effective resistance in a range of 5 ohm to 70 ohm.
18. The structure of claim 1 , wherein the capacitive electrical pathway has an effective capacitance in a range of 0.2 pF to 50 pF.
19. The structure of claim 1 , wherein the interface structure comprises an equivalent equalization circuit integrated within the interface structure, the equivalent equalization circuit configured to adjust a frequency response of a channel that includes the equivalent equalization circuit and a lossy transmission line.
20. A method for forming a stacked and electrically interconnected structure, the method comprising:
providing a first element comprising a first contact pad;
providing a second element comprising a second contact pad; and
directly bonding the first element to the second element along a bonding interface without an intervening adhesive to define an interface structure comprising a passive equalization circuit, the passive equalization circuit including a resistive electrical pathway between the first contact pad and the second contact pad and a capacitive electrical pathway between the first contact pad and the second contact pad, the capacitive electrical pathway comprising a dielectric feature between the first and second contact pads, the resistive electrical pathway at least partially embedded in the dielectric feature.
21. The method of claim 20 , wherein the bonding comprises directly bonding the first element to the second element without an intervening adhesive.
22. The method of claim 20 , wherein the capacitor is defined by the first and second contact pads and an intervening dielectric.
23. A stacked and electrically interconnected structure comprising:
a first element; and
a second element directly bonded to the first element along a bonding interface without an intervening adhesive,
wherein one or more passive electronic components are integrally formed between a lower surface of the first element and an upper surface of the second elements along the bonding interface, the one or more passive electronic components extending across the bonding interface between the first and second elements.
24. The structure of claim 23 , wherein the one or more passive electronic components are formed by layers formed on the first element.
25. The structure of claim 23 , wherein the one or more passive electronic components are formed by a combination of layers formed on the first and second elements.
26. The structure of claim 23 , wherein the one or more passive electronic components comprises a resistive electrical pathway in parallel with a capacitive electrical pathway.
27. The structure of claim 26 , wherein the first element has a first contact pad and the second element has a second contact pad, wherein the capacitive electrical pathway comprises a dielectric feature between the first and second contact pads, the resistive electrical pathway at least partially embedded in the dielectric feature.
28. The structure of claim 27 , wherein the resistive electrical pathway comprises a conductive interface feature between the first contact pad and the second contact pad.