Diffused bitline replacement in stacked wafer memory
Techniques are disclosed herein for creating metal BLs in stacked wafer memory. Using techniques described herein, metal BLs are created on a bottom surface of a wafer. The metal BLs can be created using different processes. In some configurations, a salicide process is utilized. In other configurations, a damascene process is utilized. Using metal reduces the resistance of the BLs as compared to using non-metal diffused BLs. In some configurations, wafers are stacked and bonded together to form three-dimensional memory structures.
1. A memory array comprising:
a wafer;
a transistor array disposed in the wafer such that source regions of the transistor array are closer to a first side of the wafer than drain regions of the array, and drain regions of the transistor array are closer to a second side of the wafer than the source regions of the array;
metal bitlines coupled to the source regions;
memory cells coupled to the drain regions;
a second wafer that includes a first surface and a second surface; and
a second transistor array in the second wafer, the second transistor array having memory cells coupled to a first side of the second transistor array and metal bitlines coupled a second side of the second transistor array, the second wafer mechanically and electrically coupled to the first wafer.
2. The memory array of claim 1 , further comprising silicide regions between the source regions and the metal bitlines.
3. The memory array of claim 1 , wherein the metal bitlines are separated by deep trench isolation regions.
4. The memory array of claim 1 , wherein the metal bitlines are separated by high k dielectric regions.
5. The memory array of claim 1 , wherein the metal bitlines comprise one or more of aluminum, copper, or tungsten.
6. The memory array of claim 1 , wherein the metal bitlines are separated from the source regions by a barrier layer.
7. The memory array of claim 1 , further comprising isolation regions extending between adjacent transistors in the transistor array.
8. A method to create a memory array, comprising:
forming an array of transistors in a wafer such that source regions of the array are closer to a first side of the wafer than drain regions of the array, and drain regions of the array are closer to a second side of the wafer than the source regions of the array;
forming an array of memory cells coupled to the drain regions;
forming metal bitlines coupled to the source regions;
forming a second array of transistors in a second wafer such that source regions of the second array are closer to a first side of the second wafer than drain regions of the second array, and drain regions of the second array are closer to a second side of the second wafer than the source regions of the second array;
forming a second array of memory cells coupled to the drain regions of the second array;
forming second metal bitlines coupled to the source regions of the second array; and
bonding the wafer to the second wafer.
9. The method of claim 8 , further comprising:
epitaxially growing silicon on diffused bitlines.
10. The method of claim 8 , further comprising reducing a thickness of a layer defined by a bottom wafer surface and a bottom transistor surface of the array of transistors.
11. The method of claim 10 , further comprising performing one or more of doping of diffused bitlines from the bottom wafer surface or epitaxially growing silicon on the diffused bitlines.
12. The method of claim 8 , further comprising forming isolation areas between individual transistors and depositing metal within the isolation areas.
13. The method of claim 8 , wherein forming the metal bitlines comprises forming a salicide on a bottom wafer surface before forming the metal bitlines.
14. The method of claim 8 , wherein forming the metal bitlines comprises
forming channels between a bottom transistor surface of the array of transistors and a bottom wafer surface; and
depositing metal within the channels.
15. A memory device comprising:
a transistor array that includes a first transistor surface and a second transistor surface, wherein transistors of the transistor array are electrically coupled to the metal bitlines via the second transistor surface;
metal bitlines coupled to the second transistor surface;
memory cells coupled to the first transistor surface;
a second transistor array that includes a first transistor surface and a second transistor surface;
second metal bitlines coupled to the second transistor surface; and
second memory cells electrically coupled to the first surface of the second transistor array, wherein the second transistor array is stacked and electrically coupled to the first transistor array.
16. The memory device of claim 15 , wherein the metal bitlines are adjacent to the second transistor surface.
17. The memory device of claim 15 , wherein the metal bitlines are adjacent to a barrier layer.
18. The memory device of claim 15 , wherein a portion of an area between adjacent transistors is metal, wherein the metal is adjacent to a first surface of the metal bitlines and below the second transistor surface.