Nanowire bonding interconnect for fine-pitch microelectronics
A nanowire bonding interconnect for fine-pitch microelectronics is provided. Vertical nanowires created on conductive pads provide a debris-tolerant bonding layer for making direct metal bonds between opposing pads or vias. Nanowires may be grown from a nanoporous medium with a height between 200-1000 nanometers and a height-to-diameter aspect ratio that enables the nanowires to partially collapse against the opposing conductive pads, creating contact pressure for nanowires to direct-bond to opposing pads. Nanowires may have diameters less than 200 nanometers and spacing less than 1 μm from each other to enable contact or direct-bonding between pads and vias with diameters under 5 μm at very fine pitch. The nanowire bonding interconnects may be used with or without tinning, solders, or adhesives. A nanowire forming technique creates a nanoporous layer on conductive pads, creates nanowires within pores of the nanoporous layer, and removes at least part of the nanoporous layer to reveal a layer of nanowires less than 1 μm in height for direct bonding.
1. A method, comprising:
creating a nanoporous layer on a conductive pad of a microelectronic device or wafer;
creating nanowires within pores of the nanoporous layer;
removing or recessing at least part of the nanoporous layer to reveal at least a part of the nanowires for at least conductive contact with an opposing conductive surface of an opposing microelectronic device or wafer; and
direct hybrid bonding a bonding surface of the microelectronic device or wafer to the opposing microelectronic device or wafer, wherein the direct hybrid bonding comprises direct metal bonding the nanowires to the opposing conductive surface and direct bonding the nanoporous layer to the opposing microelectronic device or wafer.
2. The method of claim 1 , further comprising creating nanowires with a diameter less than 200 nanometers, wherein each nanowire has a height between approximately 200 nanometers and approximately 1000 nanometers (1 μm).
3. The method of claim 1 , wherein a height-to-diameter aspect ratio of each nanowire enables the nanowire to partially collapse against the opposing conductive surface providing a compression or a contact pressure of the nanowire for conductively contacting or bonding to the opposing conductive surface.
4. The method of claim 1 , wherein creating the nanoporous layer further comprises depositing a thin layer of a material on the conductive pad; and
forming pores in the thin layer of the material via an etching process or a lithography process to make the nanoporous layer.
5. The method of claim 1 , further comprising flowing a joining material or a solder between the nanowires to conductively secure the nanowires to the opposing conductive surface.
6. The method of claim 5 , further comprising applying pressure to penetrate the nanowires through the solder.
7. The method of claim 1 , further comprising permanently joining the microelectronic device or wafer comprising the nanowires with a second microelectronic device or wafer comprising the opposing conductive surface with an adhesive.
8. The method of claim 1 , further comprising embedding metal pads laterally adjacent to between the conductive pad, the metal pads configured to vertically bond between surfaces being joined.
9. The method of claim 8 , wherein the metal pads comprise a heatsink.
10. The method of claim 1 further comprising exposing a conductive surface of a through substrate via for forming nanowires thereupon.
11. The method of claim 1 , wherein each conductive pad comprises a length or a diameter less than approximately 5 μm.
12. The method of claim 1 , wherein multiple nanowires are conductively connected to each conductive pad.
13. The method of claim 1 , further comprising creating the nanoporous layer on at least the conductive pad and a portion of the bonding surface.
14. The method of claim 13 , further comprising creating nanowires within pores of the nanoporous layer at least at the conductive pad and the portion of the bonding surface.
15. A method, comprising:
forming a dielectric layer on at least a conductive pad and a portion of a bonding surface of a microelectronic device or wafer;
forming nanowires within pores of the dielectric layer over the conductive pad;
removing or recessing at least part of the dielectric layer to reveal at least a part of the nanowires for at least conductive contact with an opposing conductive surface of an opposing microelectronic device or wafer; and
direct hybrid bonding a bonding surface of the microelectronic device or wafer to the opposing microelectronic device or wafer, wherein the direct hybrid bonding comprises direct metal bonding the nanowires to the opposing conductive surface and directly bonding the dielectric layer on the portion of the bonding surface to the opposing microelectronic device or wafer.
16. The method of claim 15 , further comprising forming nanowires within pores of the dielectric layer at least at the conductive pad and the portion of the bonding surface.
17. The method of claim 15 , wherein the dielectric layer comprises a nanoporous layer.
18. The method of claim 15 , wherein forming the dielectric layer further comprises depositing a thin layer of a material on the conductive pad; and
forming pores in the thin layer of the material via an etching process or a lithography process to make the dielectric layer.
19. The method of claim 15 , further comprising flowing a joining material or a solder between the nanowires to conductively secure the nanowires to the opposing conductive surface.
20. The method of claim 15 , wherein multiple nanowires are conductively connected to each conductive pad.