Semiconductor device and manufacturing method thereof
A semiconductor structure includes a semiconductor fin, a doped dielectric fin, a shallow trench isolation (STI) oxide, a gate structure, and source/drain regions. The semiconductor fin upwardly extends from a substrate. The doped dielectric fin upwardly extends above the substrate. The doped dielectric fin is implanted with an impurity therein. The STI oxide laterally surrounds a lower portion of the semiconductor fin and a lower portion of the doped dielectric fin. The gate structure extends across the semiconductor fin and the doped dielectric fin. The source/drain regions are on the semiconductor fin and at opposite sides of the gate structure.
1. A semiconductor structure, comprising:
a semiconductor fin upwardly extending from a substrate;
a doped dielectric fin upwardly extending above the substrate, wherein the doped dielectric fin is doped with a first impurity;
a shallow trench isolation (STI) oxide laterally surrounding a lower portion of the semiconductor fin and a lower portion of the doped dielectric fin;
a gate structure extending across the semiconductor fin and the doped dielectric fin; and
source/drain regions on the semiconductor fin and at opposite sides of the gate structure.
2. The semiconductor structure of claim 1 , wherein the first impurity comprises carbon.
3. The semiconductor structure of claim 2 , wherein a carbon concentration in the doped dielectric fin is in a range from about 5% to about 15%.
4. The semiconductor structure of claim 1 , wherein the first impurity comprises nitrogen.
5. The semiconductor structure of claim 4 , wherein a nitrogen concentration in the doped dielectric fin is in a range from about 10% to about 30%.
6. The semiconductor structure of claim 1 , wherein the STI oxide is doped with a second impurity.
7. The semiconductor structure of claim 6 , wherein the first impurity in the doped dielectric fin is the same as the second impurity in the STI oxide.
8. The semiconductor structure of claim 6 , wherein the first impurity in the doped dielectric fin is different than the second impurity in the STI oxide.
9. The semiconductor structure of claim 6 , wherein the doped dielectric fin has a higher impurity concentration than the STI oxide.
10. The semiconductor structure of claim 1 , wherein the doped dielectric fin is doped with a second impurity therein different than the first impurity.
11. A semiconductor structure, comprising:
first and second nanostructured pedestals on a substrate;
a dielectric layer extending continuously between the first and second nanostructured pedestals and having a U-shaped profile from a cross sectional view taken along a direction perpendicular to a lengthwise direction of the first nanostructured pedestal;
an oxide layer having an underside cupped by the dielectric layer, the oxide layer having an upper portion doped with an impurity;
a metal gate extending across the first and second nanostructured pedestals and the oxide layer;
first epitaxial structures on the first nanostructured pedestal at opposite sides of the metal gate; and
second epitaxial structures on the second nanostructured pedestal at opposite sides of the metal gate.
12. The semiconductor structure of claim 11 , wherein the impurity comprises germanium, carbon, aluminum, or combinations thereof.
13. The semiconductor structure of claim 11 , wherein the impurity is distributed in the oxide layer in a gauss manner.
14. The semiconductor structure of claim 11 , wherein the oxide layer has a lower portion free of the impurity.
15. The semiconductor structure of claim 11 , wherein the oxide layer has a top surface level with a top surface of the dielectric layer.
16. A semiconductor structure, comprising:
first and second fin patterns on a substrate;
first source/drain patterns on the first fin pattern;
second source/drain patterns on the second fin pattern;
an oxide material laterally between the first and second fin patterns from a cross-sectional view taken along a lengthwise direction of the first fin pattern;
a first dielectric layer cupping an underside of the oxide material;
a second dielectric layer over the oxide material, the second dielectric layer comprising edge regions contacting the first dielectric layer from the cross-sectional view;
a first gate pattern extending across the first fin pattern; and
a second gate pattern extending across the second fin pattern.
17. The semiconductor structure of claim 16 , wherein the oxide material is doped with an impurity therein.
18. The semiconductor structure of claim 17 , further comprising:
a shallow trench isolation (STI) oxide laterally surrounding lower portions of the first and second fin patterns and a lower portion of the first dielectric layer, the STI oxide being doped with the impurity.
19. The semiconductor structure of claim 17 , wherein the impurity comprises carbon, nitrogen, or combinations thereof.
20. The semiconductor structure of claim 16 , wherein the first dielectric layer has a U-shaped profile from the cross-sectional view taken along the lengthwise direction of the first fin pattern.