Multi-chip memory system including DRAM chips with integrated comparator arrays and method of operating same
A memory system including a first chip having a processor, and a second chip having a DRAM sector that includes: a plurality of DRAM arrays; an output circuit configured to store a plurality of data values read from the DRAM arrays; a first set of through silicon vias (TSVs) connecting the processor to the DRAM sector, wherein the first processor transmits a plurality of weight data values to the DRAM sector on the first set of TSVs; a plurality of comparator arrays coupled to receive the plurality of weight data values and the plurality of data values read from the DRAM arrays, and in response, generate a plurality of comparison output values; and a second set of TSVs connecting the processor to the DRAM sector, wherein the plurality of comparison output values are transmitted from DRAM sector to the processor on the second set of TSVs.
1 . A memory system comprising:
a first integrated circuit chip comprising a first processor;
a second integrated circuit chip comprising a first dynamic random access memory (DRAM) sector including:
a first plurality of DRAM arrays;
a first output circuit configured to store a first plurality of data values read from the first plurality of DRAM arrays;
a first set of through silicon vias connecting the first processor to the first DRAM sector, wherein the first processor transmits a first plurality of weight data values to the first DRAM sector on the first set of through silicon vias;
a first plurality of comparator arrays coupled to receive the first plurality of weight data values and the first plurality of data values read from the first plurality of DRAM arrays, and in response, generate a first plurality of comparison output values; and
a second set of through silicon vias connecting the first processor to the first DRAM sector, wherein the first plurality of comparison output values are transmitted from the first DRAM sector to the first processor on the second set of through silicon vias.
2 . The memory system of claim 1 , further comprising a third set of through silicon vias connecting the first processor to the first DRAM sector, wherein the first processor transmits addresses for reading the first plurality of data values from the first plurality of DRAM arrays on the third set of through silicon vias.
3 . The memory system of claim 1 , wherein the first integrated circuit chip further comprises a second processor and an interconnect structure that couples the first processor to the second processor, and wherein the second integrated circuit chip further comprises:
a second dynamic random access memory (DRAM) sector including:
a second plurality of DRAM arrays;
a second output circuit configured to store a second plurality of data values read from the second plurality of DRAM arrays;
a third set of through silicon vias connecting the second processor to the second DRAM sector, wherein the second processor transmits a second plurality of weight data values to the second DRAM sector on the third set of through silicon vias;
a second plurality of comparator arrays coupled to receive the second plurality of weight data values and the second plurality of data values read from the second plurality of DRAM arrays, and in response, generate a second plurality of comparison output values; and
a fourth set of through silicon vias connecting the second processor to the second DRAM sector, wherein the second plurality of comparison output values are transmitted from second DRAM sector to the second processor on the fourth set of through silicon vias.
4 . The memory system of claim 3 , wherein the first DRAM sector does not communicate with the second DRAM sector on the second integrated circuit chip.
5 . The memory system of claim 1 , further comprising a third integrated circuit chip comprising:
a second dynamic random access memory (DRAM) sector including:
a second plurality of DRAM arrays;
a second output circuit configured to store a second plurality of data values read from the second plurality of DRAM arrays;
a third set of through silicon vias connecting the first processor to the second DRAM sector, wherein the first processor transmits a second plurality of weight data values to the second DRAM sector on the third set of through silicon vias;
a second plurality of comparator arrays coupled to receive the second plurality of weight data values and the second plurality of data values read from the second plurality of DRAM arrays, and in response, generate a second plurality of comparison output values; and
a fourth set of through silicon vias connecting the first processor to the second DRAM sector, wherein the second plurality of comparison output values are transmitted from second DRAM sector to the first processor on the fourth set of through silicon vias.
6 . The memory system of claim 1 , further comprising a third integrated circuit chip coupled to the first and second integrated circuit chips by a third set of through silicon vias, wherein the third integrated circuit chip provides a plurality of supply voltages to the first and second integrated circuit chips on the third set of through silicon vias.
7 . The memory system of claim 1 , wherein the first plurality of comparator arrays comprises:
a first digital-to-analog converter configured to receive a multi-bit weight data value from the first plurality of weight data values, and in response, provide a first analog output signal;
a second digital-to-analog converter configured to receive a multi-bit data value from the first plurality of data values read from the first plurality of DRAM arrays, and in response, generate a second analog output signal;
a comparator circuit configured to receive the first and second analog output signals, and in response, provide one of the first plurality of comparison output values.
8 . The memory system of claim 7 , wherein the first digital-to-analog converter comprises:
a first capacitor structure directly connected to a first node;
a first plurality of capacitor structures; and
a first plurality of transistors, wherein each of the first plurality of capacitor structures is coupled to the first node by a corresponding one of the first plurality of transistors, and wherein each of the first plurality of transistors has a gate coupled to receive a corresponding bit of the multi-bit weight data value.
9 . The memory system of claim 8 , wherein the first capacitor structure and the first plurality of capacitor structures each comprise a different number of identical capacitors.
10 . The memory system of claim 9 , wherein the first digital-to-analog converter further comprises:
an offset capacitor structure; and
an offset transistor coupling the offset capacitor structure to the first node, wherein the offset transistor has a gate coupled to receive an offset control signal.
11 . The memory system of claim 8 , wherein the second digital-to-analog converter comprises:
a second capacitor structure directly connected to a second node, wherein the second capacitor structure is identical to the first capacitor structure;
a second plurality of capacitor structures, wherein the second plurality of capacitor structures is identical to the first plurality of capacitor structures; and
a second plurality of transistors, wherein each of the second plurality of capacitor structures is coupled to the second node by a corresponding one of the second plurality of transistors, and wherein each of the second plurality of transistors has a gate coupled to receive a corresponding bit of the multi-bit data value.
12 . The memory system of claim 11 , wherein the first digital-to-analog converter includes a first output circuit that generates the first analog output signal in response to a voltage on the first node, and wherein the second digital-to-analog converter includes a second output circuit that generates the second analog output signal in response to a voltage on the second node.
13 . The memory system of claim 12 , wherein the comparator circuit comprises a differential comparator that latches the one of the first plurality of comparison output values in response to the first and second analog output signals.
14 . The memory system of claim 7 , wherein the comparator circuit only activates the one of the first plurality of comparison output values to a logic high voltage state when the multi-bit data value is greater than the multi-bit weight data value.
15 . The memory system of claim 1 , wherein the first plurality of comparator arrays comprises: a plurality of latches for storing the plurality of weight data values, wherein the plurality of weight data values are sequentially loaded into the plurality of latches.
16 . The memory system of claim 1 , wherein the plurality of comparator arrays comprises:
a plurality of columns of q-data digital-to-analog converters, wherein each of the q-data digital-to-analog converters is coupled to receive a corresponding plurality of bits of the first plurality of data values;
a plurality of columns of weight data digital-to-analog converters, wherein each of the weight data digital-to-analog converters is coupled to receive a corresponding plurality of bits of the plurality of weight data values; and
a plurality of columns of comparator circuits, wherein each of the columns of comparator circuits is located between one of the columns of q-data digital-to-analog converters, and one of the columns of weight data digital-to-analog converters.
17 . A method comprising
transmitting a first comparison instruction and a corresponding first plurality of weight data values from a first processor on a first integrated circuit chip to a first dynamic random access memory (DRAM) sector on a second integrated circuit chip, wherein the first DRAM sector comprises a first plurality of DRAM arrays;
reading a first plurality of data values from the first plurality of DRAM arrays in response to the first comparison instruction;
generating a first plurality of comparison output values in response to the first plurality of data values and the first plurality of weight data values; and
transmitting the first plurality of comparison output values from the first DRAM sector to the first processor.
18 . The method of claim 17 , further comprising:
transmitting the first comparison instruction and the first plurality of weight data values on a first set of through silicon vias connecting the first processor to the first DRAM sector; and
transmitting the first plurality of comparison output values on a second set of through silicon vias connecting the first processor to the first DRAM sector.
19 . The method of claim 17 , further comprising:
generating a first analog output signal in response to a multi-bit weight data value included in the first plurality of weight data values;
generating a second analog output signal in response to a multi-bit data value included in the first plurality of data values read from the first plurality of DRAM arrays; and
generating one of the first plurality of comparison output values in response to the first and second analog output signals.
20 . The method of claim 17 , further comprising:
transmitting a second comparison instruction and a corresponding second plurality of weight data values from a second processor on a first integrated circuit chip to a second dynamic random access memory (DRAM) sector on the second integrated circuit chip, wherein the second DRAM sector comprises a second plurality of DRAM arrays;
reading a second plurality of data values from the second plurality of DRAM arrays in response to the second comparison instruction;
generating a second plurality of comparison output values in response to the second plurality of data values and the second plurality of weight data values; and
transmitting the second plurality of comparison output values from the second DRAM sector to the second processor.