Granted Patent B2

US 12,230,696 · App. 18/606,052 · Granted Feb 18, 2025

Inventors: Shunpei Yamazaki (Tokyo, JP); Hideomi Suzawa (Kanagawa, JP); Shinya Sasagawa (Kanagawa, JP); Motomu Kurata (Kanagawa, JP); Masashi Tsubuku (Kanagawa, JP)

Assignee: Semiconductor Energy Laboratory Co., Ltd.

H01L29/66969H01L21/02565H01L27/1225H01L27/127H01L27/14616H01L27/14689H01L29/7869H01L29/78696

Abstract

Claims (49)

1. A semiconductor device comprising:

a plurality of circuits:

the plurality of circuits each comprising:

a first transistor comprising a channel formation region comprising an oxide semiconductor;

a second transistor comprising a channel formation region comprising silicon; and

a capacitor,

wherein a source or a drain of the first transistor is electrically connected to a gate of the second transistor, and

wherein the gate of the second transistor is electrically connected to the capacitor,

a first conductive layer;

an oxide semiconductor layer comprising a region over the first conductive layer;

a first insulating layer comprising a region over the oxide semiconductor layer;

a second conductive layer comprising a region over the first insulating layer; and

a second insulating layer comprising a region over the second conductive layer,

wherein the first conductive layer comprises a region functioning as one of a source electrode and a drain electrode of the first transistor,

wherein the oxide semiconductor layer comprises a region configured to function as the channel formation region of the first transistor,

wherein the first insulating layer comprises a region configured to function as a gate insulating layer of the first transistor,

wherein the second conductive layer comprises a region configured to function as a gate electrode of the first transistor,

wherein the oxide semiconductor layer is in contact with part of a top surface and a side surface of the first conductive layer,

wherein in a cross-sectional view of the first transistor along a channel length direction, the first insulating layer comprises an extended region extending beyond an end portion of the second conductive layer,

wherein the second insulating layer is an oxide insulating layer,

wherein the second insulating layer comprises a region in contact with the top surface of the extended region of the first insulating layer, a region in contact with a side surface of the first insulating layer, a region in contact with a side surface of the oxide semiconductor layer, and a region in contact with the top surface of the first conductive layer, and

wherein a width of the first conductive layer in a channel width direction of the first transistor is larger than a channel width of the first transistor in the channel formation region.

2. A semiconductor device comprising:

a plurality of circuits:

the plurality of circuits each comprising:

a first transistor comprising a channel formation region comprising an oxide semiconductor;

a second transistor comprising a channel formation region comprising silicon; and

a capacitor,

wherein a source or a drain of the first transistor is electrically connected to a gate of the second transistor, and

wherein the gate of the second transistor is electrically connected to the capacitor,

a first conductive layer;

an oxide semiconductor layer comprising a region over the first conductive layer;

a first insulating layer comprising a region over the oxide semiconductor layer;

a second conductive layer comprising a region over the first insulating layer; and

a second insulating layer comprising a region over the second conductive layer,

wherein the first conductive layer comprises a region functioning as one of a source electrode and a drain electrode of the first transistor,

wherein the oxide semiconductor layer comprises a region configured to function as the channel formation region of the first transistor,

wherein the first insulating layer comprises a region configured to function as a gate insulating layer of the first transistor,

wherein the second conductive layer comprises a region configured to function as a gate electrode of the first transistor,

wherein the oxide semiconductor layer is in contact with part of a top surface and a side surface of the first conductive layer,

wherein in a cross-sectional view of the first transistor along a channel length direction, the first insulating layer comprises an extended region extending beyond an end portion of the second conductive layer,

wherein the second insulating layer is an oxide insulating layer,

wherein the second insulating layer comprises a region in contact with the top surface of the extended region of the first insulating layer, a region in contact with a side surface of the first insulating layer, a region in contact with a side surface of the oxide semiconductor layer, and a region in contact with the top surface of the first conductive layer,

wherein a width of the first conductive layer in a channel width direction of the first transistor is larger than a channel width of the first transistor in the channel formation region,

wherein the oxide semiconductor layer comprises a first layer and a second layer over the first layer,

wherein the first layer and the second layer each comprises indium, gallium, and zinc, and

wherein an atomic ratio of indium, gallium and zinc in the first layer is different from that of the second layer.

3. The semiconductor device according to claim 1 or claim 2 , wherein in the cross-sectional view of the first transistor along the channel length direction, a length of the extended region of the first insulating layer is smaller than 3 μm.

4. The semiconductor device according to claim 1 or claim 2 , wherein in the cross-sectional view of the first transistor along the channel length direction, a side surface of the first conductive layer overlapping with the oxide semiconductor layer comprises a stepped shape.

Assignments (1)

Priority Claims (1)

Continuity (7)

References Cited (354)