Integrated circuit device and method of forming the same
An integrated circuit device includes a first device and a second device. The first device is disposed within a first circuit region, the first device including a plurality of first semiconductor strips extending longitudinally in a first direction. Adjacent ones of the plurality of first semiconductor strips are spaced apart from each other in a second direction, which is generally perpendicular to the first direction. The second device is disposed within a second circuit region, the second circuit region being adjacent to the first circuit region in the first direction. The second device includes a second semiconductor strip extending longitudinally in the first direction. A projection of a longitudinal axis of the second semiconductor strip along the first direction lies in a space separating the adjacent ones of the plurality of first semiconductor strips.
1 . A method to form an integrated circuit (IC) structure with mandrel and spacer patterning, comprising:
forming a mandrel layer that includes three line segments, a first mandrel line segment disposed in a first circuit region and oriented in a first direction, a second mandrel line segment disposed in a second circuit region and oriented in the first direction, the second mandrel line segment being shifted from the first mandrel line segment along a second direction being orthogonal to the first direction, and a third mandrel line segment disposed in a gap region connecting the first mandrel line segment and the second mandrel line segment, wherein the third mandrel line segment is oriented in a third direction different from the first direction and the second direction;
forming spacers on sidewalls of the mandrel layer;
removing the mandrel layer; and
removing portions of the spacers, resulting in patterned spacers that include a first subset in the first circuit region and oriented in the first direction and a second subset in the second circuit region and oriented in the first direction.
2 . The method of claim 1 , further comprising:
etching a substrate using the patterned spacers as an etch mask to form a plurality of fin lines in the first circuit region of the substrate and a single fin line in the second circuit region of the substrate, wherein a projection of a longitudinal axis of the single fin line along the first direction lies in a space separating adjacent ones of the plurality of fin lines, and wherein a projection of each longitudinal edge of the single fin line along the first direction lies in the space.
3 . The method of claim 2 , further comprising forming an isolation structure in the substrate, the isolation structure being disposed between the first circuit region and the second circuit region to electrically isolate the first circuit region from the second circuit region.
4 . The method of claim 2 , wherein
each of the plurality of fin lines in the first circuit region includes a longitudinal axis along the first direction; and
the single fin line in the second circuit region is connected to one of the plurality of fin lines through selective portions of the plurality of fin lines and the single fin line.
5 . The method of claim 2 , further comprising forming a first gate stack on the plurality of fin lines and a second gate stack on the single fin line, wherein a first gate stack and a second gate stack are longitudinally extended along the second direction, and wherein each of the first gate stack and the second gate stack includes a gate dielectric layer and a gate electrode on the gate dielectric layer.
6 . The method of claim 1 , further comprising
forming a first dielectric gate stack on a boundary of the first circuit region; and
forming a second dielectric gate stack on a boundary of the second circuit region.
7 . An integrated circuit device, comprising:
a semiconductor substrate;
a first device disposed within a first circuit region, the first device including a plurality of first semiconductor strips vertically extending from the semiconductor substrate and extending longitudinally in a first direction, and a first gate stack disposed on the plurality of first semiconductor strips, wherein adjacent ones of the plurality of first semiconductor strips are spaced apart from each other in a second direction, the second direction being generally perpendicular to the first direction; and
a second device disposed within a second circuit region, the second circuit region being adjacent to the first circuit region in the first direction, the second device including a single semiconductor strip vertically extending from the semiconductor substrate and extending longitudinally in the first direction, and a second gate stack disposed on the single semiconductor strip, wherein a projection of each longitudinal edge of the single semiconductor strip along the first direction lies in a space separating the adjacent ones of the plurality of first semiconductor strips, each of the first gate stack and the second gate stack extending longitudinally in the second direction.
8 . The integrated circuit device of claim 7 , wherein each of the single semiconductor strip and the plurality of first semiconductor strips includes a semiconductor fin structure.
9 . The integrated circuit device of claim 7 , wherein each of the single semiconductor strip and the plurality of first semiconductor strips includes a nanowire or a nanosheet.
10 . The integrated circuit device of claim 7 , further comprising a contact disposed on a surface of a source/drain feature of the single semiconductor strip, the surface of the source/drain feature being directed towards a third direction generally perpendicular to the first direction and the second direction, wherein the surface of the source/drain feature contacts a center region of the contact.
11 . The integrated circuit device of claim 7 , wherein the projection of the longitudinal edge of the single semiconductor strip along the first direction equally splits the space separating the adjacent ones of the plurality of first semiconductor strips.
12 . The integrated circuit device of claim 7 , wherein a width of each of the single semiconductor strip and the plurality of first semiconductor strips, measured in the second direction, is between about 5 nanometers and about 20 nanometers.
13 . The integrated circuit device of claim 7 , further comprising an isolation structure disposed between the first circuit region and the second circuit region to electrically isolate the first circuit region from the second circuit region.
14 . The integrated circuit device of claim 13 , wherein the isolation structure includes a dielectric gate structure.
15 . An integrated circuit device, comprising:
a first standard cell having a first device, the first device including a plurality of first semiconductor strips extending longitudinally in a first direction, wherein adjacent ones of the plurality of first semiconductor strips are spaced apart from each other in a second direction, the second direction being generally perpendicular to the first direction; and
a second standard cell having a second device disposed within a second circuit region, the second standard cell being adjacent to the first standard cell in the first direction, the second device including a plurality of second semiconductor strips extending longitudinally in the first direction, wherein a projection of a longitudinal axis of each one of the plurality of second semiconductor strips along the first direction lies in a space separating the adjacent ones of the plurality of first semiconductor strips, and wherein a projection of a longitudinal axis of each one of the plurality of first semiconductor strips along the first direction lies in a space separating adjacent ones of the plurality of second semiconductor strips.
16 . The integrated circuit device of claim 15 , wherein each of the plurality of first semiconductor strips and the plurality of second semiconductor strips includes a semiconductor fin structure.
17 . The integrated circuit device of claim 15 , wherein each of the plurality of first semiconductor strips and the second semiconductor strips includes a nanowire or a nanosheet.
18 . The integrated circuit device of claim 15 , further comprising a contact disposed on a surface of a source/drain feature, the surface of the source/drain feature being directed towards a third direction generally perpendicular to the first direction and the second direction, wherein the surface of the source/drain feature contacts a center region of the contact.
19 . The integrated circuit device of claim 15 , wherein the projection of the longitudinal axis of one of the plurality of second semiconductor strips along the first direction equally splits the space separating the adjacent ones of the plurality of first semiconductor strips.
20 . The integrated circuit device of claim 15 , further comprising a dielectric gate disposed between the first standard cell and the second standard cell to electrically isolate the first standard cell from the second standard cell.