IP Library › Granted Patent US 12,667,030
Granted Patent B2
US 12,667,030 · App. 17/744,397 · Granted Jun 23, 2026

Electronic chips including J-shaped substrate sidewalls

Inventors: Olivier Ory (Tours, FR); Michael De Cruz (Monnaie, FR)
Assignee: STMICROELECTRONICS (TOURS) SAS
H10W90/701H10W70/65H10W70/69H10W72/01251H10W72/01261H10W72/07253H10W72/232H10W72/234
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,667,030
App. No.
17/744,397
Granted
Jun 23, 2026
Kind
B2
Abstract

An electronic chip including a semiconductor substrate carrying at least one metal contact extending, within the thickness of the substrate, along at least one flank of the chip.

Claims (51)

1 . A device, comprising:

a substrate including a first surface, a second surface opposite to the first surface, and a sidewall transverse to the first surface and the second surface;

an interconnect layer on the first surface of the substrate, the interconnect layer including a conductive pad;

an insulating layer is on and covers a first portion of the sidewall of the substrate;

a conductive layer is coupled to the conductive pad at the first surface of the substrate, the conductive layer is on the insulating layer and covers the insulating layer, and the conductive layer is separated from the sidewall of substrate by the insulating layer;

a first resin layer extends from the second surface of the substrate to the insulating layer and is on and covers a second portion of the sidewall of the substrate; and

a second resin layer is on the second surface of the substrate, and

wherein the first resin layer is on the second resin layer.

2 . The device of claim 1 , wherein the first portion of the sidewall is smaller than the second portion of the sidewall.

3 . The device of claim 1 , wherein:

the insulating layer includes a first end sidewall substantially coplanar with the second portion of the sidewall of the substrate; and

the conductive layer includes a second end sidewall substantially coplanar with the second portion of the sidewall of the substrate and the first end sidewall of the insulating layer.

4 . The device of claim 3 , wherein the first resin layer covers the first end sidewall of the insulating layer and the second end sidewall of the conductive layer.

5 . The device of claim 1 , wherein the first portion of the sidewall is offset from the second portion of the sidewall.

6 . The device of claim 1 , wherein sidewall surfaces of the insulating layer, the conductive layer, the first resin layer, and the second resin layer are substantially coplanar with each other and are spaced apart from the sidewall of the substrate.

7 . The device of claim 1 , wherein the first resin layer includes a negative photosensitive resin material.

8 . The device of claim 1 , wherein the first resin layer includes an end surface substantially coplanar and flush with the first surface of the substrate.

9 . The device of claim 8 , wherein the insulating layer has an L-shape.

10 . A device, comprising:

a substrate including a first surface, a second surface opposite to the first surface, and a sidewall transverse to the first surface and the second surface;

an interconnect layer on the first surface of the substrate, the interconnect layer including a conductive pad;

an insulating layer is on and covers a first portion of the sidewall of the substrate and is on and covers a curved portion of the sidewall;

a conductive layer is coupled to the conductive pad at the first surface of the substrate, the conductive layer is on the insulating layer and covers the insulating layer, and the conductive layer is separated from the sidewall of substrate by the insulating layer;

a first resin layer extends from the second surface of the substrate to the insulating layer and is on and covers a second portion of the sidewall of the substrate; and

a second resin layer is on the second surface of the substrate, and

wherein the curved portion of the sidewall extends from the first portion of the sidewall to the second portion of the sidewall, and wherein the first resin layer is on the second resin layer.

11 . The device of claim 10 , wherein:

the insulating layer includes a first end sidewall;

the conductive layer includes a second end sidewall; and

the first end sidewall and the second end sidewall are coplanar with second portion of the sidewall of the substrate.

12 . The device of claim 11 , wherein the first resin layer is on and covers the first end sidewall of the insulating layer.

13 . The device of claim 12 , wherein the first resin layer is on and covers the second end sidewall of the conductive layer.

14 . The device of claim 10 , wherein the first resin layer includes a first sidewall spaced apart from the substrate, the insulating layer, and the conductive layer, and the second resin layer includes a second sidewall coplanar with the first sidewall.

15 . A device, comprising:

a substrate including a first surface, a second surface opposite to the first surface, a J-shaped sidewall that extends from the first surface, and a sidewall that extends from the second surface to the J-shaped sidewall;

an interconnect layer on the first surface of the substrate, the interconnect layer including a conductive pad;

an insulating layer is on and covers the J-shaped sidewall of the substrate;

a conductive layer is coupled to the conductive pad at the first surface of the substrate, the conductive layer is on the insulating layer and covers the insulating layer, and the conductive layer is separated from the J-shaped sidewall of substrate by the insulating layer;

a first resin layer extends from the second surface of the substrate to the conductive layer and is on and covers the sidewall of the substrate; and

a second resin layer is on the second surface of the substrate, and

wherein the first resin layer is on the second resin layer.

16 . The device of claim 15 , wherein:

the insulating layer is a J-shaped insulating layer; and

the conductive layer is a J-shaped conductive layer.

17 . The device of claim 16 , wherein:

the insulating layer includes a first end sidewall coplanar with the sidewall of the substrate;

the conductive layer includes a second end sidewall coplanar with the sidewall of the substrate and the first end sidewall.

18 . The device of claim 17 , wherein:

the first resin layer includes a first external sidewall spaced apart from the first end sidewall of the insulating layer, the second end sidewall of the conductive layer, and the sidewall of the substrate; and

the second resin layer includes a second external sidewall that is coplanar with the first external sidewall.

19 . The device of claim 15 , wherein the first resin layer is on the interconnect layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 2, 2022
From: ORY, OLIVIER; DE CRUZ, MICHAEL
To: STMICROELECTRONICS (TOURS) SAS
Reel/Frame 060088/0704 →
Priority Claims (1)
FR 2105176 · May 18, 2021 · national
Continuity (1)
Related Publication 20220375840A1 · Nov 24, 2022
References Cited (90)
US 4640721A · Uehara et al. · 1987 [cited by applicant]
US 5428248A · Cha · 1995 [cited by applicant]
US 5606198A · Ono et al. · 1997 [cited by applicant]
US 5770888A · Song et al. · 1998 [cited by applicant]
US 5910687A · Chen · 1999 [cited by examiner]
US 5998877A · Ohuchi · 1999 [cited by applicant]
US 6326689B1 · Thomas · 2001 [cited by applicant]
US 6498099B1 · McLellan et al. · 2002 [cited by applicant]
US 7935568B2 · Oganesian et al. · 2011 [cited by applicant]
US 8278213B2 · Kameyama et al. · 2012 [cited by applicant]
US 8551815B2 · Avsian et al. · 2013 [cited by applicant]
US 9177836B1 · Liu et al. · 2015 [cited by applicant]
US 11393785B2 · Fallourd et al. · 2022 [cited by applicant]
US 20030067001A1 · Poo et al. · 2003 [cited by applicant]
US 20050095750A1 · Lo et al. · 2005 [cited by applicant]
US 20060012967A1 · Asai et al. · 2006 [cited by applicant]
US 20060170112A1 · Tanaka et al. · 2006 [cited by applicant]
US 20070026567A1 · Beer et al. · 2007 [cited by applicant]
US 20070096295A1 · Burtzlaff et al. · 2007 [cited by applicant]
US 20080315407A1 · Andrews, Jr. · 2008 [cited by examiner]
US 20090243097A1 · Koroku et al. · 2009 [cited by applicant]
US 20100001305A1 · Lin · 2010 [cited by examiner]
US 20100246152A1 · Lin et al. · 2010 [cited by applicant]
US 20110018116A1 · Feng · 2011 [cited by applicant]
US 20110042799A1 · Kang et al. · 2011 [cited by applicant]
US 20110133333A1 · Kwon · 2011 [cited by examiner]
US 20110189822A1 · Sasaki et al. · 2011 [cited by applicant]
US 20110207323A1 · Ditizio · 2011 [cited by examiner]
US 20110274299A1 · Shaw et al. · 2011 [cited by applicant]
US 20110304008A1 · Yang · 2011 [cited by applicant]
US 20120034760A1 · Schuderer et al. · 2012 [cited by applicant]
US 20120178251A1 · Lim et al. · 2012 [cited by applicant]
US 20120282735A1 · Ahn et al. · 2012 [cited by applicant]
US 20130161813A1 · Miki · 2013 [cited by applicant]
US 20130267124A1 · Chang et al. · 2013 [cited by applicant]
US 20140054796A1 · Gong et al. · 2014 [cited by applicant]
US 20150007939A1 · Sherrer et al. · 2015 [cited by applicant]
US 20150228557A1 · Cheng et al. · 2015 [cited by applicant]
US 20150255349A1 · Holden et al. · 2015 [cited by applicant]
US 20150269472A1 · Finn et al. · 2015 [cited by applicant]
US 20160172275A1 · Marchisi · 2016 [cited by applicant]
US 20170025356A1 · Xue · 2017 [cited by applicant]
US 20170077022A1 · Scanlan et al. · 2017 [cited by applicant]
US 20170084686A1 · Wang et al. · 2017 [cited by applicant]
US 20170222019A1 · Wang et al. · 2017 [cited by applicant]
US 20170271246A1 · Macheiner et al. · 2017 [cited by applicant]
US 20170316957A1 · Chen et al. · 2017 [cited by applicant]
US 20170323840A1 · Chiu et al. · 2017 [cited by applicant]
US 20170373042A1 · Shizukuishi · 2017 [cited by examiner]
US 20180005912A1 · Oh et al. · 2018 [cited by applicant]
US 20180008920A1 · Peterson, II et al. · 2018 [cited by applicant]
US 20180033781A1 · Zhou et al. · 2018 [cited by applicant]
US 20180068920A1 · Leung et al. · 2018 [cited by applicant]
US 20180204780A1 · Chiu et al. · 2018 [cited by applicant]
US 20180269138A1 · Villamor et al. · 2018 [cited by applicant]
US 20180330966A1 · Scanlan et al. · 2018 [cited by applicant]
US 20180342453A1 · Ziglioli · 2018 [cited by applicant]
US 20190244853A1 · Berger et al. · 2019 [cited by applicant]
US 20190265118A1 · Tu · 2019 [cited by examiner]
US 20200126877A1 · Takaoka · 2020 [cited by applicant]
US 20210175094A1 · De Cruz et al. · 2021 [cited by applicant]
US 20210175203A1 · Fallourd et al. · 2021 [cited by applicant]
US 20220302013A1 · Pyun et al. · 2022 [cited by applicant]
US 20220344303A1 · Fallourd et al. · 2022 [cited by applicant]
US 20230068222A1 · Ory et al. · 2023 [cited by applicant]
US 20230178380A1 · De Cruz et al. · 2023 [cited by applicant]
US 20250192022A1 · Delacourt · 2025 [cited by applicant]
CN 1812075A · 2006 [cited by applicant]
CN 1835196A · 2006 [cited by applicant]
CN 103364455A · 2013 [cited by applicant]
CN 104022043A · 2014 [cited by applicant]
CN 105374762A · 2016 [cited by applicant]
CN 107134438A · 2017 [cited by applicant]
CN 107808871A · 2018 [cited by applicant]
CN 108807197A · 2018 [cited by applicant]
CN 110943041A · 2020 [cited by applicant]
CN 112908935A · 2021 [cited by applicant]
CN 219226269U · 2023 [cited by applicant]
EP 1085570A2 · 2001 [cited by applicant]
EP 3154085A1 · 2017 [cited by applicant]
EP 3211670A1 · 2017 [cited by applicant]
EP 3282476A1 · 2018 [cited by applicant]
JP 2009076839A · 2009 [cited by applicant]
KR 20030008646A · 2003 [cited by applicant]
KR 100595885B1 · 2006 [cited by applicant]
WO WO2020250660A1 · 2020 [cited by applicant]
Ganjei, John, “Improved QFN Reliability by Flank Tin Plating Process after Singulation,” 10th International Microsystems, Packaging, Assembly and Circuits Technology Conference, 2015, 4 pages. [cited by applicant]
2021/0175094, filed Jun. 10, 2021. [cited by applicant]
U.S. Appl. No. 17/811,560, filed Jul. 8, 2022. [cited by applicant]
U.S. Appl. No. 17/744,397, filed Aug. 26, 2022. [cited by applicant]