IP Library › Assignment 030962/0142
Patent Assignment
Reel/Frame 030962/0142

Corrective Assignment to Correct the State of Incorporation Within the Assignment Document Previously Recorded on Reel 011177, Frame 0921.Assignors Hereby Confirms the State of Incorporation Is Texas.

Recorded: 2013-06-27 Pages: 25
Assignor
STAKTEK CORPORATION
Executed: 2000-09-27
Assignee
STAKTEK GROUP L.P.
8900 SHOAL CREEK, AUSTIN, TEXAS, 78758
Covered Properties (57)
Lead-On-Chip Integrated Circuit Fabrication Method
Patent: 5,221,642 →
Application: 07/746,268 →
Lead-On-Chip Integrated Circuit Apparatus
Patent: 5,448,450 →
Application: 07/783,737 →
Electromagnetic Shutter
Patent: 5,337,077 →
Application: 07/855,063 →
Simulcast Standard Multichip Memory Addressing System
Patent: 5,371,866 →
Application: 07/891,609 →
Impact Solder Method and Apparatus
Patent: 5,236,117 →
Application: 07/903,056 →
High Density Lead-on-Package Fabrication Method and Apparatus
Patent: 5,484,959 →
Application: 07/990,334 →
Warp-Resistent Ultra-Thin Integrated Circuit Package Fabrication Method
Patent: 5,369,056 →
Application: 08/037,830 →
Ultra High Density Integrated Circuit Packages Method
Patent: 5,367,766 →
Application: 08/043,196 →
Ultra High Density Integrated Circuit Packages Method
Patent: 5,279,029 →
Application: 08/059,401 →
Ultra High Density Integrated Circuit Packages Method and Apparatus
Patent: 5,446,620 →
Application: 08/133,395 →
Ultra High Density Modular Integrated Circuit Package
Patent: 5,420,751 →
Application: 08/133,397 →
Capacitive Coupling Configuration for an Integrated Circuit Package
Patent: 5,498,906 →
Application: 08/153,511 →
Warp-Resistent Ultra-Thin Integrated Circuit Package Fabrication Method
Patent: 5,369,058 →
Application: 08/206,301 →
Method of Assembling Ultra High Density Integrated Circuit Packages
Patent: 5,475,920 →
Application: 08/206,311 →
Bus Communication System for Stacked High Density Integrated Circuit Packages
Patent: 5,455,740 →
Application: 08/206,829 →
Warp-Resistant Ultra-Thin Integrated Circuit Package
Patent: 5,581,121 →
Application: 08/280,968 →
Multi-Signal Rail Assembly with Impedance Control for a Three-Dimensional High Density Integrated Circuit Package
Patent: 5,561,591 →
Application: 08/289,468 →
Ultra High Density Integrated Circuit Packages Method and Apparatus
Patent: 5,566,051 →
Application: 08/298,544 →
Hermetically Sealed Ceramic Integrated Circuit Heat Dissipating Package Fabrication Method
Patent: 5,702,985 →
Application: 08/325,719 →
Hermetically Sealed Ceramic Integrated Circuit Heat Dissipating Package
Patent: 5,572,065 →
Application: 08/328,338 →
Ultra High Density Integrated Circuit Package
Patent: 5,543,664 →
Application: 08/375,747 →
Lead-On-Chip Integrated Circuit Apparatus
Patent: 5,528,075 →
Application: 08/375,874 →
High Density Integrated Circuit Module with Complex Electrical Interconnect Rails
Patent: 5,592,364 →
Application: 08/377,578 →
Hermetically Sealed Integrated Circuit Lead-on Package Configuration
Patent: 5,804,870 →
Application: 08/380,541 →
High Density Integrated Circuit Module with Snap-on Rail Assemblies
Patent: 5,499,160 →
Application: 08/380,543 →
Ultra High Density Integrated Circuit Packages
Patent: 5,550,711 →
Application: 08/436,902 →
Bus Communication System for Stacked High Density Integrated Circuit Packages with Trifurcated Distal Lead Ends
Patent: 5,479,318 →
Application: 08/440,500 →
Bus Communication System for Stacked High Density Integrated Circuit Packages with Bifurcated Distal Lead Ends
Patent: 5,493,476 →
Application: 08/445,848 →
Method of Manufacturing a Bus Communication System for Stacked High Density Integrated Circuit Packages
Patent: 5,605,592 →
Application: 08/445,895 →
Ultra-High Density Warp-Resistant Memory Module
Patent: 5,644,161 →
Application: 08/473,593 →
High Density Lead-on-Package Fabrication Method and Apparatus
Patent: 5,631,193 →
Application: 08/497,565 →
Bus Communication System for Stacked High Density Integrated Circuit Packages
Patent: 5,552,963 →
Application: 08/506,309 →
Simulcast Standard Multichip Memory Addressing System
Patent: 36,229 →
Application: 08/510,729 →
Three-Dimensional Warp-Resistant Integrated Circuit Module Method and Apparatus
Patent: 5,801,437 →
Application: 08/514,294 →
Lead-On-Chip Integrated Circuit Apparatus
Patent: 5,654,877 →
Application: 08/516,848 →
Method of Manufacturing an Integrated Package Having a Pair of Die on a Common Lead Frame
Patent: 5,615,475 →
Application: 08/517,485 →
Method of Manufacturing a High Density Integrated Circuit Module Having Complex Electrical Interconnect Rails
Patent: 5,588,205 →
Application: 08/523,201 →
Bus Communication System for Stacked High Density Integrated Circuit Packages Having an Intermediate Lead Frame
Patent: 5,541,812 →
Application: 08/526,470 →
Integrated Circuit Package with Overlapped Die on a Common Lead Frame
Patent: 5,585,668 →
Application: 08/601,880 →
Bus Communication System for Stacked High Density Integrated Circuit Packages
Patent: 5,586,009 →
Application: 08/630,083 →
Warp-Resistent Ultra-Thin Integrated Circuit Package Fabrication Method
Patent: 5,864,175 →
Application: 08/644,491 →
Integrated Circuit Packages Having an Externally Mounted Lead Frame Having Bifurcated Distal Lead Ends
Patent: 5,978,227 →
Application: 08/645,319 →
Method of Manufacturing a High Density Integrated Circuit Module with Complex Electrical Interconnect Rails Having Electrical Interconnect Strain Relief
Patent: 5,778,522 →
Application: 08/650,721 →
Method of Manufacturing an Uktra-High Density Warp-Resistant Memory Module
Patent: 5,843,807 →
Application: 08/686,985 →
Ultra-High Density Warp-Resistant Memory Module
Patent: 5,828,125 →
Application: 08/758,839 →
Method of Forming a Hermetically Sealed Circuit Lead-on Package
Patent: 5,783,464 →
Application: 08/798,556 →
Apparatus and Method of Manufacturing a Warp Resistant Thermally Conductive Integrated Circuit Package
Patent: 5,945,732 →
Application: 08/815,537 →
Three-Dimensional Warp-Resistant Integrated Circuit Module Method and Apparatus
Patent: 5,895,232 →
Application: 08/888,850 →
Ultra High Density Integrated Circuit Packages
Patent: 6,049,123 →
Application: 08/935,380 →
Ultra High Density Integrated Circuit Packages
Patent: 6,025,642 →
Application: 08/937,200 →
Method of Making High Density Circuit Module
Patent: 5,960,539 →
Application: 09/021,744 →
Method of Manufacturing a Warp Resistant Thermally Conductive Circuit Package
Patent: 6,190,939 →
Application: 09/115,293 →
Clock Driver with Instantaneously Selectable Phase and Method for Use in Data Communication System
Patent: 6,282,210 →
Application: 09/133,297 →
Stacked Micro Ball Grid Array Packages
Patent: 6,310,392 →
Application: 09/221,350 →
Method of Manufacturing a Surface Mount Package
Patent: 6,205,654 →
Application: 09/222,263 →
High Density Integrated Circuit Module with Complex Electrical Interconnect Rails Having Electrical Interconnect Strain Relief
Patent: 6,288,907 →
Application: 09/343,432 →
Rambus Stakpak
Patent: 6,404,662 →
Application: 09/646,724 →
Related Assignments (8)
Other recorded transfers of the patents in this record — the chain of ownership.
Change of Name Jan 26, 2010
From: STAKTEK GROUP, L.P.
To: ENTORIAN TECHNOLOGIES L.P.
Reel/Frame 023848/0062 →
Release of Security Interest Feb 26, 2010
From: COMERICA BANK, AS AGENT
To: STAKTEK GROUP L.P. NOW KNOWN AS ENTORIAN TECHNOLOGIES L.P.
Reel/Frame 023985/0954 →
Merger Sep 28, 2012
From: ENTORIAN GP LLC
To: ENTORIAN TECHNOLOGIES INC.
Reel/Frame 029048/0636 →
Merger Sep 28, 2012
From: ENTORIAN TECHNOLOGIES L.P.
To: ENTORIAN GP LLC
Reel/Frame 029048/0376 →
Merger Oct 25, 2012
From: ENTORIAN GP LLC
To: ENTORIAN TECHNOLOGIES INC.
Reel/Frame 029195/0114 →
Merger Oct 25, 2012
From: ENTORIAN TECHNOLOGIES L.P.
To: ENTORIAN GP LLC
Reel/Frame 029195/0048 →
Assignment of Assignor's Interest Dec 2, 2012
From: ENTORIAN TECHNOLOGIES INC.
To: OVID DATA CO. LLC
Reel/Frame 029389/0672 →
Merger Dec 27, 2015
From: OVID DATA CO. LLC
To: TAMIRAS PER PTE. LTD., LLC
Reel/Frame 037373/0481 →