IP Library Granted Patent US 12,198,981
Granted Patent B2
US 12,198,981 · App. 18/297,829 · Granted Jan 14, 2025

Diffusion barrier collar for interconnects

Inventors: Rajesh Katkar (Milpitas, CA); Cyprian Emeka Uzoh (San Jose, CA)
Assignee: Adeia Semiconductor Bonding Technologies Inc.
H01L21/76843H01L21/68H01L23/53238H01L24/09H01L25/0657H01L25/50H01L2224/08237H01L2225/06513H01L2924/37001
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Quick Facts
Patent No.
US 12,198,981
App. No.
18/297,829
Granted
Jan 14, 2025
Kind
B2
Abstract

Representative implementations of techniques and devices are used to reduce or prevent conductive material diffusion into insulating or dielectric material of bonded substrates. Misaligned conductive structures can come into direct contact with a dielectric portion of the substrates due to overlap, especially while employing direct bonding techniques. A barrier interface that can inhibit the diffusion is disposed generally between the conductive material and the dielectric at the overlap.

Claims (57)

1. A substrate having a bonding surface, the substrate comprising:

a first insulating layer having an upper surface and a first cavity extending vertically at least partially through a thickness of the first insulating layer;

a first conductive interconnect pad at least partially disposed in the first cavity; and

an embedded barrier interface material disposed on the first insulating layer without extending below the upper surface of the first insulating layer,

a second insulating layer over the embedded barrier interface material, the second insulating layer having a dielectric surface spaced above the embedded barrier interface material, the bonding surface including the dielectric surface of the second insulating layer and an upper surface of the first conductive interconnect pad, wherein the bonding surface is prepared for direct bonding, and

wherein the embedded barrier interface material inhibits diffusion of conductive material into the first insulating layer from the bonding surface.

2. The substrate of claim 1 , wherein the second insulating layer comprises a bonding layer on the embedded barrier interface material and partially defining the bonding surface of the substrate.

3. The substrate of claim 2 , wherein the bonding layer completely covers the embedded barrier interface material.

4. The substrate of claim 2 , wherein the bonding layer comprises silicon and oxygen.

5. The substrate of claim 1 , wherein the embedded barrier interface material extends across the substrate.

6. The substrate of claim 1 , wherein the embedded barrier interface material comprises one or more of silicon nitride, silicon oxynitride, silicon carbide, or silicon carbonitride.

7. The substrate of claim 6 , wherein the embedded barrier interface comprises silicon carbonitride.

8. The substrate of claim 1 , wherein the embedded barrier interface contacts a sidewall of the first conductive interconnect pad.

9. The substrate of claim 8 , wherein the first conductive interconnect pad comprises a barrier material surrounding copper.

10. The substrate of claim 9 , wherein the barrier material comprises tantalum.

11. The substrate of claim 1 , wherein the first insulating layer further comprises a second cavity extending vertically at least partially through the thickness of the first insulating layer and a second conductive interconnect pad at least partially disposed in the second cavity, wherein the embedded barrier interface material extends from the first conductive interconnect pad to the second conductive interconnect pad.

12. The substrate of claim 1 , wherein the second insulating layer is disposed on the embedded barrier interface material.

13. A bonded structure comprising:

a first substrate having a bonding surface, the first substrate comprising:

a first insulating layer having an upper surface and a first cavity extending vertically at least partially through a thickness of the first insulating layer;

a first conductive interconnect pad at least partially disposed in the first cavity;

an embedded barrier interface material disposed on the first insulating layer without extending below the upper surface of the first insulating material, the embedded barrier interface material inhibiting diffusion of conductive material into the first insulating layer from the bonding surface; and

a second insulating layer having a dielectric surface spaced above the embedded barrier interface material, the dielectric surface and an upper surface of the first conductive interconnect pad defining the bonding surface of the first substrate, and

a second substrate including a second an insulating material and a second conductive interconnect pad,

wherein the first substrate and the second substrate are directly bonded to one another without an intervening adhesive.

14. The bonded structure of claim 13 , wherein the dielectric surface of the second insulating layer of the first substrate is directly bonded to the insulating material of the second substrate, and the first conductive interconnect pad is directly bonded to the second conductive interconnect pad.

15. The bonded structure of claim 14 , wherein the dielectric surface of the second insulating layer comprises silicon and oxygen.

16. The bonded structure of claim 15 , wherein the embedded barrier interface material comprises silicon carbonitride.

17. The bonded structure of claim 15 , wherein the embedded barrier interface material comprises silicon nitride.

18. The bonded structure of claim 14 , further comprising a via extending from a lower surface of the first conductive interconnect pad opposite the upper surface of the first conductive interconnect pad.

19. The bonded structure of claim 14 , wherein a width of the first conductive interconnect pad is narrower than a width of the second conductive interconnect pad at the bonding surface.

20. The bonded structure of claim 13 , wherein the second insulating layer is disposed on the embedded barrier interface material.

21. A substrate having a bonding surface, the substrate comprising:

a first insulating material including a first region and a second region, the first region having first and second cavities extending at least partially through a thickness of the first insulating material;

a first conductive interconnect pad at least partially disposed in the first cavity;

a second conductive interconnect pad at least partially disposed in the second cavity; and

a barrier interface in the first region, the barrier interface extending at least between the first and second conductive interconnect pads, the second region being free from the barrier interface,

wherein the bonding surface of the substrate is prepared for direct bonding.

22. The substrate of claim 21 , wherein the first region comprises a conductive interconnect pad region and the barrier interface extends across the first region.

23. The substrate of claim 22 , wherein the first region is surrounded by the second region that is free from the barrier interface.

24. The substrate of claim 21 , wherein the barrier interface is a continuous layer over the first insulating material, the barrier interface including openings therethrough for the first and second conductive interconnect pads.

25. The substrate of claim 21 , wherein the barrier interface comprises one or more of silicon nitride, silicon oxynitride, silicon carbide, or silicon carbonitride.

26. The substrate of claim 25 , wherein the barrier interface comprises silicon carbonitride.

27. The substrate of claim 21 , wherein the barrier interface is an embedded barrier interface that is disposed on an upper surface of the first insulating material without extending below the upper surface of the first insulating material, wherein the bonding surface comprises a dielectric surface spaced above the embedded barrier interface and an upper surface of the first conductive interconnect pad.

28. The substrate of claim 21 , wherein the first and second interconnect pads include sidewall barrier materials surrounding copper.

29. A bonded structure comprising:

a first substrate having a bonding surface, the substrate comprising:

a first insulating material including a first region and a second region, the first region having first and second cavities extending at least partially through a thickness of the first insulating material,

a first conductive interconnect pad at least partially disposed in the first cavity,

a second conductive interconnect pad at least partially disposed in the second cavity, and

a barrier interface in the first region, the barrier interface extending at least between the first and second conductive interconnect pads, the second region being free from the barrier interface; and

a second substrate having a second bonding surface directly bonded to the bonding surface of the substrate without an intervening adhesive.

30. The bonded structure of claim 29 , wherein the first and second conductive interconnect pads of the substrate are directly bonded to corresponding third and fourth conductive interconnect pads of the second substrate.

31. The bonded structure of claim 29 , wherein the barrier interface comprises silicon carbonitride.

32. The bonded structure of claim 29 , wherein the first and second interconnect pads are narrower at the bonding surface than the third and fourth interconnect pads, respectively, at the second bonding surface.

33. The bonded structure of claim 29 , wherein the first and second interconnect pads include sidewall lining layers surrounding copper.

34. The bonded structure of claim 33 , wherein the sidewall lining layers comprise tantalum.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 11, 2024
From: KATKAR, RAJESH; UZOH, CYPRIAN EMEKA
To: INVENSAS BONDING TECHNOLOGIES, INC.
Reel/Frame 067078/0240 →
CHANGE OF NAME Recorded Apr 11, 2024
From: INVENSAS BONDING TECHNOLOGIES, INC.
To: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
Reel/Frame 067098/0111 →
Continuity (4)
Continuation 17313185 · May 6, 2021
Continuation 16143850 · Sep 27, 2018
Provisional Application 62569232 · Oct 6, 2017
Related Publication 20230360968A1 · Nov 9, 2023
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Bush, Steve, “Electronica: Automotive power modules from On Semi,” ElectronicsWeekly.com, indicating an ONSEMI AR0820 product was to be demonstrated at a Nov. 2018 trade show, https://www.electronicsweekly.com/news/prod… [cited by applicant]
Chinese Office Action mailed Nov. 30, 2023, Chinese Application No. 201880055006.5, 11 pages. [cited by applicant]
Morrison, Jim et al., “Samsung Galaxy S7 Edge Teardown,” Tech Insights (posted Apr. 24, 2016), includes description of hybrid bonded Sony IMX260 dual-pixel sensor, https://www.techinsights.com/blog/samsung-galaxy-s7-edg… [cited by applicant]
ONSEMI AR0820 image, cross section of a CMOS image sensor product. The part in the image was shipped on Sep. 16, 2021. Applicant makes no representation that the part in the image is identical to the part identified in … [cited by applicant]
Sony IMX260 image, a first cross section of Sony product labeled IMX260, showing a hybrid bonded back side illuminated CMOS image sensor with a pad opening for a wire bond. The second image shows a second cross-section … [cited by applicant]
Extended European Search Report for EP Appl. No. 18864135.1, mailed May 10, 2021, 10 pages. [cited by applicant]
Extended European Search Report for EP Appl. No. 22166588.8, mailed Oct. 31, 2022, 12 pages. [cited by applicant]
International Search Report and Written Opinion, dated Feb. 1, 2019, for PCT Application No. PCT/US2018/053736, 10 pages. [cited by applicant]
Ker, Ming-Dou et al., “Fully process-compatible layout design on bond pad to improve wire bond reliability in CMOS ICs,” IEEE Transactions on Components and Packaging Technologies, Jun. 2002, vol. 25, No. 2, pp. 309-316. [cited by applicant]
Korean Notice of Final Rejection, in KR 10-2020-7007913, dated Jan. 10, 2022. [cited by applicant]
Moriceau, H. et al., “Overview of recent direct wafer bonding advances and applications,” Advances in Natural Sciences—Nanoscience and Nanotechnology, 2010, 11 pages. [cited by applicant]
Nakanishi, H. et al., “Studies on SiO2—SiO2 bonding with hydrofluoric acid. Room temperature and low stress bonding technique for MEMS,” Sensors and Actuators, 2000, vol. 79, pp. 237-244. [cited by applicant]
Oberhammer, J. et al., “Sealing of adhesive bonded devices on wafer level,” Sensors and Actuators A, 2004, vol. 110, No. 1-3, pp. 407-412, see pp. 407-412, and Figures 1(a)-1(I), 6 pages. [cited by applicant]
Plobi, A. et al., “Wafer direct bonding: tailoring adhesion between brittle materials,” Materials Science and Engineering Review Journal, 1999, R25, 88 pages. [cited by applicant]
Supplementary European Search Report in EP 18864135, dated Apr. 28, 2021. [cited by applicant]
Yang, Chih-Chao et al., “Co Capping Layers for Cu/Low-k Interconnects,” IBM Research, AMC, Albany, NY, Oct. 5-7, 2010, 16 pages. [cited by applicant]
OmniVision OV20880 Press Release, “OmniVision Announces New Family of 20-Megapixel PureCel® Plus-S Sensors for High-End Smartphones,” www.prnewswire.com/news-releases/omnivision-announces-new-family-of-20-megapixel-pure… [cited by applicant]
OmniVision OV20880 Images, cross-section and EDX material analysis of hybrid bonded image sensor product. The part in the images was shipped Sep. 3, 2021. The first image is a cross section showing hybrid bonded parts; … [cited by applicant]
Sony IMX260 Image and Materials Analysis, cross-section and EDX material analysis of hybrid bonded back side illuminated CMOS image sensor. The part in the images was shipped in Apr. 2016. The first image is a cross sec… [cited by applicant]
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US 12,322,650