Granted Patent B2

US 12,451,445 · App. 18/520,337 · Granted Oct 21, 2025

Inventors: Javier A. DeLaCruz (San Jose, CA); Belgacem Haba (Saratoga, CA); Rajesh Katkar (Milpitas, CA)

Assignee: Adeia Semiconductor Bonding Technologies Inc.

H01L23/573H01L22/34H01L23/528H01L23/562H01L24/05H01L24/08H01L24/27H01L24/29H01L24/32H01L24/48H01L24/73H01L24/83H01L24/49H01L2224/08237H01L2224/29082H01L2224/29187H01L2224/32225H01L2224/48091H01L2224/48106H01L2224/48225H01L2224/49171H01L2224/73215

Abstract

Claims (31)

1. A method of forming a bonded structure, the method comprising:

patterning a disruption structure into at least one of a semiconductor element having active circuitry and an obstructive element including an obstructive material disposed over at least a portion of the active circuitry, the obstructive material configured to obstruct external access to the active circuitry; and

directly bonding the obstructive element to the semiconductor element without an adhesive, the disruption structure configured to disrupt functionality of the semiconductor element upon debonding of the obstructive element from the semiconductor element.

2. The method of claim 1 , further comprising depositing a first bonding layer on the semiconductor element and a second bonding layer on the obstructive element, the method comprising directly bonding the first and second bonding layers without an adhesive.

3. The method of claim 2 , further comprising forming a plurality of dielectric layers separated by a plurality of blocking layers, the plurality of dielectric layers comprising a same material as the first bonding layer.

4. The method of claim 2 , further comprising directly bonding a first plurality of contact pads in the first bonding layer to a second plurality of contact pads in the second bonding layer.

5. The method of claim 3 , further comprising forming a first blocking layer in the first bonding layer and an anchor material layer in the second bonding layer, the first blocking layer having one or more openings therethrough.

6. The method of claim 1 , wherein patterning the disruption structure comprises patterning openings through one or more blocking layers within one or more intermediate layers.

7. The method of claim 1 , further comprising patterning openings in the obstructive material to expose portions of the semiconductor element.

8. The method of claim 1 , further comprising monitoring an electrical signal along a conductor disposed at least partially in one or both of the semiconductor element and the obstructive element to determine whether the obstructive element has been debonded from the semiconductor element.

9. A method of forming a bonded structure, the method comprising:

providing a semiconductor element comprising active circuitry;

directly bonding an element to the semiconductor element without an adhesive, the element including a material disposed over at least a portion of the active circuitry; and

providing a conductor connected to a monitoring circuit usable to determine whether the direct bond between the semiconductor element and the element has been tampered with.

10. The method of claim 9 , further comprising depositing a first bonding layer on the semiconductor element and a second bonding layer on the element, the method comprising directly bonding the first and second bonding layers without an adhesive.

11. The method of claim 10 , wherein the first and second bonding layers comprise silicon.

12. The method of claim 10 , further comprising forming one or more intermediate layers between the first bonding layer and the active circuitry, the one or more intermediate layers comprising circuitry, an etch pathway extending through at least a portion of the one or more intermediate layers.

13. The method of claim 12 , wherein the one or more intermediate layers includes a blocking layer, one or more openings formed in the blocking layer, the etch pathway extending through the one or more openings.

14. The method of claim 12 , further comprising at least partially disposing the conductor in the one or more intermediate layers.

15. The method of claim 9 , further comprising monitoring an electrical current through the conductor.

16. The method of claim 15 , further comprising configuring the monitoring circuit to indicate that the direct bond has been tampered with if an electrical signal through the conductor is interrupted.

17. The method of claim 10 , further comprising directly bonding a first plurality of contact pads in the first bonding layer to a second plurality of contact pads in the second bonding layer without an adhesive.

18. The method of claim 17 , further comprising forming a first blocking layer in the first bonding layer and an anchor material layer in the second bonding layer, the first blocking layer having one or more openings therethrough.

19. The method of claim 18 , further comprising partially embedding the second plurality of contact pads in the second blocking layer.

20. The method of claim 17 , further comprising connecting at least one contact pad to the monitoring circuit to monitor connectivity of the directly bonded first and second pluralities of contact pads.

21. The method of claim 9 , wherein the element is an obstructive element, and the material is an obstructive material configured to obstruct external access to the active circuitry.

22. The method of claim 21 , wherein a first hardness of the obstructive material is greater than a second hardness of the semiconductor element.

23. The method of claim 21 , wherein the obstructive material comprises an abrasive material.

24. The method of claim 21 , wherein the obstructive material comprises a light-blocking material.

25. The method of claim 24 , wherein the light-blocking material is configured to block light at near infrared (NIR) wavelengths.

26. The method of claim 9 , wherein the conductor extends from a bond interface between the element and the semiconductor element.

Assignments (2)

Continuity (7)

References Cited (343)