Granted Patent B2

US 12,366,782 · App. 18/104,817 · Granted Jul 22, 2025

Inventor: Shunpei Yamazaki (Setagaya, JP)

Assignee: Semiconductor Energy Laboratory Co., Ltd.

G02F1/1368H10D30/6734H10D30/6755H10D30/6757H10D62/118H10D86/423H10D86/60H10D99/00

Abstract

Claims (69)

1. A semiconductor device comprising:

a metal oxide comprising indium, gallium, and zinc;

a source electrode and a drain electrode comprising a titanium layer and a copper layer over the titanium layer,

a first gate electrode over the metal oxide;

a gate insulating film between the metal oxide and the first gate electrode; and

an insulating film in contact with a top surface and a side surface of the first gate electrode,

the metal oxide comprising:

a channel formation region; and

a first region and a second region on both sides of the channel formation region,

wherein the first gate electrode overlaps with the channel formation region through the gate insulating film and does not overlap with the first region and the second region,

wherein the insulating film comprises a region in contact with a top surface of the first region and a top surface of the second region,

wherein the channel formation region comprises at least two regions having different concentrations of indium,

wherein the at least two regions each comprise a nano-size particle with a size of greater than or equal to 0.5 nm and less than or equal to 10 nm, and

wherein the nano-size particle is dispersed or distributed in a mosaic pattern.

2. The semiconductor device according to claim 1 , wherein hydrogen concentrations of the first region and the second region are higher than a hydrogen concentration of the channel formation region.

3. The semiconductor device according to claim 1 , wherein the first region and the second region are each an n-type region comprising nitrogen.

4. The semiconductor device according to claim 1 , wherein the channel formation region comprises a third region having a first energy band gap and a fourth region having a second energy band gap,

wherein the third region comprises indium or zinc,

wherein the fourth region comprises one or more of indium, gallium, and zinc, and

wherein the second energy band gap is larger than the first energy band gap.

5. The semiconductor device according to claim 4 ,

wherein the first energy band gap is 2.4 eV, and

wherein the second energy band gap is greater than or equal to 3.0 eV and less than or equal to 4.0 eV.

6. The semiconductor device according to claim 1 , further comprising a second gate electrode under the metal oxide,

wherein a length of the second gate electrode is longer than a length of the first gate electrode in a cross-sectional view in a channel length direction, and

wherein the second gate electrode overlaps with the first region and the second region.

7. The semiconductor device according to claim 1 ,

wherein the source electrode is electrically connected to the first region, and

wherein the drain electrode is electrically connected to the second region.

8. A semiconductor device comprising:

a metal oxide comprising indium, gallium, and zinc;

a source electrode and a drain electrode comprising a titanium layer and a copper layer over the titanium layer,

a first gate electrode over the metal oxide;

a gate insulating film between the metal oxide and the first gate electrode;

an insulating film in contact with a top surface and a side surface of the first gate electrode; and

a second gate electrode under the metal oxide,

the metal oxide comprising:

a channel formation region; and

a first region and a second region on both sides of the channel formation region,

wherein the first gate electrode overlaps with the channel formation region through the gate insulating film and does not overlap with the first region and the second region,

wherein the gate insulating film is in contact with the channel formation region and is not in contact with the first region and the second region,

wherein the insulating film comprises a region in direct contact with a top surface of the first region and a top surface of the second region,

wherein hydrogen concentrations of the first region and the second region are higher than a hydrogen concentration of the channel formation region,

wherein the metal oxide comprises a nanocrystal,

wherein a length of the second gate electrode is longer than a length of the first gate electrode in a cross-sectional view in a channel length direction, and

wherein the second gate electrode overlaps with the first region and the second region.

9. The semiconductor device according to claim 8 ,

wherein the source electrode is electrically connected to the first region, and

wherein the drain electrode is electrically connected to the second region.

10. A semiconductor device comprising:

a metal oxide comprising indium, gallium, and zinc;

a source electrode and a drain electrode comprising a titanium layer and a copper layer over the titanium layer,

a first gate electrode over the metal oxide;

a gate insulating film between the metal oxide and the first gate electrode;

an insulating film in contact with a top surface and a side surface of the first gate electrode; and

a second gate electrode under the metal oxide,

the metal oxide comprising:

a channel formation region; and

a first region and a second region on both sides of the channel formation region,

wherein the first gate electrode overlaps with the channel formation region through the gate insulating film and does not overlap with the first region and the second region,

wherein the gate insulating film is in contact with the channel formation region and is not in contact with the first region and the second region,

wherein the insulating film comprises a region in direct contact with a top surface of the first region and a top surface of the second region,

wherein the first region and the second region are each an n-type region comprising nitrogen,

wherein the metal oxide comprises a nanocrystal,

wherein a length of the second gate electrode is longer than a length of the first gate electrode in a cross-sectional view in a channel length direction, and

wherein the second gate electrode overlaps with the first region and the second region.

11. The transistor according to claim 10 ,

wherein the source electrode is electrically connected to the first region, and

wherein the drain electrode is electrically connected to the second region.

Priority Claims (8)

Continuity (4)

References Cited (262)