Patent Assignment
Reel/Frame 017379/0630
Security Agreement
Recorded: 2006-01-03
Received: 2006-01-06
Pages: 28
Assignor
AMKOR TECHNOLOGY, INC.
Executed: 2005-11-23
Assignee
BANK OF AMERICA, N.A.
901 MAIN STREET, 22ND FLOOR, DALLAS, TX, 75202, UNITED STATES
Covered Properties
(100)
Semiconductor Package Having One or More Die Stacked on a Prepackaged Device and Method Therefor
Application:
10/831,505 →
Leadframe Package for Semiconductor Devices
Application:
10/781,220 →
Structures for Improving Heat Dissipation in Stacked Semiconductor Packages
Application:
10/771,072 →
Stacked Semiconductor Die Assembly Having at Least One Support
Application:
10/705,194 →
Method of Making an Integrated Circuit Package
Application:
10/688,710 →
Semiconductor Package and Method for Manufacturing the Same
Application:
10/680,280 →
Semiconductor Package Structure Reducing Warpage and Manufacturing Method Thereof
Application:
10/672,886 →
Reinforced Die Pad Support Structure
Application:
10/669,820 →
Power Semiconductor Package with Strap
Application:
10/618,192 →
Double Downset Double Dambar Suspended Leadframe
Application:
10/614,440 →
Thermally Enhanced Chip Scale Lead on Chip Semiconductor Package and Method of Making Same
Application:
10/610,016 →
Fully-Molded Leadframe Stand-Off Feature
Application:
10/459,097 →
Semiconductor Package with Increased Number of Input and Output Pins
Application:
10/447,012 →
Color Contacts for a Semiconductor Package
Application:
10/437,749 →
Semiconductor Package Having More Reliable Electrical Conductive Patterns
Application:
10/435,888 →
Semiconductor Package Including Low Temperature Co-Fired Ceramic Substrate
Application:
10/427,118 →
Sheet Resin Composition and Process for Manufacturing Semiconductor Device Therewith
Application:
10/427,610 →
Thin Profile Semiconductor Package Which Reduces Warpage and Damage During Laser Markings
Application:
10/425,134 →
Wire Bonding Method for a Semiconductor Package
Application:
10/423,702 →
Semiconductor Package Using a Printed Circuit Board and a Method of Manufacturing the Same
Application:
10/420,977 →
Integrated Circuit Substrate Having Laminated Laser-Embedded Circuit Layers
Application:
10/392,738 →
Leadframe Package for Semiconductor Devices
Application:
10/387,801 →
Semiconductor Package Exhibiting Efficient Lead Placement
Application:
10/383,504 →
Semiconductor Package Capable of Die Stacking
Application:
10/376,988 →
Stacking Structure for Semiconductor Devices Using a Folded Over Flexible Substrate and Method Therefor
Application:
10/370,013 →
Offset Etched Corner Leads for Semiconductor Package
Application:
10/358,621 →
Method of Making a Semiconductor Package Having Exposed Metal Strap
Application:
10/356,046 →
Integrated Circuit Device Packages and Substrates for Making the Packages
Application:
10/354,772 →
Mounting for a Package Containing a Chip
Application:
10/340,256 →
Pre-Molded Leadframe
Application:
10/329,620 →
Semiconductor Package and Method for Fabricating the Same
Application:
10/306,627 →
Wafer Level Package and Fabrication Method
Application:
10/291,050 →
Wafer-Level Chip-Scale Package
Application:
10/285,978 →
Image Sensor Package
Application:
10/286,589 →
Method of Fabricating and Using an Image Sensor Package
Application:
10/286,269 →
Die Down Multi-Media Card and Method of Making Same
Application:
10/266,329 →
Semiconductor Device Including Metal Strap Electrically Coupled Between Semiconductor Die and Metal Leadframe
Application:
10/256,905 →
Lead-Frame Method and Circuit Module Assembly Including Edge Stiffener
Application:
10/251,410 →
Compact Flash Memory Card with Clamshell Leadframe
Application:
10/245,071 →
Exposed Lead Qfp Package Fabricated Through the Use of a Partial Saw Process
Application:
10/237,293 →
Laminated Low-Profile Dual Filter Module for Telecommunications Devices and Method Therefor
Application:
10/235,135 →
Optic Semiconductor Package
Application:
10/227,054 →
Method of Making a Semiconductor Package Including Stacked Semiconductor Dies
Application:
10/224,864 →
Integrated Circuit Having Multiple Power/Ground Connections to a Single External Terminal and Method Therefor
Application:
10/223,749 →
Integrated Circuit Substrate Having Embedded Wire Conductors and Method Therefor
Application:
10/223,747 →
Leadframe Including Corner Leads and Semiconductor Package Using Same
Application:
10/194,557 →
Saw and Etch Singulation Method for a Chip Package
Application:
10/174,603 →
Plastic Integrated Circuit Package and Leadframe for Making the Package
Application:
10/171,702 →
Semiconductor Package and Method for Manufacturing the Same
Application:
10/162,953 →
Injection Molded Lens-Barrel Assembly and Method for Fabricating Lens-Barrel and Mount Assemblies
Application:
10/161,963 →
Semiconductor Package and Method of Making Using Leadframe Having Lead Locks to Secure Leads to Encapsulant
Application:
10/152,945 →
Laser Module and Optical Subassembly
Application:
10/144,905 →
Semiconductor Package Including Isolated Ring Structure
Application:
10/142,222 →
Integrated Circuit Substrate Having Laser-Embedded Conductive Patterns and Method Therefor
Application:
10/138,225 →
Lead Frame with Plated End Leads and Recesses
Application:
10/122,598 →
Shield Cap and Semiconductor Package Including Shield Cap
Application:
10/121,215 →
Carrier Frame and Semiconductor Package Including Carrier Frame
Application:
10/115,218 →
Semiconductor Package and Method for Manufacturing the Same
Application:
10/103,048 →
Flip-Chip Micromachine Package Using Seal Layer
Application:
10/097,905 →
Low Profile Mounting of Thick Integrated Circuit Packages Within Low-Profile Circuit Modules
Application:
10/094,731 →
Reduced Copper Lead Frame for Saw-Singulated Chip Package
Application:
10/093,267 →
Thin Semiconductor Package with Semiconductor Chip and Electronic Discrete Device
Application:
10/086,293 →
Enhanced Chip Scale Package for Wire Bond Dies
Application:
10/078,718 →
Thin Integrated Circuit Package Having an Optically Transparent Window
Application:
10/067,068 →
Integrated Circuit Package Mounting
Application:
10/068,717 →
Semiconductor Package Including Rings Structure Connected to Leads with Vertically Downset Inner Ends
Application:
10/054,124 →
Optical Device Packages Having Improved Conductor Efficiency, Optical Coupling and Thermal Transfer
Application:
10/046,995 →
Reduced Size Semiconductor Package with Stacked Dies
Application:
10/043,946 →
Semiconductor Package Including Flip Chip
Application:
10/034,656 →
Sensor Module with Integrated Discrete Components
Application:
10/012,378 →
Lead Frame for Semiconductor Package
Application:
10/013,160 →
Structures for Improving Heat Dissipation in Stacked Semiconductor Packages
Application:
10/013,396 →
Printed Circuit Board with Integral Heat Sink for Semiconductor Package
Application:
10/006,642 →
Multi-Layer Lead Frame Structure
Application:
09/996,226 →
Power Semiconductor Package with Strap
Application:
10/008,048 →
Method of Making an Integrated Circuit Package
Application:
10/007,337 →
Semiconductor Package with Optimized Leadframe Bonding Strength
Application:
09/998,844 →
Apparatus and Method for Allowing Testing of Semiconductor Devices at Different Temperatures
Application:
09/978,535 →
Semiconductor Package with Singulation Crease
Application:
09/976,866 →
Semiconductor Package Having Stacked Semiconductor Chips and Method of Making the Same
Application:
09/974,541 →
Lead-Frame Method and Assembly for Interconnecting Circuits Within a Circuit Module
Application:
09/956,190 →
Semiconductor Package Having Multiple Dies with Independently Biased Back Surfaces
Application:
09/953,422 →
Quick Sealing Glass-Lidded Package
Application:
09/946,750 →
Quick Sealing Glass-Lidded Package Fabrication Method
Application:
09/946,861 →
Placement Template and Method for Placing Optical Dies
Application:
09/943,068 →
Vcsel Package and Fabrication Method
Application:
09/940,103 →
Method and Circuit Module Package for Automated Switch Actuator Insertion
Application:
09/934,040 →
Semiconductor Package Having Substrate with Laser-Formed Aperture Through Solder Mask Layer
Application:
09/932,528 →
Solderable Injection-Molded Integrated Circuit Substrate and Method Therefor
Application:
09/931,144 →
Integrated Circuit Package Including Pin and Barrel Interconnects
Application:
09/932,109 →
Laser Defined Pads for Flip Chip on Leadframe Package
Application:
09/929,239 →
Laser Defined Pads for Flip Chip on Leadframe Package Fabrication Method
Application:
09/929,428 →
Reduced Thickness Packaged Electronic Device
Application:
09/916,716 →
Pre-Drilled Ball Grid Array Package
Application:
09/916,848 →
Method for Forming a Reduced Thickness Packaged Electronic Device
Application:
09/916,719 →
Integrated Circuit Chip Package Having an Internal Lead
Application:
09/909,160 →
Method of Fabricating and Using an Image Sensor Package with Reflector
Application:
09/906,868 →
Image Sensor Package with Reflector
Application:
09/906,992 →
Method for Molding Semiconductor Package Having a Ceramic Substrate
Application:
09/895,767 →
Pre-Drilled Image Sensor Package Fabrication Method
Application:
09/896,074 →