Granted Patent B2

US 12,381,128 · App. 17/562,967 · Granted Aug 5, 2025

Inventors: Guilian Gao (San Jose, CA); Gaius Gillman Fountain, Jr. (Youngsville, NC)

Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

H01L23/481H01L21/76816H01L21/76843H01L21/76877H01L21/76898

Abstract

Claims (32)

1. A microelectronic structure comprising:

a bulk semiconductor portion having a first surface and a second surface opposite the first surface;

a via structure extending at least partially through the bulk semiconductor portion along a direction non-parallel to the first surface;

a first dielectric barrier layer disposed on the first surface of the bulk semiconductor portion and extending to the via structure; and

a second dielectric layer disposed on the first dielectric barrier layer and extending to the via structure,

wherein the second surface of the bulk semiconductor portion comprises an active surface that includes active circuitry, and one or more back-end-of-line layers over the active surface.

2. The microelectronic structure of claim 1 , wherein the via structure comprises a conductive via and a dielectric liner disposed around the conductive via, the second dielectric layer extending to the dielectric liner.

3. The microelectronic structure of claim 2 , wherein the via structure comprises a second barrier layer extending along the conductive via between the conductive via and the dielectric liner.

4. The microelectronic structure of claim 1 , wherein the second dielectric layer comprises a dielectric layer that includes silicon oxynitride.

5. The microelectronic structure of claim 1 , wherein the second dielectric layer comprises a high temperature silicon oxide layer.

6. The microelectronic structure of claim 1 , wherein the second dielectric layer comprises a dielectric layer that includes silicon oxycarbonitride.

7. The microelectronic structure of claim 1 , wherein a first sidewall of the bulk semiconductor portion adjacent the via structure has first artifacts indicative of a first etching process and a second sidewall of the dielectric layer adjacent the via structure has second artifacts indicative of a second etching process different from the first etching process.

8. The microelectronic structure of claim 7 , wherein the first and second artifacts have different surface roughness profiles along the first and second sidewalls.

9. The microelectronic structure of claim 8 , wherein the first artifacts comprise ridges indicative of a Bosch etch process.

10. The microelectronic structure of claim 1 , wherein the first dielectric barrier layer comprises silicon nitride.

11. The microelectronic structure of claim 1 , wherein the second dielectric layer and the via structure are hybrid bonded to another element without an intervening adhesive along a bonding interface.

12. The microelectronic structure of claim 1 , wherein the second dielectric layer and the via structure are directly bonded to another element without an intervening adhesive along a bonding interface.

13. The microelectronic structure of claim 1 , wherein the via structure has an end surface that is recessed relative to a surface of the second dielectric layer that is opposite the bulk semiconductor portion, and the end surface of the via structure and the surface of the dielectric layer comprise planarized surfaces.

14. The microelectronic structure of claim 12 , wherein the second dielectric layer and the via structure are hybrid bonded to another element without an intervening adhesive along a bonding interface.

15. A microelectronic structure comprising:

a bulk semiconductor portion having a first surface and a second surface opposite the first surface;

a dielectric layer disposed over the first surface of the bulk semiconductor portion; and

a via structure extending at least partially through the bulk semiconductor portion and through the dielectric layer along a direction non-parallel to the first surface, wherein a first sidewall of the bulk semiconductor portion adjacent the via structure has first artifacts indicative of a first etching process, and a second sidewall of the dielectric layer adjacent the via structure has second artifacts indicative of a second etching process different from the first etching process.

16. The microelectronic structure of claim 15 , wherein a barrier dielectric layer intervenes between the dielectric layer and the bulk semiconductor portion but does not intervene between the dielectric layer and the via structure, and the via structure comprises a conductive via and a dielectric liner disposed around the conductive via, the dielectric layer extending to the dielectric liner.

17. The microelectronic structure of claim 15 , wherein the second dielectric layer comprises a high temperature silicon oxide layer.

18. The microelectronic structure of claim 15 , wherein the first and second artifacts have different surface roughness profiles along the first and second sidewalls.

19. The microelectronic structure of claim 15 , wherein the dielectric layer and the via structure are directly bonded to another element without an intervening adhesive along a bonding interface.

20. A microelectronic structure comprising:

a bulk semiconductor portion having a first surface and a second surface opposite the first surface;

a via structure extending at least partially through the bulk semiconductor portion along a direction non-parallel to the first surface;

a dielectric layer disposed on the bulk semiconductor portion and extending to the via structure, the dielectric layer comprising a high temperature silicon oxide layer,

wherein a barrier dielectric layer intervenes between the dielectric layer and the bulk semiconductor portion but does not intervene between the dielectric layer and the via structure.

Assignments (3)

Continuity (2)

References Cited (400)