IP Library Granted Patent US 12,300,662
Granted Patent B2
US 12,300,662 · App. 18/653,243 · Granted May 13, 2025

DBI to SI bonding for simplified handle wafer

Inventors: Chandrasekhar Mandalapu (Morrisville, NC); Gaius Gillman Fountain, Jr. (Youngsville, NC); Guilian Gao (Campbell, CA)
Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
H01L24/83H01L21/6836H01L21/78H01L24/03H01L24/08H01L24/09H01L24/32H01L24/33H01L24/98H01L2221/68327H01L2221/68368H01L2221/68381H01L2224/03002H01L2224/08145H01L2224/09181H01L2224/32145H01L2224/33181H01L2224/80895H01L2224/83009H01L2224/83896H01L2224/83948
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Quick Facts
Patent No.
US 12,300,662
App. No.
18/653,243
Filed
May 2, 2024
Granted
May 13, 2025
Kind
B2
Art Unit
2898
USPC
257/777
Abstract

Devices and techniques include process steps for preparing various microelectronic components for bonding, such as for direct bonding without adhesive. The processes include providing a first bonding surface on a first surface of the microelectronic components, bonding a handle to the prepared first bonding surface, and processing a second surface of the microelectronic components while the microelectronic components are gripped at the handle. In some embodiments, the processes include removing the handle from the first bonding surface, and directly bonding the microelectronic components at the first bonding surface to other microelectronic components.

Claims (44)

1. A method comprising:

preparing a bonding surface of a first bonding layer on a substrate;

direct bonding a first side of a first microelectronic component to the bonding surface using a direct non-adhesive technique to form at least a portion of a structure;

while the substrate supports the first microelectronic component, forming a second bonding layer on a surface on a second side of the of the first microelectronic component, wherein the second side is opposite the first side;

hybrid bonding a second microelectronic component to the second bonding layer;

after hybrid bonding the second microelectronic component to the second bonding layer, removing at least the substrate by grinding or polishing the substrate; and

singulating the structure to form a plurality of microelectronic units, wherein a first microelectronic unit of the plurality of microelectronic units comprises the first microelectronic component.

2. The method of claim 1 , wherein the second bonding layer comprises a first conductive feature and a first dielectric region, wherein the second microelectronic component comprises a second conductive feature and a second dielectric region, and wherein hybrid bonding the second microelectronic component to the bonding layer comprises directly bonding the first and second conductive features and directly bonding the first and second dielectric regions using the direct non-adhesive technique.

3. The method of claim 1 , wherein preparing the bonding surface of the substrate comprises a plasma activating bonding surface.

4. The method of claim 1 , wherein removing the substrate by grinding or polishing the substrate comprises exposing the first side of the first microelectronic component.

5. The method of claim 4 , further comprising:

after removing the substrate, processing the exposed first side of the microelectronic component to form a second bonding surface over the exposed first side.

6. The method of claim 5 , wherein processing the exposed first side of the microelectronic component to form the second bonding surface comprises polishing the first side.

7. The method of claim 1 , further comprising:

before forming the bonding layer over the surface, planarizing the second side of the first microelectronic component.

8. The method of claim 1 , further comprising:

before forming the bonding layer over the surface, polishing the second side of the first microelectronic component to form the surface.

9. The method of claim 1 , further comprising:

before forming the bonding layer over the surface, forming more than one protective layer over the second side of the first microelectronic component.

10. The method of claim 1 , further comprising singulating to form a plurality of microelectronic units, a first microelectronic unit of the plurality of microelectronic units comprising the first and second microelectronic components.

11. A method comprising:

direct bonding a first side of a first microelectronic component to a first bonding layer on a substrate using a direct non-adhesive technique to form at least a portion of a structure;

while the substrate supports the first microelectronic component, planarizing a second side of the first microelectronic component and providing a second bonding layer on the second side, wherein the second side faces away from the substrate;

hybrid bonding a second microelectronic component to the second bonding layer without an adhesive, wherein the second bonding layer on the first microelectronic component comprises a first conductive feature and the second microelectronic component comprises a second conductive feature directly bonded to the first conductive feature;

removing at least the substrate by grinding or polishing the substrate; and

singulating the structure to form a plurality of microelectronic units, wherein a first microelectronic unit of the plurality of microelectronic units comprises the first microelectronic component.

12. The method of claim 11 , further comprising:

after removing the substrate, forming a bonding surface on the first side of the first microelectronic component.

13. The method of claim 12 , wherein forming the bonding surface on the first side of the microelectronic component comprises polishing the first side of the microelectronic component.

14. The method of claim 11 , further comprising:

while the substrate supports the first microelectronic component, forming more than one type of protective layer on the second side of the first microelectronic component.

15. The method of claim 11 , wherein direct bonding the first side of the first microelectronic component to the substrate comprises direct bonding the first side of the first microelectronic component to a bonding surface of the first bonding layer on the substrate, the method further comprising:

before direct bonding the first side of the first microelectronic component to a bonding surface of the first bonding layer on the substrate, plasma activating the bonding surface.

16. A method comprising:

providing a structure comprising a first side of a first microelectronic component directly bonded to a first bonding layer on a substrate using a direct non-adhesive technique;

while the substrate supports the first microelectronic component, processing the first microelectronic component to form a second bonding layer on a second side of the first microelectronic component, wherein the second bonding layer faces away from the substrate;

hybrid bonding a second microelectronic components to the second bonding layer;

removing at least the substrate to expose the first side of the first microelectronic component, the removing comprising grinding or polishing the substrate;

polishing the first side of the first microelectronic component; and

singulating the structure to form a plurality of microelectronic units, wherein a first microelectronic unit of the plurality of microelectronic units comprises the first microelectronic component.

17. The method of claim 16 , wherein removing the substrate comprises removing the substrate by grinding the substrate.

18. The method of claim 16 , wherein the second bonding layer comprises a first conductive feature and the second microelectronic component comprises a second conductive feature and wherein the first and second conductive features are directly bonded to each other.

19. The method of claim 16 , wherein processing the first microelectronic component comprises applying more than one type of protective coating over the second side of the first microelectronic component.

20. The method of claim 16 , wherein processing the first microelectronic component comprises planarizing the first microelectronic component.

Assignments (3)
SECURITY INTEREST Recorded May 28, 2025
From: ADEIA INC. (F/K/A XPERI HOLDING CORPORATION); ADEIA HOLDINGS INC.; ADEIA MEDIA HOLDINGS INC.; ADEIA IMAGING LLC; ADEIA MEDIA LLC; ADEIA MEDIA SOLUTIONS INC.; ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.; ADEIA TECHNOLOGIES INC.; ADEIA GUIDES INC.; ADEIA SOLUTIONS LLC; ADEIA SEMICONDUCTOR ADVANCED TECHNOLOGIES INC.; ADEIA SEMICONDUCTOR SOLUTIONS LLC; ADEIA SEMICONDUCTOR INTELLECTUAL PROPERTY LLC; ADEIA SEMICONDUCTOR TECHNOLOGIES LLC; ADEIA PUBLISHING INC.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 071454/0343 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 13, 2024
From: MANDALAPU, CHANDRASEKHAR; FOUNTAIN, GAIUS GILLMAN, JR.; GAO, GUILIAN
To: INVENSAS BONDING TECHNOLOGIES, INC.
Reel/Frame 067389/0118 →
CHANGE OF NAME Recorded May 13, 2024
From: INVENSAS BONDING TECHNOLOGIES, INC.
To: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
Reel/Frame 067397/0224 →
Continuity (5)
Continuation 18464982 · Sep 11, 2023
Continuation 17209638 · Mar 23, 2021
Continuation 16386261 · Apr 17, 2019
Provisional Application 62660509 · Apr 20, 2018
Related Publication 20240282747A1 · Aug 22, 2024
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