IP Library Granted Patent US 12,341,125
Granted Patent B2
US 12,341,125 · App. 18/671,851 · Granted Jun 24, 2025

Dimension compensation control for directly bonded structures

Inventors: Guilian Gao (San Jose, CA); Laura Wills Mirkarimi (Sunol, CA); Gaius Gillman Fountain, Jr. (Youngsville, NC); Cyprian Emeka Uzoh (San Jose, CA)
Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
H01L24/80H01L24/08H01L2224/08145H01L2224/80031H01L2224/80143H01L2224/80895H01L2224/80896
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Quick Facts
Patent No.
US 12,341,125
App. No.
18/671,851
Granted
Jun 24, 2025
Kind
B2
Abstract

A method of direct hybrid bonding first and second semiconductor elements of differential thickness is disclosed. The method can include patterning a plurality of first contact features on the first semiconductor element. The method can include second a plurality of second contact features on the second semiconductor element corresponding to the first contact features for direct hybrid bonding. The method can include applying a lithographic magnification correction factor to one of the first patterning and second patterning without applying the lithographic magnification correction factor to the other of the first patterning and the second patterning. In various embodiments, a differential expansion compensation structure can be disposed on at least one of the first and the second semiconductor elements. The differential expansion compensation structure can be configured to compensate for differential expansion between the first and second semiconductor elements to reduce misalignment between at least the second and fourth contact features.

Claims (35)

1. A method of bonding a first element and a second element, the method comprising:

providing a first semiconductor element having a first bonding surface, the first bonding surface including a first contact feature at an inner portion of the first semiconductor element and a second contact feature at a peripheral portion of the first semiconductor element, the first element having a first thickness;

providing a second semiconductor element having a second bonding surface, the second bonding surface having a third contact feature at an inner portion of the second semiconductor element and a fourth contact feature at a peripheral portion of the second semiconductor element, the second semiconductor element having a second thickness less than the first thickness;

bonding the first bonding surface to the second bonding surface such that the first contact feature is bonded to the third contact feature and the second contact feature is bonded to the fourth contact feature, wherein the bonding comprises directly bonding without an intervening adhesive; and

providing a differential expansion compensation structure on at least one of the first and second elements, the differential expansion compensation structure configured to compensate for differential expansion between the first and second semiconductor elements to reduce misalignment between at least the second and fourth contact features.

2. The method of claim 1 , wherein providing the differential expansion compensation structure comprises providing one or more dielectric layers on a back side of the second semiconductor element, the back side opposite the second bonding surface, the one or more dielectric layers comprises a compressive layer configured to counterbalance stresses at or near the second bonding surface.

3. The method of claim 2 , wherein the differential expansion compensation structure comprises a plurality of dielectric layers, wherein the plurality of dielectric layers comprises a first dielectric layer on the back side of the second semiconductor element and a second dielectric layer on a third semiconductor element, and wherein providing the differential expansion compensation structure comprises directly bonding the second dielectric layer to the first dielectric layer without an adhesive.

4. The method of claim 2 , wherein the differential expansion compensation structure comprises a plurality of dielectric layers, wherein the plurality of dielectric layers comprises a first dielectric layer and a second dielectric layer, and wherein providing the differential expansion compensation structure comprises providing a metal layer between the first and second dielectric layers.

5. The method of claim 1 , wherein providing the differential expansion compensation structure comprises forming one or more dicing street etches in at least one of the first and the second semiconductor elements.

6. The method of claim 1 , wherein providing the differential expansion compensation structure comprises diffusing hydrogen ions into the second semiconductor element by exposing the second element to a hydrogen-containing plasma.

7. The method of claim 1 , further comprising:

before the bonding, obtaining a lithographic magnification correction factor to compensate for differential expansion between the first and second semiconductor elements at their different thicknesses at the time of bonding;

first patterning a first plurality of contact features on the first semiconductor element;

second patterning a second plurality of contact features on the second semiconductor element; and

applying the lithographic magnification correction factor to one of the first patterning and second patterning without applying the lithographic magnification correction factor to the other of the first patterning and the second patterning.

8. A bonded structure comprising:

a first semiconductor element having a first bonding surface, the first bonding surface including a first contact feature at an inner portion of the first semiconductor element and a second contact feature at a peripheral portion of the first semiconductor element, the first element having a first thickness;

a second semiconductor element having a second bonding surface directly bonded to the first bonding surface of the first semiconductor element without an intervening adhesive, the second bonding surface having a third contact feature at an inner portion of the second semiconductor element and a fourth contact feature at a peripheral portion of the second semiconductor element, the second semiconductor element having a second thickness, wherein the first contact feature is bonded to the third contact feature, and wherein the second contact feature is bonded to the fourth contact feature; and

a differential expansion compensation structure on at least one of the first and the second semiconductor elements, the differential expansion compensation structure configured to compensate for differential expansion between the first and second semiconductor elements to reduce misalignment between at least the second and fourth contact features.

9. The bonded structure of claim 8 , wherein the second thickness is less than the first thickness at least before the first and second elements are bonded.

10. The bonded structure of claim 8 , wherein the differential expansion compensation structure comprises one or more dielectric layers on a back side of the second semiconductor element, the back side opposite the second bonding surface, wherein the one or more dielectric layers comprises a stressed layer configured to counterbalance stresses at or near the second bonding surface.

11. The bonded structure of claim 8 , wherein the differential expansion compensation structure further comprises a third semiconductor element, wherein the plurality of dielectric layers comprises a first dielectric layer on the back side of the second semiconductor element and a second dielectric layer on the third semiconductor element, the first and second dielectric layers directly bonded to one another without an adhesive, and wherein the second and third semiconductor elements having different coefficients of thermal expansion.

12. The bonded structure of claim 11 , wherein the first and second dielectric layers are embedded between a first semiconductor portion of the second element and a second semiconductor portion of the third element.

13. The bonded structure of claim 8 , wherein the second element comprises a compound semiconductor layer on a carrier dielectric layer, the compound semiconductor layer disposed between the second bonding surface and the carrier dielectric layer.

14. The bonded structure of claim 8 , wherein the plurality of dielectric layers comprises a first dielectric layer and a second dielectric layer, the differential expansion compensation structure further comprising a metal layer between the first and second dielectric layers.

15. The bonded structure of claim 8 , wherein the differential expansion compensation structure comprises one or more dicing street etches in at least one of the first and the second semiconductor elements.

16. The bonded structure of claim 8 , wherein the differential expansion compensation structure comprises a signature indicative of hydrogen ion diffusion into the second semiconductor element.

17. A method of bonding a first element and a second element, the method comprising:

providing a first semiconductor element having a first bonding surface, the first bonding surface including a first contact feature at a peripheral portion of the first semiconductor element, the first element having a first thickness;

providing a second semiconductor element having a second bonding surface, the second bonding surface having a second contact feature at a peripheral portion of the second semiconductor element, the second semiconductor element having a second thickness less than the first thickness;

bonding the first bonding surface to the second bonding surface such that the first contact feature is bonded to the second contact feature, wherein the bonding comprises directly bonding without an intervening adhesive; and

providing a differential expansion compensation structure on at least one of the first and second elements, the differential expansion compensation structure configured to compensate for differential expansion between the first and second semiconductor elements to reduce misalignment between at least the first and second contact features.

18. The method of claim 17 , wherein providing the differential expansion compensation structure comprises providing one or more dielectric layers on a back side of the second semiconductor element, the back side opposite the second bonding surface, the one or more dielectric layers comprises a compressive layer configured to counterbalance stresses at or near the second bonding surface.

19. The method of claim 18 , wherein the differential expansion compensation structure comprises a plurality of dielectric layers, wherein the plurality of dielectric layers comprises a first dielectric layer on the back side of the second semiconductor element and a second dielectric layer on a third semiconductor element, and wherein providing the differential expansion compensation structure comprises directly bonding the second dielectric layer to the first dielectric layer without an adhesive.

20. The method of claim 18 , wherein the differential expansion compensation structure comprises a plurality of dielectric layers, wherein the plurality of dielectric layers comprises a first dielectric layer and a second dielectric layer, and wherein providing the differential expansion compensation structure comprises providing a metal layer between the first and second dielectric layers.

Assignments (3)
SECURITY INTEREST Recorded May 28, 2025
From: ADEIA INC. (F/K/A XPERI HOLDING CORPORATION); ADEIA HOLDINGS INC.; ADEIA MEDIA HOLDINGS INC.; ADEIA IMAGING LLC; ADEIA MEDIA LLC; ADEIA MEDIA SOLUTIONS INC.; ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.; ADEIA TECHNOLOGIES INC.; ADEIA GUIDES INC.; ADEIA SOLUTIONS LLC; ADEIA SEMICONDUCTOR ADVANCED TECHNOLOGIES INC.; ADEIA SEMICONDUCTOR SOLUTIONS LLC; ADEIA SEMICONDUCTOR INTELLECTUAL PROPERTY LLC; ADEIA SEMICONDUCTOR TECHNOLOGIES LLC; ADEIA PUBLISHING INC.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 071454/0343 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 23, 2024
From: GAO, GUILIAN; MIRKARIMI, LAURA WILLS; FOUNTAIN, GAIUS GILLMAN, JR.; UZOH, CYPRIAN EMEKA
To: INVENSAS BONDING TECHNOLOGIES, INC.
Reel/Frame 067508/0673 →
CHANGE OF NAME Recorded May 23, 2024
From: INVENSAS BONDING TECHNOLOGIES, INC.
To: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
Reel/Frame 067527/0215 →
Continuity (3)
Continuation 17206725 · Mar 19, 2021
Provisional Application 62991775 · Mar 19, 2020
Related Publication 20240312953A1 · Sep 19, 2024
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