Flip-chip semiconductor-on-insulator transistor layout
A flip-chip semiconductor-on-insulator die includes a substrate layer, an active layer, an insulator layer between the substrate layer and the active layer, a first metal layer, and a first via layer between the active layer and the first metal layer. The die at least first and second contact pads and a transistor including a first terminal formed within the active layer. A first portion of the first terminal falls within a footprint of the first contact pad and a second portion of the first terminal falls within a footprint of the second contact pad.
1. A semiconductor-on-insulator die comprising:
a substrate layer, an active layer, an insulator layer between the substrate layer and the active layer, a first metal layer, and a second metal layer, the first metal layer between the active layer and the second metal layer;
at least one contact pad, the second metal layer between the at least one contact pad and the first metal layer;
a transistor including a first terminal, the first terminal formed within the active layer; and
a conductive path extending between the first terminal and the at least one contact pad through at least the first metal layer and the second metal layer, at least a first portion of the conductive path extending in a straight-line path from the first terminal to the at least one contact pad, the at least one contact pad including a first contact pad and a second contact pad, the first portion of the conductive path extending in a straight-line path from the first terminal to the first contact pad, and a second portion of the conductive path extending in a straight-line path from the first terminal to the second contact pad.
2. The semiconductor-on-insulator die of claim 1 wherein the transistor is a field effect transistor and the first terminal is a source of the transistor.
3. The semiconductor-on-insulator die of claim 1 wherein the conductive path further includes at least a second portion extending between the first terminal and the at least one contact pad and which resides at least partly outside of a footprint of the at least one contact pad.
4. The semiconductor-on-insulator die of claim 1 wherein a footprint of the at least one contact pad overlaps with a footprint of the transistor.
5. The semiconductor-on-insulator die of claim 4 wherein at least 50 percent of the first terminal falls within the footprint of the at least one contact pad.
6. The semiconductor-on-insulator die of claim 1 wherein the semiconductor-on-insulator die is a flip-chip die and the at least one contact pad includes at least one contact bump.
7. A semiconductor-on-insulator die comprising:
a substrate layer, an active layer, an insulator layer between the substrate layer and the active layer, a first metal layer, and a second metal layer, the first metal layer between the active layer and the second metal layer;
at least one contact pad, the second metal layer between the at least one contact pad and the first metal layer;
a transistor including a first terminal, the first terminal formed within the active layer; and
a conductive path extending between the first terminal and the at least one contact pad through at least the first metal layer and the second metal layer, at least a first portion of the conductive path extending in a straight-line path from the first terminal to the at least one contact pad, the conductive path including a first via segment formed within a first via layer and a first metal segment formed within the first metal layer, the first via layer between the active layer and the first metal layer, a surface area of an interface between the first via segment and the first terminal being at least 5 percent of a surface area of the first terminal.
8. The semiconductor-on-insulator die of claim 7 wherein the first terminal substantially completely overlaps with the first via segment.
9. The semiconductor-on-insulator die of claim 7 further comprising a second via layer, the second via layer between the first metal layer and the second metal layer, the conductive path further including a second via segment formed from the second via layer and a second metal segment formed from the second metal layer.
10. The semiconductor-on-insulator die of claim 9 wherein the surface area of an interface between the first metal segment and the second via segment is at least 15 percent of the surface area of the first metal segment.
11. A semiconductor-on-insulator die comprising:
a substrate layer, an active layer, an insulator layer between the substrate layer and the active layer, a first metal layer, and a second metal layer, the first metal layer between the active layer and the second metal layer;
at least one contact pad, the second metal layer between the at least one contact pad and the first metal layer;
a transistor including a first terminal, the first terminal formed within the active layer; and
a conductive path extending between the first terminal and the at least one contact pad through at least the first metal layer and the second metal layer, at least a first portion of the conductive path extending in a straight-line path from the first terminal to the at least one contact pad, the transistor including a first section and a second section, the at least one contact pad including a first contact pad and a second contact pad, a footprint of the first contact pad overlapping with a footprint of the first section, and a footprint of the second contact pad overlapping with a footprint of the second section.
12. The semiconductor-on-insulator die of claim 11 wherein the first portion of the conductive path extends in a straight-line path from the first terminal to the first contact pad, and a second portion of the conductive path extends in a straight-line path from the first terminal to the second contact pad.
13. A packaged module comprising:
a semiconductor-on-insulator die including a substrate layer, an active layer, an insulator layer between the substrate layer and the active layer, a first metal layer, and a second metal layer, the first metal layer between the active layer and the second metal layer, the die further including at least one contact pad and a transistor including a first terminal, the first terminal formed within the active layer, the second metal layer between the at least one contact pad and the first metal layer;
a ground plane electrically connected to the at least one contact pad; and
a conductive path extending between the first terminal and the ground plane through at least the first metal layer, the second metal layer, and the at least one contact pad, at least a first portion of the conductive path extending in a straight-line path from the first terminal to the ground plane.
14. The packaged module of claim 13 wherein the at least one contact pad includes a first contact pad and a second contact pad, the first portion of the conductive path extends in a straight-line path from the first terminal to the ground plane through at least the first metal layer, the second metal layer, and the first contact pad, and a second portion of the conductive path extends in a straight-line path from the first terminal to the ground plane through at least the first metal layer, the second metal layer, and the second contact pad.
15. The packaged module of claim 13 further comprising a module metal layer between the ground plane and the at least one contact pad.
16. The packaged module of claim 15 further comprising a module via layer between the module metal layer and the ground plane, and a module via segment formed within the module via layer, the conductive path further including the module via segment.
17. A power amplifier system comprising:
a semiconductor-on-insulator die including a substrate layer, an active layer, an insulator layer between the substrate layer and the active layer, a first metal layer, and a second metal layer, the first metal layer between the active layer and the second metal layer, the die further including at least one contact pad and a transistor including a first terminal, the first terminal formed within the active layer, the second metal layer between the at least one contact pad and the first metal layer; and
a power amplifier configured to amplify a radio frequency signal and including a first transistor formed in the semiconductor-on-insulator die, the first transistor including a first terminal formed within the active layer of the semiconductor-on-insulator die, a conductive path extending between the first terminal and the at least one contact pad through at least the first metal layer and the second metal layer, at least a first portion of the conductive path extending in a straight-line path from the first terminal to the at least one contact pad.
18. The power amplifier system of claim 17 wherein the first transistor is a field effect transistor and the first terminal is a source terminal.
19. The power amplifier system of claim 18 wherein the power amplifier further includes a second transistor formed in the semiconductor-on-insulator die, the second transistor being a field effect transistor.
20. The power amplifier system of claim 17 wherein the at least one contact pad includes a first contact pad and a second contact pad, the first portion of the conductive path extends in a straight-line path from the first terminal to the first contact pad, and a second portion of the conductive path extends in a straight-line path from the first terminal to the second contact pad.