Semiconductor device
Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.
1. A semiconductor device comprising:
a shift register circuit comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, one of a source and a drain of the sixth transistor, and a first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,
wherein a gate of the first transistor is electrically connected to one of a source and a drain of the third transistor, one of a source and a drain of the fourth transistor, and one of a source and a drain of the fifth transistor,
wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the sixth transistor,
wherein a gate of the second transistor is electrically connected to a gate of the third transistor, one of a source and a drain of the seventh transistor, and one of a source and a drain of the eighth transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the fifth transistor,
wherein a gate of the fourth transistor is electrically connected to the other of the source and the drain of the fourth transistor and a third wiring,
wherein a gate of the fifth transistor is electrically connected to a fourth wiring,
wherein a gate of the sixth transistor is electrically connected to a fifth wiring,
wherein a gate of the seventh transistor is electrically connected to one of a source and a drain of the ninth transistor,
wherein the other of the source and the drain of the eighth transistor is electrically connected to the other of the source and the drain of the ninth transistor,
wherein a gate of the eighth transistor is electrically connected to a gate of the ninth transistor,
wherein a gate of the ninth transistor is electrically connected to one of a source and a drain of the tenth transistor and one of a source and a drain of the eleventh transistor,
wherein the first wiring is configured to transmit an output signal,
wherein the second wiring is configured to transmit a clock signal,
wherein the third wiring is configured to transmit a first signal,
wherein the fourth wiring is configured to transmit a second signal, and
wherein the fifth wiring is configured to transmit a third signal.
2. A semiconductor device comprising:
a shift register circuit comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, one of a source and a drain of the sixth transistor, and a first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,
wherein a gate of the first transistor is electrically connected to one of a source and a drain of the third transistor, one of a source and a drain of the fourth transistor, and one of a source and a drain of the fifth transistor,
wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the sixth transistor,
wherein a gate of the second transistor is electrically connected to a gate of the third transistor, one of a source and a drain of the seventh transistor, and one of a source and a drain of the eighth transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the fifth transistor,
wherein a gate of the fourth transistor is electrically connected to the other of the source and the drain of the fourth transistor and a third wiring,
wherein a gate of the fifth transistor is electrically connected to a fourth wiring,
wherein a gate of the sixth transistor is electrically connected to a fifth wiring,
wherein a gate of the seventh transistor is electrically connected to one of a source and a drain of the ninth transistor,
wherein the other of the source and the drain of the eighth transistor is electrically connected to the other of the source and the drain of the ninth transistor,
wherein a gate of the eighth transistor is electrically connected to a gate of the ninth transistor, and
wherein a gate of the ninth transistor is electrically connected to one of a source and a drain of the tenth transistor and one of a source and a drain of the eleventh transistor.
3. A semiconductor device comprising:
a shift register circuit comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, one of a source and a drain of the sixth transistor, and a first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,
wherein a gate of the first transistor is electrically connected to one of a source and a drain of the third transistor, one of a source and a drain of the fourth transistor, and one of a source and a drain of the fifth transistor,
wherein a gate of the second transistor is electrically connected to a gate of the third transistor, one of a source and a drain of the seventh transistor, and one of a source and a drain of the eighth transistor,
wherein a gate of the fourth transistor is electrically connected to a third wiring,
wherein a gate of the fifth transistor is electrically connected to a fourth wiring,
wherein a gate of the seventh transistor is electrically connected to one of a source and a drain of the ninth transistor, and
wherein a gate of the eighth transistor is electrically connected to a gate of the ninth transistor.