Fluid channel geometry optimizations to improve cooling efficiency
Embodiments herein provide for fluidic cooling assemblies embedded within a device package and related manufacturing methods. In one embodiment, the integrated cooling assembly includes a semiconductor device and a cold plate attached to the semiconductor device. The cold plate has a perimeter sidewall, a top portion and pairs of opposing cavity sidewalls. The perimeter sidewall extends downwardly from the top portion to a backside of the semiconductor device to define a perimeter of the cold plate. Each pair of opposing cavity sidewalls extends downwardly from the top portion towards the backside of the semiconductor device to define a coolant chamber volume therebetween. A distance between each pair of opposing cavity sidewalls in a direction parallel with the backside of the semiconductor device defines a width of a corresponding coolant chamber volume and a spacing between adjacent coolant chamber volumes, wherein the ratio of width to spacing is about 1:1.
1. A device package comprising:
an integrated cooling assembly comprising a semiconductor device and a cold plate attached to the semiconductor device, the cold plate comprises:
a perimeter sidewall;
a top portion;
a bottom portion, wherein the bottom portion of the cold plate is attached to the semiconductor device by direct dielectric bonds; and
a plurality of pairs of opposing cavity sidewalls, wherein:
the perimeter sidewall extends downwardly from the top portion to a backside of the semiconductor device to define a perimeter of the cold plate;
a first pair of opposing cavity sidewalls extends downwardly from the top portion towards the backside of the semiconductor device to define a first coolant channel therebetween;
a device-facing side of the first coolant channel is open to the backside of the semiconductor device;
the first coolant channel has a substantially triangular cross-section defined by the first pair of opposing cavity sidewalls and the device-facing side of the first coolant channel;
the first pair of opposing cavity sidewalls are joined together to define a first vertex of the substantially triangular cross-section, the first vertex being spaced from the backside of the semiconductor device,
the substantially triangular cross-section has a pair of device-adjacent vertices at the backside of the semiconductor device, the pair of device-adjacent vertices comprise a first device-adjacent vertex and a second device-adjacent vertex;
a distance between the first device-adjacent vertex and the second device-adjacent vertex along the backside of the semiconductor device defines a width W of the first coolant channel;
the pair of device-adjacent vertices of the first coolant channel are separated from an additional pair of device-adjacent vertices of an adjacent coolant channel by a spacing S; and
a ratio of W to S is substantially 1:1.
2. The device package of claim 1 , wherein the ratio of W to S is between substantially 1:1.05 and 1:1.2.
3. The device package of claim 1 , wherein each pair of opposing cavity sidewalls extend downwardly from the top portion to a depth of substantially 0.5 mm.
4. The device package of claim 1 , wherein dividers are defined between adjacent coolant channels.
5. The device package of claim 1 , wherein a portion of the cold plate is disposed above a hotspot region of the semiconductor device.
6. The device package of claim 5 , wherein the portion of the cold plate disposed above the hotspot region of the semiconductor device is between adjacent coolant channels.
7. The device package of claim 5 , wherein each pair of opposing cavity sidewalls are spaced apart in a direction parallel with the backside of the semiconductor device such that the portion of the cold plate disposed above the hotspot region is spaced evenly between adjacent coolant channels.
8. The device package of claim 1 , wherein the cold plate comprises an inlet opening and an outlet opening disposed in the top portion, wherein the inlet opening and the outlet opening are in fluid communication with the first coolant channel.
9. The device package of claim 8 , wherein each pair of opposing cavity sidewalls extends laterally and in parallel between the inlet opening and the outlet opening of the cold plate.
10. The device package of claim 1 , further comprising:
a package substrate upon which the integrated cooling assembly is disposed;
a package cover extending over the integrated cooling assembly so that the integrated cooling assembly is disposed between the package substrate and the package cover, wherein:
the package cover comprises an inlet opening and an outlet opening disposed therethrough; and
one or more coolant channels are in fluid communication with the inlet opening and the outlet opening.
11. The device package of claim 10 , wherein the device package further comprises a sealing material layer that surrounds an interface between the semiconductor device and the package substrate.
12. The device package of claim 1 , wherein the integrated cooling assembly comprises a plurality of semiconductor devices and the cold plate is attached to the plurality of semiconductor devices.
13. The device package of claim 1 , wherein the perimeter sidewall is formed integrally with the top portion.
14. The device package of claim 1 , wherein the plurality of pairs of opposing cavity sidewalls are formed integrally with the top portion.
15. A device package comprising:
an integrated cooling assembly comprising a semiconductor device and a cold plate attached to the semiconductor device, the cold plate comprises:
a perimeter sidewall;
a top portion;
a bottom portion, wherein the bottom portion of the cold plate is attached to the semiconductor device by direct hybrid bonds; and
a plurality of pairs of opposing cavity sidewalls, wherein:
the perimeter sidewall extends downwardly from the top portion to a backside of the semiconductor device to define a perimeter of the cold plate;
a first pair of opposing cavity sidewalls extends downwardly from the top portion towards the backside of the semiconductor device to define a first coolant channel therebetween;
a device-facing side of the first coolant channel is open to the backside of the semiconductor device;
the first coolant channel has a substantially triangular cross-section defined by the first pair of opposing cavity sidewalls and the device-facing side of the first coolant channel;
the first pair of opposing cavity sidewalls are joined together to define a first vertex of the substantially triangular cross-section, the first vertex being spaced from the backside of the semiconductor device,
the substantially triangular cross-section has a pair of device-adjacent vertices at the backside of the semiconductor device, the pair of device-adjacent vertices comprise a first device-adjacent vertex and a second device-adjacent vertex;
a distance between the first device-adjacent vertex and the second device-adjacent vertex along the backside of the semiconductor device defines a width W of the first coolant channel;
the pair of device-adjacent vertices of the first coolant channel are separated from an additional pair of device-adjacent vertices of an adjacent coolant channel by a spacing S; and
a ratio of W to S is substantially 1:1.
16. The device package of claim 15 , wherein the ratio of W to S is between substantially 1:1.05 and 1:1.2.
17. The device package of claim 15 , wherein a portion of the cold plate is disposed above a hotspot region of the semiconductor device.
18. The device package of claim 17 , wherein the portion of the cold plate disposed above the hotspot region of the semiconductor device is between adjacent coolant channels.
19. The device package of claim 17 , wherein each pair of opposing cavity sidewalls are spaced apart in a direction parallel with the backside of the semiconductor device such that the portion of the cold plate disposed above the hotspot region is spaced evenly between adjacent coolant channels.
20. The device package of claim 15 , wherein the integrated cooling assembly comprises a plurality of semiconductor devices and the cold plate is attached to the plurality of semiconductor devices.