IP Library › Granted Patent US 12,513,855
Granted Patent B1
US 12,513,855 · App. 19/073,556 · Granted Dec 30, 2025

Integrated cooling assembly with upper and lower channels

Inventors: Belgacem Haba (Saratoga, CA); Gaius Gillman Fountain, Jr. (Youngsville, NC)
Assignee: Adeia Semiconductor Bonding Technologies Inc.
H05K7/20254H05K1/0203H05K3/305
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Quick Facts
Patent No.
US 12,513,855
App. No.
19/073,556
Granted
Dec 30, 2025
Kind
B1
Abstract

Embodiments herein provide for fluidic cooling assemblies embedded within a device package and related manufacturing methods. In one embodiment, an integrated cooling assembly includes a semiconductor device and a cold plate attached to a backside of the semiconductor device. The cold plate includes an upper portion disposed vertically adjacent to the backside of the semiconductor device and a lower portion disposed between the upper portion of the cold plate and the backside of the semiconductor device. The upper portion includes upper coolant channels defined by upper cavity sidewalls. The lower portion includes lower coolant channels defined by lower cavity sidewalls. The upper cavity sidewalls extend downwardly into regions between adjacent lower coolant channels. The lower cavity sidewalls extend upwardly into regions between adjacent upper coolant channels.

Claims (44)

1 . An integrated cooling assembly comprising:

a semiconductor device;

a cold plate attached to a backside of the semiconductor device, the cold plate comprising:

an upper portion disposed vertically adjacent to the backside of the semiconductor device; and

a lower portion disposed between the upper portion of the cold plate and the backside of the semiconductor device, wherein:

the upper portion comprises upper coolant channels defined by upper cavity sidewalls;

the lower portion comprises lower coolant channels defined by lower cavity sidewalls;

the upper cavity sidewalls extend downwardly into regions between adjacent lower coolant channels; and

the lower cavity sidewalls extend upwardly into regions between adjacent upper coolant channels.

2 . The integrated cooling assembly of claim 1 , wherein the upper coolant channels are separated from the lower coolant channels by the upper cavity sidewalls and the lower cavity sidewalls.

3 . The integrated cooling assembly of claim 1 , wherein the cold plate comprises:

a lower side facing the backside of the semiconductor device and an upper side opposite the lower side, wherein:

the lower cavity sidewalls extend upwardly into the lower portion from the lower side of the cold plate to form the lower coolant channels; and

the upper cavity sidewalls extend downwardly into the upper portion from the upper side of the cold plate to form the upper coolant channels.

4 . The integrated cooling assembly of claim 1 , wherein the cold plate comprises a channel cover disposed on the upper portion of the cold plate to fluidly seal the upper coolant channels.

5 . The integrated cooling assembly of claim 4 , wherein the channel cover is attached to the upper portion by direct dielectric bonds, direct hybrid bonds, or adhesive.

6 . The integrated cooling assembly of claim 1 , wherein the upper coolant channels are horizontally offset from the lower coolant channels.

7 . The integrated cooling assembly of claim 1 , wherein:

the upper cavity sidewalls are sloped to form upper coolant channels with a triangular cross-section; and

the lower cavity sidewalls are sloped to form lower coolant channels with a triangular cross-section.

8 . The integrated cooling assembly of claim 1 wherein a width of the cold plate in a direction parallel with the backside of the semiconductor device is greater than a width of the semiconductor device in the same direction.

9 . The integrated cooling assembly of claim 1 , wherein the cold plate is attached to the semiconductor device by direct dielectric bonds or direct hybrid bonds.

10 . The integrated cooling assembly of claim 1 , wherein:

the integrated cooling assembly comprises a plurality of semiconductor devices each comprising a backside; and

the cold plate is attached to the backside of each semiconductor device.

11 . The integrated cooling assembly of claim 10 , wherein at least one upper coolant channel is fluidly connected to at least one lower coolant channel.

12 . The integrated cooling assembly of claim 10 , wherein the upper coolant channels are horizontally aligned with the lower coolant channels.

13 . The integrated cooling assembly of claim 1 , wherein:

the cold plate further comprises inlet and outlet openings; and

the upper coolant channels and the lower coolant channels are in fluid communication with the inlet and outlet openings.

14 . The integrated cooling assembly of claim 13 , wherein a length of the upper coolant channels between the inlet and outlet openings is less than a length of the lower coolant channels between the inlet and outlet openings.

15 . A device package comprising the integrated cooling assembly of claim 1 , the device package comprising a package substrate, wherein the integrated cooling assembly is attached to the package substrate.

16 . The device package of claim 15 , further comprising a package cover disposed over the integrated cooling assembly, wherein:

the package cover comprises an inlet opening and an outlet opening disposed therethrough; and

the upper coolant channels and the lower coolant channels are in fluid communication with the inlet opening and the outlet opening of the package cover.

17 . A method of manufacturing the integrated cooling assembly of claim 1 , the method comprising:

forming a first substrate comprising a cold plate, wherein the cold plate comprises upper cavity sidewalls defining upper coolant channels and lower cavity sidewalls defining lower coolant channels; and

directly bonding the cold plate to a second substrate comprising a semiconductor device.

18 . The method of claim 17 , further comprising:

singulating an integrated cooling assembly from the bonded first and second substrates.

19 . The method of claim 18 , further comprising:

connecting the integrated cooling assembly to a package substrate and sealing a package cover comprising inlet and outlet openings to the integrated cooling assembly.

20 . The method of claim 19 , further comprising:

before or after sealing the package cover to the integrated cooling assembly, forming inlets and outlets in a sealing material layer to fluidly connect the inlet and outlet opening of the package cover to the cold plate.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 17, 2025
From: HABA, BELGACEM; FOUNTAIN,, GAIUS GILLMAN, JR.
To: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
Reel/Frame 071432/0911 →
SECURITY INTEREST Recorded May 28, 2025
From: ADEIA INC. (F/K/A XPERI HOLDING CORPORATION); ADEIA HOLDINGS INC.; ADEIA MEDIA HOLDINGS INC.; ADEIA IMAGING LLC; ADEIA MEDIA LLC; ADEIA MEDIA SOLUTIONS INC.; ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.; ADEIA TECHNOLOGIES INC.; ADEIA GUIDES INC.; ADEIA SOLUTIONS LLC; ADEIA SEMICONDUCTOR ADVANCED TECHNOLOGIES INC.; ADEIA SEMICONDUCTOR SOLUTIONS LLC; ADEIA SEMICONDUCTOR INTELLECTUAL PROPERTY LLC; ADEIA SEMICONDUCTOR TECHNOLOGIES LLC; ADEIA PUBLISHING INC.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 071454/0343 →
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