High dose implantation for ultrathin semiconductor-on-insulator substrates
Methods and structures for forming highly-doped, ultrathin layers for transistors formed in semiconductor-on-insulator substrates are described. High dopant concentrations may be achieved in ultrathin semiconductor layers to improve device characteristics. Ion implantation at elevated temperatures may mitigate defect formation for stoichiometric dopant concentrations up to about 30%. In-plane stressors may be formed adjacent to channels of transistors formed in ultrathin semiconductor layers.
1. An integrated circuit, comprising:
a substrate;
an insulating layer over the substrate;
an ultrathin semiconductor layer on the insulating layer, the ultrathin semiconductor layer having a first surface and a second surface opposite the first surface, the ultrathin semiconductor layer including a first portion and a second portion, the first portion and the second portion both extending from the first surface to the second surface;
a first device former in and over the first portion, the first device including:
a first gate structure over the first portion
a first channel region embedded in the first portion and below the first gate structure, the first channel region including a first doping concentration of a first impurity, the first impurity is germanium, and
a first source or drain extension region embedded in the first portion and laterally adjacent to the first channel region, the first source or drain extension region including a second doping concentration of the first impurity, the second doping concentration being greater than the first doping concentration; and
a second device formed in and over the second portion, the second device including:
a second gate structure over the second portion,
a second channel region embedded in the second portion and below the second gate structure, the second channel region being substantially un-doped, and
a second source or drain extension region embedded in the second portion and laterally adjacent to the second channel region, the second source or drain extension region including a third doping concentration of a second impurity,
wherein the ultrathin semiconductor layer includes silicon.
2. The integrated circuit of claim 1 , wherein a thickness of the ultrathin semiconductor layer is less than approximately 10 nm.
3. The integrated circuit of claim 1 , wherein the second source or drain extension region applies a compressive tension toward the second channel region.
4. The integrated circuit of claim 1 , wherein the first and second devices are transistors.
5. A method, comprising:
forming an ultrathin semiconductor layer on an insulating layer over a substrate, the ultrathin semiconductor layer having a first surface and a second surface opposite the first surface, the ultrathin semiconductor layer including a first portion and a second portion, the first portion and the second portion both extending from the first surface to the second surface;
forming a first device in and over the first portion, the first device including:
a first gate structure over the first portion,
a first channel region embedded in the first portion and below the first gate structure, the first channel region including a first doping concentration of a first impurity, the first impurity is germanium, and
a first source or drain extension region embedded in the first portion and laterally adjacent to the first channel region, the first source or drain extension region including a second doping concentration of the first impurity, the second doping concentration being greater than the first doping concentration; and
forming a second device in and over the second portion, the second device including:
a second gate structure over the second portion,
a second channel region embedded in the second portion and below the second gate structure, and the second channel region being substantially un-doped,
a second source or drain extension region embedded in the second portion and laterally adjacent to the second channel region, the second source or drain extension region including a third doping concentration of a second impurity,
wherein the ultrathin semiconductor layer includes silicon.
6. The method of claim 5 , further comprising doping the first portion by implanting a first dopant of the first impurity.
7. The method of claim 6 , further comprising:
before doping the first portion, forming a thin implantation layer over the first portion; and
removing the thin implantation layer after implanting the first dopant, wherein the first dopant is implanted through the thin implantation layer.
8. The method of claim 7 , further comprising:
before forming the thin implantation layer, forming a hardmask over the second portion; and
removing the hardmask after the implanting the first dopant.
9. The method of claim 7 , wherein the thin implantation layer is an oxide layer, a thin nitride layer, a thin polymer layer, or a thin low-Z metal layer.
10. The method of claim 6 , wherein doping includes maintaining the substrate at a temperature between approximately 350° C. and approximately 500° C.
11. The method of claim 6 , wherein implanting the first dopant is carried out at an energy between approximately 0.5 keV and approximately 3 keV.
12. The method of claim 6 , wherein the first dopant is implanted at a dose between approximately 0.5×10 16 cm −2 and approximately 2×10 16 cm −2 .
13. A device, comprising:
a substrate;
an insulating layer on the substrate;
a silicon ultrathin semiconductor layer on the insulating layer, the silicon ultrathin semiconductor layer having a first surface opposite a second surface, the silicon ultrathin semiconductor layer including a first portion and a second portion, the first portion and the second portion both extending from the first surface to the second surface;
a first transistor on the first portion, the first transistor including:
a first gate structure on the first portion,
a doped channel in the first portion and opposite the first gate structure, the second channel region being substantially un-doped, and
a first doped source or drain extension region in the first portion and spaced from the doped channel, the first doped source or drain extension region have a first doping concentration greater than a second doping concentration of the doped channel; and
a second transistor on the second portion and spaced from the first transistor, the second transistor including:
a second gate structure on the second portion,
an un-doped channel in the second portion and opposite the second gate structure, and
a second doped source or drain extension region in the second portion and spaced from to the un-doped channel.
14. The device of claim 13 , wherein the doped channel and the first portion are coplanar.
15. The device of claim 13 , wherein the un-doped channel and the second portion are coplanar.
16. The device of claim 13 , wherein the doped channel has a concentration of germanium from about 15% to about 40%.