IP Library › Assignment 022973/0239
Patent Assignment
Reel/Frame 022973/0239

Assignment of Assignor's Interest

Recorded: 2009-07-18 Pages: 9
Assignor
PHILIPS SEMICONDUCTORS INC.
Executed: 2009-07-15
Assignee
NXP B.V.
HIGH TECH CAMPUS 60, 5656 AG EINDHOVEN, NETHERLANDS
Covered Properties (75)
Method of Generating Tests for a Combinational Logic Circuit
Patent: 4,996,689 →
Application: 07/305,449 →
A Circuit to Aribitrate Multiple Requests for Memory Access
Patent: 4,998,030 →
Application: 07/390,784 →
Self-Aligning Metal Interconnect Fabrication
Patent: 4,988,643 →
Application: 07/419,284 →
Non-Volatile Memory Structure
Patent: 5,097,449 →
Application: 07/494,007 →
Method and Apparatus for Marking or Erasing a Marking on a Semiconductor Chip Package
Patent: 5,110,628 →
Application: 07/494,246 →
Static Random Access Memory with Pmos Pass Gates
Patent: 5,126,970 →
Application: 07/505,730 →
Routing Independent Circuit Components
Patent: 5,088,061 →
Application: 07/557,228 →
Etching System Having Simplified Diffuser Element Removal
Patent: 5,180,467 →
Application: 07/565,621 →
Reusable Package for Holding a Semiconductor Chip and Method for Reusing the Package
Patent: 5,041,396 →
Application: 07/585,023 →
Tightly Coupled, Low Overhead Ram Built-in Self-Test Logic with Particular Applications for Embedded Memories
Patent: 5,258,986 →
Application: 07/585,334 →
System for Positioning a Semiconductor Chip Package with Respect to a Testing Device
Patent: 5,124,644 →
Application: 07/630,115 →
Water Sealing Develop Ring
Patent: 5,159,374 →
Application: 07/680,203 →
Integrated Circuit Test System
Patent: 5,146,161 →
Application: 07/681,803 →
Ion Beam Contamination Sensor
Patent: 5,146,098 →
Application: 07/681,807 →
Method and Apparatus for Controlling Simultaneous Switching Output Noise in Boundry Scan Paths
Patent: 5,229,657 →
Application: 07/694,532 →
Symbolic Routing Guidance for Wire Networks in Vlsi Circuits
Patent: 5,485,396 →
Application: 07/723,109 →
Output Pad Electrostatic Discharge Protection Circuit for Mos Devices
Patent: 5,208,719 →
Application: 07/747,545 →
Esd Protection Circuit and Method for Power-Down Application
Patent: 5,229,635 →
Application: 07/748,294 →
High Power Buffer with Increased Current Stability
Patent: 5,233,238 →
Application: 07/812,194 →
Self-Compensating Digital Delay Semiconductor Device with Selectable Output Delays and Method Therefor
Patent: 5,252,867 →
Application: 07/843,488 →
Dual Edge-Triggered Digital Storage Element and Method Therefor
Patent: 5,179,295 →
Application: 07/854,154 →
Cache Controller and Method for Dumping Contents of a Cache Directory and Cache Data Random Access Memory (Ram)
Patent: 5,537,572 →
Application: 07/860,812 →
Package Structure Having Accessible Chip
Patent: 5,491,362 →
Application: 08/106,146 →
Vapor/Liquid Phase Separator for an Open Tank Ipa-Dryer
Patent: 5,535,525 →
Application: 08/214,481 →
Densification in an Intermetal Dielectric Film
Patent: 5,610,105 →
Application: 08/258,180 →
Electrically and Thermally Enhanced Package Using a Separate Silicon Substrate
Patent: 5,598,031 →
Application: 08/328,939 →
Thermometric Digital-to-Analog Converter Occouying Reduced Chip Area
Patent: 5,600,319 →
Application: 08/333,008 →
Method of Making Microscope Probe Tips
Patent: 5,540,958 →
Application: 08/357,842 →
Noise Isolated I/O Buffer
Patent: 5,534,791 →
Application: 08/375,741 →
Integrated Circuit with Variable Pad Pitch
Patent: 5,610,417 →
Application: 08/415,183 →
High Voltage Tolerant Cmos Input/Output Circuit
Patent: 5,543,733 →
Application: 08/494,756 →
Patterned Filled Photo Mask Generation for Integrated Circuit Manufacturing
Patent: 5,597,668 →
Application: 08/504,157 →
Multi-Size Cryptographic Key System
Patent: 5,659,618 →
Application: 08/536,835 →
Thermal Management Device and Method for a Computer Processor
Patent: 5,713,030 →
Application: 08/540,714 →
Purge Apparatus for Integrated Circuit Test System
Patent: 5,636,924 →
Application: 08/542,089 →
Technique for Improving Bonding Strength of Leadframe to Substrate in Semiconductor Ic Chip Packages
Patent: 5,661,337 →
Application: 08/553,214 →
Wafer Edge Sealing
Patent: 5,618,380 →
Application: 08/574,069 →
Electrically Enhanced Power Quad Flat Pack Arrangement
Patent: 5,646,831 →
Application: 08/581,294 →
N-Well Resistor as a Ballast Resistor for Output Mosfet
Patent: 5,637,902 →
Application: 08/586,041 →
Multi-Layered, Integrated Circuit Package Having Reduced Parasitic Noise Characteristics
Patent: 5,625,225 →
Application: 08/589,751 →
Method for Optimizing Performance Versus Power Consumption Using External/Internal Clock Frequency Ratios
Patent: 5,754,867 →
Application: 08/619,924 →
Event Driven Power Management Control Circuit and Method Therefor
Patent: 5,715,467 →
Application: 08/627,461 →
Integrated Circuit Test Apparatus
Patent: 5,751,151 →
Application: 08/630,685 →
System and Method for Altering the Clock Frequency to a Logic Controller Controlling a Logic Device Running at a Fixed Frequency Slower Than a Computer System Running the Logic Device
Patent: 5,768,571 →
Application: 08/705,356 →
Method and System for Vacuum Removal of Chemical Mechanical Polishing By-Products
Patent: 6,190,236 →
Application: 08/732,165 →
Methods of Analyzing a Radio Signal and Methods of Analyzing a Personal Handy-Phone System Radio Signal
Patent: 6,115,367 →
Application: 08/906,341 →
Methods of Synchronization, Personal Handy-Phone System Stations and Phase Lock Loops
Patent: 6,016,331 →
Application: 08/906,531 →
Method and System for Pseudo Delayed Transactions Through a Bridge to Guarantee Access to a Shared Resource
Patent: 6,178,477 →
Application: 08/947,650 →
Method for Preventing Electrochemical Erosion of Interconnect Structures
Patent: 6,153,531 →
Application: 08/995,679 →
Binary Memory Design with Data Stored in Low Power Sense
Application: 09/006,404 →
Low Power Undervoltage Detector with Power Down Mode
Patent: 6,104,220 →
Application: 09/009,567 →
Pipelined Hardware Implementation of a Hashing Algorithm
Patent: 6,091,821 →
Application: 09/022,847 →
Process for Forming Metal Interconnects with Reduced or Eliminated Metal Recess in Vias
Patent: 6,228,757 →
Application: 09/035,735 →
Pseudo-Scan Testing Using Hardware-Accessible Ic Structures
Patent: 6,141,782 →
Application: 09/052,796 →
Arrangement and Method for Dram Cell Using Shallow Trench Isolation
Patent: 6,087,214 →
Application: 09/069,429 →
Centrally Controlled Interface Scheme for Promoting Design Reusable Circuit Blocks
Patent: 6,052,754 →
Application: 09/079,989 →
Semiconductor Calibration Structures and Calibration Wafers for Ascertaining Layer Alignment During Processing and Calibrating Multiple Semiconductor Wafer Coating Systems
Patent: 6,094,965 →
Application: 09/087,764 →
Method for Forming Vias Through Porous Dielectric Material and Devices Formed Thereby
Patent: 6,140,221 →
Application: 09/124,603 →
Polysilicon Pillar Heat Sinks for Semiconductor on Insulator Circuits
Patent: 6,080,608 →
Application: 09/130,423 →
Hdl Simulation Interface for Testing and Verifying an Asic Model
Patent: 6,199,031 →
Application: 09/144,680 →
Process to Control Poly Silicon Profiles in a Dual Doped Poly Silicon Process
Patent: 6,399,432 →
Application: 09/199,203 →
Electromigration Bonding Process and System
Patent: 6,156,626 →
Application: 09/259,744 →
Method and Apparatus for Improved Copper Plating Uniformity on a Semiconductor Wafer Using Optimized Electrical Currents
Patent: 6,193,860 →
Application: 09/298,629 →
Method and Arrangement for Gyration Filtering with Low Power Consumption
Patent: 6,317,016 →
Application: 09/312,132 →
High Differential Impedance Load Device
Patent: 6,154,018 →
Application: 09/388,034 →
Programmable Integrated Ciruit Structures and Methods for Making the Same
Patent: 6,355,969 →
Application: 09/405,043 →
Built-In Self Test for Integrated Digital-to-Analog Converters
Patent: 6,320,528 →
Application: 09/419,465 →
Methods of Synchronizing a Personal Handy-Phone System Station and Phase Lock Loops
Patent: 6,198,784 →
Application: 09/422,029 →
Predictive Mechanism for Asb Slave Responses
Patent: 6,578,098 →
Application: 09/435,133 →
Trench-Diffusion Corner Rounding in a Shallow -Trench (Sti) Process
Patent: 6,150,234 →
Application: 09/465,151 →
Pad Metallization Over Active Circuitry
Patent: 6,261,939 →
Application: 09/472,384 →
Arrangement for Dram Cell Using Shallow Trench Isolation
Patent: 6,177,697 →
Application: 09/487,008 →
Semiconductor Device with Anti-Reflective Structure and Methods of Manufacture
Patent: 6,410,421 →
Application: 09/560,939 →
Reset Circuit and Method Therefor
Patent: 6,529,053 →
Application: 09/826,570 →
Publication: US 2002/0145454
Reconfigurable Digital Filter Having Multiple Filtering Modes
Patent: 6,963,890 →
Application: 09/871,198 →
Publication: US 2002/0184275
Related Assignments (10)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Feb 17, 2009
From: NXP B.V.
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 022266/0047 →
Change of Name Jul 18, 2009
From: PHILIPS SEMICONDUCTORS VLSI INC.
To: PHILIPS SEMICONDUCTORS INC.
Reel/Frame 022973/0254 →
Change of Name Jul 18, 2009
From: VLSI TECHNOLOGY, INC.
To: PHILIPS SEMICONDUCTORS VLSI INC.
Reel/Frame 022973/0248 →
Assignment of Assignor's Interest Feb 5, 2010
From: NXP B.V.
To: LSI CORPORATION
Reel/Frame 023905/0095 →
Corrective Assignment to Correct the Omission of Conveying Parties Who Executed the Assignment Previously Recorded on Reel 007223 Frame 0611. Assignor(S) Hereby Confirms the Addition of Conveying Parties: Sigmund a. Koenigseder, Landon B. Vines, Chang-Ou Lee, and Felix Fujishiro. Nov 1, 2011
From: CAIN, JOHN L.; KOENIGSEDER, SIGMUND A.; VINES, LANDON B.; LEE, CHANG-OU
To: VLSI TECHNOLOGY, INC.
Reel/Frame 027158/0275 →
Assignment of Assignor's Interest Nov 22, 2011
From: NXP B.V.
To: CALLAHAN CELLULAR L.L.C.
Reel/Frame 027265/0798 →
Assignment of Assignor's Interest Jan 10, 2012
From: NXP SEMICONDUCTORS N.V. ON BEHALF OF ITSELF AND ITS SUBSIDIARIES, INCLUDING NXP B.V.
To: INVENSAS CORPORATION
Reel/Frame 027545/0060 →
Assignment of Assignor's Interest Mar 13, 2012
From: HAMZEHDOOST, AHMAD; MORA, LEONARD L.
To: VLSI TECHNOLOGY, INC.
Reel/Frame 027855/0467 →
Confirmatory Assignment Mar 26, 2012
From: PHILIPS SEMICONDUCTORS INC.
To: NXP B.V.
Reel/Frame 027931/0442 →
Assignment of Assignor's Interest Apr 16, 2012
From: NXP B.V.
To: SEONG CAPITAL LTD. LIMITED LIABILITY COMPANY
Reel/Frame 028049/0649 →