Integrated cooling assemblies for advanced device packaging and methods of manufacturing the same
A device package comprising an integrated cooling assembly. The integrated cooling assembly comprises a semiconductor device and a cold plate attached to the semiconductor device. The cold plate comprises a top portion and a bottom portion horizontally adjacent to the top portion. The top portion comprises upper cavity dividers extending downwardly to define upper cavity volumes. The bottom portion comprises lower cavity dividers extending upwardly to define lower cavity volumes. The upper cavity dividers and the lower cavity dividers alternate across a horizontal length of the cold plate.
1. A device package comprising:
an integrated cooling assembly comprising a semiconductor device and a cold plate directly bonded to the semiconductor device by direct dielectric bonds, wherein:
the cold plate comprises a top portion and a bottom portion vertically adjacent to the top portion;
the top portion comprises upper cavity dividers extending downwardly to define upper cavity volumes;
the bottom portion comprises lower cavity dividers extending upwardly to define lower cavity volumes; and
the upper cavity dividers and the lower cavity dividers alternate across a horizontal length of the cold plate.
2. The device package of claim 1 , wherein the upper cavity dividers and the lower cavity dividers are disposed across the horizontal length of the cold plate with a lateral spacing between adjacent upper and lower cavity dividers.
3. The device package of claim 1 , wherein:
the upper cavity dividers are spaced horizontally across the top portion at a first lateral spacing and the lower cavity dividers are spaced horizontally across the bottom portion at a second lateral spacing different to the first lateral spacing; and
the lateral spacings between the cavity dividers are greater than a horizontal width of the cavity dividers.
4. The device package of claim 1 , wherein:
the top portion comprises an upper surface attached to an upper sidewall, the upper sidewall extending downwardly from the upper surface.
5. The device package of claim 4 , wherein the upper cavity dividers extend downwardly from the upper surface to substantially a same depth as a depth of the upper sidewall.
6. The device package of claim 4 , wherein the upper cavity dividers extend between opposite sides of the upper sidewall to define the upper cavity volumes.
7. The device package of claim 1 , wherein:
the bottom portion comprises a lower surface attached to a lower sidewall, the lower sidewall extending upwardly from the lower surface; and
the lower surface is attached to a backside of the semiconductor device.
8. The device package of claim 7 , wherein the lower cavity dividers extend upwardly from the lower surface to substantially a same depth as a depth of the lower sidewall.
9. The device package of claim 7 , wherein the lower cavity dividers extend between opposite sides of the lower sidewall to define the lower cavity volumes.
10. The device package of claim 1 , wherein:
the bottom portion comprises a lower sidewall extending upwardly from a backside of the semiconductor device; and
the lower cavity dividers are disposed on the backside of the semiconductor device.
11. The device package of claim 10 , wherein the lower cavity dividers extend upwardly from the backside of the semiconductor device to substantially a same depth as a depth of the lower sidewall.
12. The device package of claim 1 , wherein:
the top portion comprises an upper cavity separator attached between a pair of upper cavity dividers to define compartments within the upper cavity volumes, and
the bottom portion comprises a lower cavity separator attached between a pair of lower cavity dividers to define compartments within the lower cavity volumes.
13. The device package of claim 1 , wherein surfaces of the upper cavity dividers slope towards the bottom portion at an angle greater than 90 degrees.
14. The device package of claim 1 , wherein:
surfaces of the lower cavity dividers slope towards the top portion at an angle greater than 90 degrees; or
surfaces of the lower cavity dividers slope towards the top portion at an angle less than 90 degrees.
15. The device package of claim 1 , wherein the upper cavity dividers are rows of first metal posts and the lower cavity dividers are rows of second metal posts.
16. The device package of claim 1 , wherein the top portion of the cold plate comprises:
a package cover, the package cover having an inlet opening and an outlet opening disposed therethrough, and wherein:
the upper cavity volumes and the lower cavity volumes collectively define a coolant chamber volume therebetween; and
the coolant chamber volume is in fluid communication with the inlet opening and the outlet opening.
17. The device package of claim 1 , wherein:
the upper cavity dividers define two longitudinal upper cavity volumes;
the lower cavity dividers define three longitudinal lower cavity volumes orthogonal to the longitudinal upper cavity volumes;
a first lower cavity volume overlaps with a first upper cavity volume only;
a second lower cavity volume overlaps with a second upper cavity volume only; and
a third lower cavity volume overlaps with both the first and the second upper cavity volumes.
18. A method of manufacturing the device package of claim 1 , the method comprising:
directly bond a first substrate comprising the upper cavity dividers defining the upper cavity volumes to a second substrate comprising the lower cavity dividers defining the lower cavity volumes, the bonded first and second substrates forming the cold plate with horizontally alternating upper and lower cavity dividers, wherein the upper and lower cavity dividers are etched into the first and second substrates with an anisotropic etch process; and
directly bond the cold plate to a third substrate comprising the semiconductor device.
19. The method of claim 18 , further comprising:
sealingly attach a package cover to the integrated cooling assembly by use of a material layer disposed therebetween, the package cover comprising an inlet opening and an outlet opening; and
before or after attaching the package cover to the cold plate, form openings in the material layer to fluidly connect the inlet opening and the outlet opening to the lower cavity volumes and the upper cavity volumes.
20. The method of claim 18 , wherein the cold plate is attached to the semiconductor device by direct hybrid bonds.
21. The device package of claim 1 , wherein the cold plate is attached to the semiconductor device by direct hybrid bonds.
22. The device package of claim 1 , wherein:
the upper cavity volumes and the lower cavity volumes collectively define a coolant chamber volume therebetween; and
the device package further comprises upper and lower cavity separators to define a plurality of channels through the coolant chamber volume.
23. A device package comprising:
an integrated cooling assembly comprising a semiconductor device and a cold plate directly bonded to the semiconductor device by direct dielectric bonds, wherein:
the cold plate is spaced apart from the semiconductor device to collectively define a coolant chamber volume therebetween;
the cold plate comprises a top portion having upper cavity dividers extending downwardly to define upper cavity volumes;
a backside of the semiconductor device comprises lower cavity dividers extending upwardly to define lower cavity volumes; and
the upper cavity dividers and the lower cavity dividers alternate across a horizontal length of the cold plate.
24. The device package of claim 23 , wherein:
the device package further comprises upper and lower cavity separators to define a plurality of channels through the coolant chamber volume.