Granted Patent B2

US 12,218,249 · App. 18/227,361 · Granted Feb 4, 2025

Inventor: Shunpei Yamazaki (Setagaya, JP)

Assignee: Semiconductor Energy Laboratory Co., Ltd.

H01L29/7869H01L27/1225H01L29/04H01L29/045H01L29/24H01L29/66969H01L29/78648H01L29/78693H01L29/78696

Abstract

Claims (11)

1. A semiconductor device comprising:

a first conductive layer;

a first insulating layer over the first conductive layer;

an oxide semiconductor layer including a channel formation region of a transistor, over the first insulating layer; and

a second conductive layer in contact with a top surface of the oxide semiconductor layer,

wherein the first conductive layer is configured to be a gate electrode of the transistor,

wherein the second conductive layer is configured to be a source electrode or a drain electrode of the transistor,

wherein the oxide semiconductor layer includes a first region overlapping the first conductive layer, a second region overlapping the first conductive layer and the second conductive layer, and a third region overlapping the second conductive layer,

wherein the first region includes a crystal grain whose c-axis is aligned, and

wherein the second region is closer to the first conductive layer than the first region.

2. The semiconductor device according to claim 1 , further comprising a third conductive layer over the oxide semiconductor layer and the second conductive layer.

Priority Claims (1)

Continuity (10)

References Cited (351)