Patent Assignment
Reel/Frame 021985/0001
Assignment of Assignor's Interest
Recorded: 2008-12-16
Received: 2008-12-16
Pages: 9
Assignor
NMS COMMUNICATIONS CORPORATION
Executed: 2008-12-02
Assignee
DIALOGIC CORPORATION
9800 CAVENDISH BLVD., 5TH FLOOR, MONTREAL, QUEBEC, CAX, H4M 2V9, CANADA
Covered Properties
(100)
Solar Powered Lantern Charging Case
Application:
29/321,188 →
Solar Powered Lantern Charging Case with Battery
Application:
29/321,058 →
Image Recognition Device and Image Rotating Method
Application:
12/050,513 →
Ieee 1394 Transmitter, Ieee 1394 Receiver and Audio Data Content Transmission Method
Application:
12/046,684 →
Non-Saturating Fairness Protocol and Method for Nacking Systems
Application:
12/039,048 →
Dynamic Video Messaging
Application:
11/870,580 →
System, Method, and Computer Program Product for Remote Graphics Processing
Application:
11/892,627 →
Debugging System, Debugging Circuit and Information Processing Apparatus
Application:
11/878,780 →
Program Control Device and Program Control Method
Application:
11/822,730 →
Avoiding Livelock Using Intervention Messages in Multiple Core Processors
Application:
11/767,261 →
Avoiding Livelock Using a Cache Manager in Multiple Core Processors
Application:
11/767,247 →
Preventing Writeback Race in Multiple Core Processors
Application:
11/767,225 →
Reduced Handling of Writeback Data
Application:
11/767,239 →
Led Lens
Application:
29/288,646 →
Full Scan Solution for Latched-Based Design
Application:
11/764,137 →
Processor Having a Compare Extension of an Instruction Set Architecture
Application:
11/806,845 →
System Debug and Trace System and Method, and Applications Thereof
Application:
11/747,666 →
Clustered Filesystem with Membership Version Support
Application:
11/785,255 →
An Instruction Processor Having Multiple Execution Pipelines
Application:
11/727,640 →
Direct Memory Access Engine for Data Transfers
Application:
11/685,750 →
System and Method for Managing the Design and Configuration of an Integrated Circuit Semiconductor Design
Application:
11/684,156 →
Protecting Trade Secrets During the Design and Configuration of an Integrated Circuit Semiconductor Design
Application:
11/684,205 →
Remote Interface for Managing the Design and Configuration of an Integrated Circuit Semiconductor Design
Application:
11/684,189 →
Pll Frequency Synthesizer
Application:
11/714,139 →
Horizontally-Shared Cache Victims in Multiple Core Processors
Application:
11/681,610 →
High Intensity Outdoor Light Fixture
Application:
29/273,090 →
Solar Powered Outdoor Light Fixture
Application:
29/273,096 →
Solar Powered Bug Eliminator
Application:
29/273,088 →
Solar Powered Outdoor Light Fixture
Application:
29/273,101 →
High Intensity Outdoor Light Fixture
Application:
29/273,091 →
Solar Powered Bug Eliminator
Application:
29/273,099 →
Solar Powered Bug Eliminator
Application:
29/273,089 →
Load Balancing for Parallel Tasks
Application:
11/677,460 →
Method and Apparatus for Implementing Atomicity of Memory Operations in Dynamic Multi-Streaming Processors
Application:
11/676,541 →
Trace Control from Hardware and Software
Application:
11/676,242 →
Configurable Co-Processor Interface
Application:
11/674,924 →
Smooth morphing between personal video calling avatars
Application:
11/704,745 →
Alignment and Ordering of Vector Elements for Single Instruction Multiple Data Processing
Application:
11/702,659 →
System, Method and Software Application for the Generation of Verification Programs
Application:
11/670,876 →
Method and Apparatus for Binding Shadow Registers to Vectored Interrupts
Application:
11/668,582 →
Systems and Methods for Controlling the Use of Processing Algorithms, and Applications Thereof
Application:
11/627,899 →
Synthesized assertions in a self-correcting processor and applications thereof
Application:
11/655,267 →
System and Method of Synchronizing Real Time Clock Values in Arbitrary Distributed Systems
Application:
11/620,215 →
Multithreading Instruction Scheduler Employing Thread Group Priorities
Application:
11/620,362 →
Speculative Cache Tag Evaluation
Application:
11/616,558 →
Efficient Resource Arbitration
Application:
11/616,539 →
Symmetric Multiprocessor Operating System for Execution on Non-Independent Lightweight Thread Contexts
Application:
11/615,960 →
Symmetric Multiprocessor Operating System for Execution on Non-Independent Lightweight Thread Contexts
Application:
11/615,963 →
Symmetric Multiprocessor Operating System for Execution on Non-Independent Lightweight Thread Contexts
Application:
11/615,964 →
Symmetric Multiprocessor Operating System for Execution on Non-Independent Lightweight Thread Contexts
Application:
11/615,965 →
Virtual Instruction Expansion Using Parameter Selector Defining Logical Operation on Parameters for Template Opcode Substitution
Application:
11/644,001 →
Conditional Move Instruction Formed into One Decoded Instruction to Be Graduated and Another Decoded Instruction to Be Invalidated
Application:
11/640,491 →
Barrel-Incrementer-Based Round-Robin Apparatus and Instruction Dispatch Scheduler Employing Same for Use in Multithreading Microprocessor
Application:
11/611,064 →
Selection of Isa Decoding Mode for Plural Instruction Sets Based Upon Instruction Address
Application:
11/636,462 →
Apparatus and Method to Trace High Performance Multi-Issue Processors
Application:
11/608,725 →
Instruction Encoding for System Register Bit Set and Clear
Application:
11/567,290 →
Context Selection and Activation Mechanism for Activating One of a Group of Inactive Contexts in a Processor Core for Servicing Interrupts
Application:
11/566,870 →
External Trace Synchronization via Periodic Sampling
Application:
11/557,005 →
Apparatus and Method for Forming a Bus Transaction Trace Stream with Simplified Bus Transaction Descriptors
Application:
11/555,122 →
Method and Apparatus for Overflowing Data Packets to a Software-Controlled Memory When They Do Not Fit into a Hardware-Controlled Memory
Application:
11/552,764 →
Context Switching Processor with Multiple Context Control Register Sets Including Write Address Register Identifying Destination Register for Waiting Context to Store Returned Data from External Source
Application:
11/552,640 →
Microprocessor with Improved Data Stream Prefetching
Application:
11/549,418 →
Microprocessor with Improved Data Stream Prefetching
Application:
11/549,413 →
Horizontally-Shared Cache Victims in Multiple Core Processors
Application:
60/829,099 →
Reconfigurable Circuit
Application:
11/545,477 →
Data Cache Virtual Hint Way Prediction, and Applications Thereof
Application:
11/545,706 →
Fetch and Dispatch Disassociation Apparatus for Multi-Streaming Processors
Application:
11/539,322 →
Data cache virtual hint way prediction, and applications thereof
Application:
60/848,047 →
Detection and prevention of write-after-write hazards, and applications thereof
Application:
11/529,710 →
Apparatus and Method for Tracing Processor State from Multiple Clock Domains
Application:
11/537,584 →
Apparatus and Method for Tracing Instructions with Simplified Instruction State Descriptors
Application:
11/537,574 →
Load/Store Unit for a Processor, and Applications Thereof
Application:
11/529,728 →
Twice issued conditional move instruction, and applications thereof
Application:
60/853,314 →
Transaction Selector Employing Barrel-Incrementer-Based Round-Robin Apparatus Supporting Dynamic Priorities in Multi-Port Switch
Application:
11/532,520 →
Transaction Selector Employing Round-Robin Apparatus Supporting Dynamic Priorities in Multi-Port Switch
Application:
11/532,521 →
Bifurcated Transaction Selector Supporting Dynamic Priorities in Multi-Port Switch
Application:
11/532,522 →
Extended Instruction Set for Packet Processing Applications
Application:
11/530,945 →
Software Programmable Hardware State Machines
Application:
11/517,569 →
System for Synchronizing an in-Order Co-Processor with an Out-of-Order Processor Using a Co-Processor Interface Store Data Queue
Application:
11/515,720 →
Coprocessor Load Data Queue for Interfacing an Out-of-Order Execution Unit with an in-Order Coprocessor
Application:
11/515,723 →
Micro Tag Array Having Way Selection Bits for Reducing Data Cache Access Power
Application:
11/505,865 →
Methods for Reducing Data Cache Access Power in a Processor Using Way Selection Bits
Application:
11/505,869 →
Microprocessor with Improved Data Stream Prefetching
Application:
11/463,954 →
Microprocessor with Improved Data Stream Prefetching
Application:
11/463,957 →
Microprocessor with Improved Data Stream Prefetching
Application:
11/463,950 →
Microprocessor with Improved Data Stream Prefetching
Application:
11/463,939 →
Latest producer tracking in an out-of-order processor, and applications thereof
Application:
11/485,960 →
Method for Latest Producer Tracking in an Out-of-Order Processor, and Applications Thereof
Application:
11/485,959 →
Dynamic Selection of a Compression Algorithm for Trace Data
Application:
11/445,518 →
Apparatus and Method for Processing Template Based User Defined Instructions
Application:
11/442,696 →
Apparatus and Method for Discrete Test Access Control of Multiple Cores
Application:
11/442,695 →
Configurable Co-Processor Interface
Application:
11/380,925 →
Functional Validation of a Packet Management Unit
Application:
11/380,924 →
Apparatus and Method of Controlling Data Sharing on a Shared Memory Computer System
Application:
11/413,620 →
Extended Precision Accumulator
Application:
11/410,146 →
Method and Apparatus for Binding Shadow Registers to Vectored Interrupts
Application:
11/279,914 →
System and Method for Extracting Fields from Packets Having Fields Spread Over More Than One Register
Application:
11/279,136 →
Method and Apparatus for Non-Speculative Pre-Fetch Operation in Data Packet Processing
Application:
11/278,890 →
Methods and Apparatus for Improving Fetching and Dispatch of Instructions in Multithreaded Processors
Application:
11/278,874 →
Method for Allocating Memory Space for Limited Packet Head and/or Tail Growth
Application:
11/278,901 →