IP Library › Granted Patent US 12,211,534
Granted Patent B2
US 12,211,534 · App. 18/236,000 · Granted Jan 28, 2025

Semiconductor device

Inventors: Shunpei Yamazaki (Tokyo, JP); Jun Koyama (Kanagawa, JP); Kiyoshi Kato (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L27/1207G11C11/405G11C16/0433H01L27/11803H01L27/1225H01L27/124H01L27/1255H01L29/16H01L29/24H01L29/247H01L29/7869H01L29/78693H01L29/78696H10B41/20H10B41/70H10B69/00G11C2211/4016H01L21/8221H01L27/0688H01L29/7833H10B12/00
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Quick Facts
Patent No.
US 12,211,534
App. No.
18/236,000
Granted
Jan 28, 2025
Kind
B2
Abstract

An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

Claims (110)

1. A memory cell comprising:

a first transistor, a second transistor and a third transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor,

wherein one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the third transistor,

wherein a channel formation region of the first transistor includes an oxide semiconductor layer,

wherein the oxide semiconductor layer includes a crystal whose c-axis is arranged perpendicular to a surface of the oxide semiconductor layer, and

wherein an off-state current of the first transistor is 1×10 −13 A or less.

2. The memory cell according to claim 1 , wherein the off-state current of the first transistor is 1×10 −13 A or less when a drain voltage is +1 V or +10 V and a gate voltage is in the range of −5 V to −20 V.

3. The memory cell according to claim 1 , wherein the oxide semiconductor layer is In—Ga—Zn—O-based oxide semiconductor, In—Sn—Zn—O-based oxide semiconductor, In—Al—Zn—O-based oxide semiconductor, Sn—Ga—Zn—O-based oxide semiconductor, Al—Ga—Zn—O-based oxide semiconductor, Sn—Al—Zn—O-based oxide semiconductor, In—Zn—O-based oxide semiconductor, Sn—Zn—O-based oxide semiconductor, Al—Zn—O-based oxide semiconductor, In—O-based oxide semiconductor, Sn—O-based oxide semiconductor, or Zn—O-based oxide semiconductor.

4. The memory cell according to claim 1 , wherein a hydrogen concentration measured by secondary ion mass spectrometry in the oxide semiconductor layer is 5×10 19 atoms/cm 3 or lower.

5. The memory cell according to claim 1 , wherein a channel formation region of the second transistor includes silicon.

6. A memory cell comprising:

a first transistor, a second transistor and a third transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor,

wherein one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the third transistor,

wherein a channel formation region of the first transistor includes an oxide semiconductor layer, and

wherein the oxide semiconductor layer includes a crystal whose c-axis is arranged perpendicular to a surface of the oxide semiconductor layer.

7. The memory cell according to claim 6 , wherein the oxide semiconductor layer is In—Ga—Zn—O-based oxide semiconductor, In—Sn—Zn—O-based oxide semiconductor, In—Al—Zn—O-based oxide semiconductor, Sn—Ga—Zn—O-based oxide semiconductor, Al—Ga—Zn—O-based oxide semiconductor, Sn—Al—Zn—O-based oxide semiconductor, In—Zn—O-based oxide semiconductor, Sn—Zn—O-based oxide semiconductor, Al—Zn—O-based oxide semiconductor, In—O-based oxide semiconductor, Sn—O-based oxide semiconductor, or Zn—O-based oxide semiconductor.

8. The memory cell according to claim 6 , wherein a hydrogen concentration measured by secondary ion mass spectrometry in the oxide semiconductor layer is 5×10 19 atoms/cm 3 or lower.

9. The memory cell according to claim 6 , wherein a channel formation region of the second transistor includes silicon.

10. A memory cell comprising:

a first transistor, a second transistor and a third transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor,

wherein one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the third transistor,

wherein a channel formation region of the first transistor includes an oxide semiconductor layer,

wherein the oxide semiconductor layer includes a crystal whose c-axis is arranged perpendicular to a surface of the oxide semiconductor layer,

wherein an off-state current of the first transistor is 1×10 −13 A or less, and

wherein a capacitor element electrically connected to the gate of the second transistor is not provided.

11. The memory cell according to claim 10 , wherein the off-state current of the first transistor is 1×10 −13 A or less when a drain voltage is +1 V or +10 V and a gate voltage is in the range of −5 V to −20 V.

12. The memory cell according to claim 10 , wherein the oxide semiconductor layer is In—Ga—Zn—O-based oxide semiconductor, In—Sn—Zn—O-based oxide semiconductor, In—Al—Zn—O-based oxide semiconductor, Sn—Ga—Zn—O-based oxide semiconductor, Al—Ga—Zn—O-based oxide semiconductor, Sn—Al—Zn—O-based oxide semiconductor, In—Zn—O-based oxide semiconductor, Sn—Zn—O-based oxide semiconductor, Al—Zn—O-based oxide semiconductor, In—O-based oxide semiconductor, Sn—O-based oxide semiconductor, or Zn—O-based oxide semiconductor.

13. The memory cell according to claim 10 , wherein a hydrogen concentration measured by secondary ion mass spectrometry in the oxide semiconductor layer is 5×10 19 atoms/cm 3 or lower.

14. The memory cell according to claim 10 , wherein a channel formation region of the second transistor includes silicon.

15. A memory cell comprising:

a first transistor, a second transistor and a third transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor,

wherein one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the third transistor,

wherein a channel formation region of the first transistor includes an oxide semiconductor layer,

wherein the oxide semiconductor layer includes a crystal whose c-axis is arranged perpendicular to a surface of the oxide semiconductor layer, and

wherein a capacitor element electrically connected to the gate of the second transistor is not provided.

16. The memory cell according to claim 15 , wherein the oxide semiconductor layer is In—Ga—Zn—O-based oxide semiconductor, In—Sn—Zn—O-based oxide semiconductor, In—Al—Zn—O-based oxide semiconductor, Sn—Ga—Zn—O-based oxide semiconductor, Al—Ga—Zn—O-based oxide semiconductor, Sn—Al—Zn—O-based oxide semiconductor, In—Zn—O-based oxide semiconductor, Sn—Zn—O-based oxide semiconductor, Al—Zn—O-based oxide semiconductor, In—O-based oxide semiconductor, Sn—O-based oxide semiconductor, or Zn—O-based oxide semiconductor.

17. The memory cell according to claim 15 , wherein a hydrogen concentration measured by secondary ion mass spectrometry in the oxide semiconductor layer is 5×10 19 atoms/cm 3 or lower.

18. The memory cell according to claim 15 , wherein a channel formation region of the second transistor includes silicon.

19. A memory cell comprising:

a first transistor, a second transistor and a third transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor,

wherein one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the third transistor,

wherein a channel formation region of the first transistor includes an oxide semiconductor layer,

wherein the oxide semiconductor layer includes an intrinsic or substantially intrinsic region,

wherein the oxide semiconductor layer includes a crystal whose c-axis is arranged perpendicular to a surface of the oxide semiconductor layer, and

wherein an off-state current of the first transistor is 1×10 −13 A or less.

20. The memory cell according to claim 19 , wherein the off-state current of the first transistor is 1×10 −13 A or less when a drain voltage is +1 V or +10 V and a gate voltage is in the range of −5 V to −20 V.

21. The memory cell according to claim 19 , wherein the oxide semiconductor layer is In—Ga—Zn—O-based oxide semiconductor, In—Sn—Zn—O-based oxide semiconductor, In—Al—Zn—O-based oxide semiconductor, Sn—Ga—Zn—O-based oxide semiconductor, Al—Ga—Zn—O-based oxide semiconductor, Sn—Al—Zn—O-based oxide semiconductor, In—Zn—O-based oxide semiconductor, Sn—Zn—O-based oxide semiconductor, Al—Zn—O-based oxide semiconductor, In—O-based oxide semiconductor, Sn—O-based oxide semiconductor, or Zn—O-based oxide semiconductor.

22. The memory cell according to claim 19 , wherein a hydrogen concentration measured by secondary ion mass spectrometry in the oxide semiconductor layer is 5×10 19 atoms/cm 3 or lower.

23. The memory cell according to claim 19 , wherein a channel formation region of the second transistor includes silicon.

24. A memory cell comprising:

a first transistor, a second transistor and a third transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor,

wherein one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the third transistor,

wherein a channel formation region of the first transistor includes an oxide semiconductor layer,

wherein the oxide semiconductor layer includes an intrinsic or substantially intrinsic region, and

wherein the oxide semiconductor layer includes a crystal whose c-axis is arranged perpendicular to a surface of the oxide semiconductor layer.

25. The memory cell according to claim 24 , wherein the oxide semiconductor layer is In—Ga—Zn—O-based oxide semiconductor, In—Sn—Zn—O-based oxide semiconductor, In—Al—Zn—O-based oxide semiconductor, Sn—Ga—Zn—O-based oxide semiconductor, Al—Ga—Zn—O-based oxide semiconductor, Sn—Al—Zn—O-based oxide semiconductor, In—Zn—O-based oxide semiconductor, Sn—Zn—O-based oxide semiconductor, Al—Zn—O-based oxide semiconductor, In—O-based oxide semiconductor, Sn—O-based oxide semiconductor, or Zn—O-based oxide semiconductor.

26. The memory cell according to claim 24 , wherein a hydrogen concentration measured by secondary ion mass spectrometry in the oxide semiconductor layer is 5×10 19 atoms/cm 3 or lower.

27. The memory cell according to claim 24 , wherein a channel formation region of the second transistor includes silicon.

28. A memory cell comprising:

a first transistor, a second transistor and a third transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor,

wherein one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the third transistor,

wherein a channel formation region of the first transistor includes an oxide semiconductor layer,

wherein the oxide semiconductor layer includes an intrinsic or substantially intrinsic region,

wherein the oxide semiconductor layer includes a crystal whose c-axis is arranged perpendicular to a surface of the oxide semiconductor layer,

wherein an off-state current of the first transistor is 1×10 −13 A or less, and

wherein a capacitor element electrically connected to the gate of the second transistor is not provided.

29. The memory cell according to claim 28 , wherein the off-state current of the first transistor is 1×10 −13 A or less when a drain voltage is +1 V or +10 V and a gate voltage is in the range of −5 V to −20 V.

30. The memory cell according to claim 28 , wherein the oxide semiconductor layer is In—Ga—Zn—O-based oxide semiconductor, In—Sn—Zn—O-based oxide semiconductor, In—Al—Zn—O-based oxide semiconductor, Sn—Ga—Zn—O-based oxide semiconductor, Al—Ga—Zn—O-based oxide semiconductor, Sn—Al—Zn—O-based oxide semiconductor, In—Zn—O-based oxide semiconductor, Sn—Zn—O-based oxide semiconductor, Al—Zn—O-based oxide semiconductor, In—O-based oxide semiconductor, Sn—O-based oxide semiconductor, or Zn—O-based oxide semiconductor.

31. The memory cell according to claim 28 , wherein a hydrogen concentration measured by secondary ion mass spectrometry in the oxide semiconductor layer is 5×10 19 atoms/cm 3 or lower.

32. The memory cell according to claim 28 , wherein a channel formation region of the second transistor includes silicon.

33. A memory cell comprising:

a first transistor, a second transistor and a third transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor,

wherein one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the third transistor,

wherein a channel formation region of the first transistor includes an oxide semiconductor layer,

wherein the oxide semiconductor layer includes an intrinsic or substantially intrinsic region,

wherein the oxide semiconductor layer includes a crystal whose c-axis is arranged perpendicular to a surface of the oxide semiconductor layer, and

wherein a capacitor element electrically connected to the gate of the second transistor is not provided.

34. The memory cell according to claim 33 , wherein the oxide semiconductor layer is In—Ga—Zn—O-based oxide semiconductor, In—Sn—Zn—O-based oxide semiconductor, In—Al—Zn—O-based oxide semiconductor, Sn—Ga—Zn—O-based oxide semiconductor, Al—Ga—Zn—O-based oxide semiconductor, Sn—Al—Zn—O-based oxide semiconductor, In—Zn—O-based oxide semiconductor, Sn—Zn—O-based oxide semiconductor, Al—Zn—O-based oxide semiconductor, In—O-based oxide semiconductor, Sn—O-based oxide semiconductor, or Zn—O-based oxide semiconductor.

35. The memory cell according to claim 33 , wherein a hydrogen concentration measured by secondary ion mass spectrometry in the oxide semiconductor layer is 5×10 19 atoms/cm 3 or lower.

36. The memory cell according to claim 33 , wherein a channel formation region of the second transistor includes silicon.

37. A memory cell comprising:

a first transistor, a second transistor and a third transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor,

wherein one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the third transistor,

wherein a channel formation region of the first transistor includes an oxide semiconductor layer,

wherein the oxide semiconductor layer includes a crystal whose c-axis is arranged perpendicular to a surface of the oxide semiconductor layer,

wherein an off-state current of the first transistor is 1×10 −13 A or less, and

wherein a capacitor element electrically connected to the gate of the second transistor is provided.

38. The memory cell according to claim 37 , wherein the off-state current of the first transistor is 1×10 −13 A or less when a drain voltage is +1 V or +10 V and a gate voltage is in the range of −5 V to −20 V.

39. The memory cell according to claim 37 , wherein the oxide semiconductor layer is In—Ga—Zn—O-based oxide semiconductor, In—Sn—Zn—O-based oxide semiconductor, In—Al—Zn—O-based oxide semiconductor, Sn—Ga—Zn—O-based oxide semiconductor, Al—Ga—Zn—O-based oxide semiconductor, Sn—Al—Zn—O-based oxide semiconductor, In—Zn—O-based oxide semiconductor, Sn—Zn—O-based oxide semiconductor, Al—Zn—O-based oxide semiconductor, In—O-based oxide semiconductor, Sn—O-based oxide semiconductor, or Zn—O-based oxide semiconductor.

40. The memory cell according to claim 37 , wherein a hydrogen concentration measured by secondary ion mass spectrometry in the oxide semiconductor layer is 5×10 19 atoms/cm 3 or lower.

41. The memory cell according to claim 37 , wherein a channel formation region of the second transistor includes silicon.

42. A memory cell comprising:

a first transistor, a second transistor and a third transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor,

wherein one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the third transistor,

wherein a channel formation region of the first transistor includes an oxide semiconductor layer,

wherein the oxide semiconductor layer includes a crystal whose c-axis is arranged perpendicular to a surface of the oxide semiconductor layer, and

wherein a capacitor element electrically connected to the gate of the second transistor is provided.

43. The memory cell according to claim 42 , wherein the oxide semiconductor layer is In—Ga—Zn—O-based oxide semiconductor, In—Sn—Zn—O-based oxide semiconductor, In—Al—Zn—O-based oxide semiconductor, Sn—Ga—Zn—O-based oxide semiconductor, Al—Ga—Zn—O-based oxide semiconductor, Sn—Al—Zn—O-based oxide semiconductor, In—Zn—O-based oxide semiconductor, Sn—Zn—O-based oxide semiconductor, Al—Zn—O-based oxide semiconductor, In—O-based oxide semiconductor, Sn—O-based oxide semiconductor, or Zn—O-based oxide semiconductor.

44. The memory cell according to claim 42 , wherein a hydrogen concentration measured by secondary ion mass spectrometry in the oxide semiconductor layer is 5×10 19 atoms/cm 3 or lower.

45. The memory cell according to claim 42 , wherein a channel formation region of the second transistor includes silicon.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2023
From: YAMAZAKI, SHUNPEI; KOYAMA, JUN; KATO, KIYOSHI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 064649/0210 →
Priority Claims (1)
JP 2009-251261 · Oct 30, 2009 · national
Continuity (9)
Continuation 17582092 · Jan 24, 2022
Continuation 16944289 · Jul 31, 2020
Continuation 16558386 · Sep 3, 2019
Continuation 15615873 · Jun 7, 2017
Continuation 15175190 · Jun 7, 2016
Continuation 14804478 · Jul 21, 2015
Continuation 14336107 · Jul 21, 2014
Division 12914672 · Oct 28, 2010
Related Publication 20230397448A1 · Dec 7, 2023
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