IP Library Granted Patent US 12,320,844
Granted Patent B2
US 12,320,844 · App. 18/369,171 · Granted Jun 3, 2025

Integrated circuit profiling and anomaly detection

Inventors: Evelyn Landman (Haifa, IL); Yahel David (Kibbutz Gazit, IL); Eyal Fayneh (Givatayim, IL); Shai Cohen (Haifa, IL); Yair Talker (Binyamina, IL)
Assignee: PROTEANTECS LTD.
G01R31/31707G01R31/2803G01R31/2894G01R31/31718G06N3/08G06N7/01
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Quick Facts
Patent No.
US 12,320,844
App. No.
18/369,171
Granted
Jun 3, 2025
Kind
B2
Abstract

A computerized method for IC classification, outlier detection and/or anomaly detection comprising using at least one hardware processor for testing each of the plurality of ICs in accordance with an IC design on a wafer, wherein the IC design comprises a plurality of sensors. The at least one hardware processor is used for testing each of the plurality of ICs by: collecting a plurality of sensor values, the plurality of sensor values including sensor values from each of the plurality of sensors; comparing the plurality of sensor values to a classification scheme, thereby obtaining a classification for each tested IC; and recording the classification of the tested IC.

Claims (71)

1. A computer program product comprising computer readable instructions that are configured, when operated on at least one hardware processor, to:

collect at least one sensor value from each of a plurality of sensors that are comprised in multiple Integrated Circuit (IC) dies that are manufactured according to a common IC design, wherein the at least one sensor value is indicative of field performance of the respective IC die; and

classify each of the multiple IC dies based on the field performance indicated by the at least one sensor value.

2. The computer program product of claim 1 , wherein the instructions are further configured to compare the collected at least one sensor value to a classification scheme, thereby enabling the classification of each of the multiple IC dies.

3. The computer program product of claim 2 , wherein the classification scheme is based on at least one of:

simulations of a plurality of IC operations of the common IC design and a fabrication process, wherein the simulations are selected from the group consisting of: at least one complete IC design simulation, at least one partial IC design simulation, and at least one device simulation for the fabrication process;

a plurality of training sensor values collected during a pre-production tape-out test; or

the collected at least one sensor value.

4. The computer program product of claim 2 , wherein the comparing comprises:

estimating high coverage measurements from the collected at least one sensor value using a function and/or a rule that are determined from a training set of: sensor values, and training high coverage measurements.

5. The computer program product of claim 1 , wherein the instructions are further configured to:

(i) from each of the IC dies, determine a set of parameters of a fabrication process based on the classification and the collected at least one sensor value; and

(ii) select a second set of parameters of the fabrication process based on the common IC design and the sets of parameters of the fabrication process for each of the IC dies,

to enable manufacturing additional IC dies using the second set of parameters.

6. The computer program product of claim 2 , wherein the instructions are further configured to:

determine the classification scheme based on a plurality of classification values by:

establishing a matrix representation from the plurality of classification values, each row of the matrix representation comprising classification values in respect of one of the IC dies;

computing a covariance matrix from the matrix representation and a singular value decomposition (SVD) for the covariance matrix;

determining, using the SVD, a plurality of distance values, each distance value representing a respective distance between one of the IC dies and another one of the IC dies; and

identifying, from the plurality of distance values, at least one family, thereby defining the classification scheme.

7. The computer program product of claim 6 , wherein the step of identifying comprises:

classifying a first IC die of the IC dies in a first family, such that the first family is defined by the first IC die;

comparing a distance value, from the plurality of distance values, representing a distance between the first IC die and a second IC die of the IC dies with a predetermined threshold;

if the distance value is less than the predetermined threshold, classifying the second IC die in the first family; and

if the distance value is greater than the predetermined threshold, classifying the second IC die in a second family, such that the second family is defined by the second IC die.

8. The computer program product of claim 7 , wherein the step of identifying further comprises, for each other IC die of the IC dies:

identifying a group of distance values, from the plurality of distance values, each distance value in the group of distance values representing a distance between the other IC die and a respective IC die of the IC dies that defines a respective family;

comparing each distance value from the group of distance values with the predetermined threshold;

if a distance value from the group of distance values, representing a distance between the respective other IC die and a specific IC die of the IC dies that defines a specific family, is less than the predetermined threshold, classifying the other IC die in the specific family; and

if all the distance values from the group of distance values are greater than the predetermined threshold, classifying the other IC die in a new family, such that the new family is defined by the other IC die.

9. The computer program product of claim 6 , wherein the instructions are further configured to normalize the matrix representation prior to computing the covariance matrix.

10. The computer program product of claim 6 , wherein the plurality of classification values are based on at least one of:

simulated values determined from a simulation of the common IC design;

a plurality of training sensor values collected from the sensors of the common IC design during a pre-production tape-out test; or

measured sensor values collected from the sensors.

11. The computer program product of claim 6 , wherein the step of identifying the classification scheme is part of the step of comparing the plurality of collected sensor values to the classification scheme, thereby enabling the classification of each of the multiple IC dies.

12. The computer program product of claim 6 , wherein:

the plurality of classification values are based on simulated sensor values determined from a simulation of the common IC design;

the step of determining the classification scheme takes place before the step of comparing the collected at least one sensor value to the classification scheme; and

the step of comparing the collected at least one sensor value to the classification scheme comprises:

establishing a collected data matrix representation from the collected sensor values, each row of the matrix representation comprising collected sensor values in respect of one of the IC dies, and

determining, using the collected data matrix representation, a plurality of collected data distance values, each distance value representing a respective distance between one IC die of the IC dies and another one of the IC dies,

wherein the classifying is based on the plurality of distance values scheme.

13. The computer program product of claim 12 , wherein:

the step of computing the covariance matrix from the matrix representation comprises normalizing the matrix representation prior to computing the covariance matrix, to define normalization coefficients thereby; and

the step of establishing the collected data covariance matrix comprises normalizing the matrix representation using the defined normalization coefficients.

14. The computer program product of claim 6 , wherein the matrix representation is established from at least one of:

simulated sensor values determined from a simulation of the common IC design;

operational parameters determined from a simulation of the common IC design; or

design signature values.

15. The computer program product of claim 6 , wherein the matrix representation is established from Pre-Si (pre-silicon) data, and wherein the step of determining, using the SVD, the plurality of distance values, comprises:

defining a set of Pre-Si SVD signatures by identifying at least one of the following:

vectors of the SVD for which the corresponding principal values of the SVD are greater than a pre-defined value, or

a pre-defined number of vectors of the SVD for which the corresponding principal values of the SVD are the greatest; and

determining the plurality of distance values using the defined set of Pre-Si SVD signatures.

16. The computer program product of claim 15 , wherein the step of determining the plurality of distance values using the defined set of Pre-Si SVD signatures comprises:

calculating at least some of the plurality of distance values, each of the at least some of the plurality of distance values being based on a distance between one of the Pre-Si SVD signatures and another of the Pre-Si SVD signatures.

17. The computer program product of claim 15 , wherein the step of determining the plurality distance values using the defined set of Pre-Si SVD signatures comprises:

configuring a plurality of estimators from the simulated sensor values and the set of Pre-Si SVD signatures, each estimator generating an estimated SVD signature from input sensor values;

estimating from the plurality of estimators, for each of the plurality of IC dies, a respective Post-Si SVD signature from the collected sensor values; and

calculating at least some of the plurality of distance values, each of the at least some of the plurality of distance values being based on a distance between one of the Post-Si SVD signatures and another of the Post-Si SVD signatures.

18. The computer program product of claim 15 , wherein the step of determining the plurality distance values using the defined set of Pre-Si SVD signatures further comprises:

calculating further distance values of the plurality of distance values, each of the further distance values being based on a distance between one of the Pre-Si SVD signatures and one of the Post-Si SVD signatures.

19. A method comprising operating at least one hardware processor to:

collect at least one sensor value from each of a plurality of sensors that are comprised in multiple Integrated Circuit (IC) dies that are manufactured according to a common IC design, wherein the at least one sensor value is indicative of field performance of the respective IC die; and

classify each of the multiple IC dies based on the field performance indicated by the at least one sensor value.

20. A computerized system comprising:

(a) at least one hardware processor; and

(b) a non-transitory computer-readable storage medium having program code embodied therewith, the program code executable by said at least one hardware processor to:

collect at least one sensor value from each of a plurality of sensors that are comprised in multiple Integrated Circuit (IC) dies that are manufactured according to a common IC design, wherein the at least one sensor value is indicative of field performance of the respective IC die, and

classify each of the multiple IC dies based on the field performance indicated by the at least one sensor value.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2023
From: LANDMAN, EVELYN; DAVID, YAHEL; FAYNEH, EYAL; COHEN, SHAI; TALKER, YAIR
To: PROTEANTECS LTD.
Reel/Frame 064928/0910 →
Continuity (3)
Continuation 17047243
Provisional Application 62657986 · Apr 16, 2018
Related Publication 20240003968A1 · Jan 4, 2024
References Cited (308)
US 4555663A · Shimizu · 1985 [cited by applicant]
US 5548539A · Vlach et al. · 1996 [cited by applicant]
US 5748509A · Fewster · 1998 [cited by applicant]
US 5774403A · Clark, II et al. · 1998 [cited by applicant]
US 5818251A · Intrater · 1998 [cited by applicant]
US 5895629A · Russell et al. · 1999 [cited by applicant]
US 5956497A · Ratzel et al. · 1999 [cited by applicant]
US 5966527A · Krivokapic et al. · 1999 [cited by applicant]
US 6140833A · Flietner et al. · 2000 [cited by applicant]
US 6172546B1 · Liu et al. · 2001 [cited by applicant]
US 6182253B1 · Lawrence et al. · 2001 [cited by applicant]
US 6486716B1 · Minami et al. · 2002 [cited by applicant]
US 6586921B1 · Sunter · 2003 [cited by applicant]
US 6683484B1 · Kueng et al. · 2004 [cited by applicant]
US 6807503B2 · Ye · 2004 [cited by examiner]
US 6873926B1 · Diab · 2005 [cited by applicant]
US 6882172B1 · Suzuki et al. · 2005 [cited by applicant]
US 6948388B1 · Clayton et al. · 2005 [cited by applicant]
US 7038483B1 · Suzuki et al. · 2006 [cited by applicant]
US 7067335B2 · Weiner et al. · 2006 [cited by applicant]
US 7254507B2 · Dosho et al. · 2007 [cited by applicant]
US 7288958B2 · Takagi · 2007 [cited by applicant]
US 7369893B2 · Gunderson · 2008 [cited by applicant]
US 7443189B2 · Ramappa · 2008 [cited by applicant]
US 7455450B2 · Liu et al. · 2008 [cited by applicant]
US 7501832B2 · Spuhler et al. · 2009 [cited by applicant]
US 7649373B2 · Tokunaga · 2010 [cited by applicant]
US 7701246B1 · Plants et al. · 2010 [cited by applicant]
US 7818601B2 · LaBerge · 2010 [cited by applicant]
US 7877657B1 · Miller et al. · 2011 [cited by applicant]
US 7940862B2 · Tanaka et al. · 2011 [cited by applicant]
US 8001512B1 · White · 2011 [cited by applicant]
US 8086978B2 · Zhang et al. · 2011 [cited by applicant]
US 8170067B2 · Zerbe et al. · 2012 [cited by applicant]
US 8279976B2 · Lin et al. · 2012 [cited by applicant]
US 8310265B2 · Zjajo et al. · 2012 [cited by applicant]
US 8365115B2 · Liu et al. · 2013 [cited by applicant]
US 8418103B2 · Wang et al. · 2013 [cited by applicant]
US 8479130B1 · Zhang et al. · 2013 [cited by applicant]
US 8633722B1 · Lai · 2014 [cited by applicant]
US 8825158B2 · Swerdlow · 2014 [cited by applicant]
US 8996937B2 · Jain et al. · 2015 [cited by applicant]
US 9275706B2 · Tam · 2016 [cited by applicant]
US 9424952B1 · Seok et al. · 2016 [cited by applicant]
US 9490787B1 · Kho et al. · 2016 [cited by applicant]
US 9536038B1 · Quinton et al. · 2017 [cited by applicant]
US 9564883B1 · Quinton et al. · 2017 [cited by applicant]
US 9564884B1 · Quinton et al. · 2017 [cited by applicant]
US 9632126B2 · Yoon et al. · 2017 [cited by applicant]
US 9714966B2 · Chen et al. · 2017 [cited by applicant]
US 9760672B1 · Taneja et al. · 2017 [cited by applicant]
US 9791834B1 · Nassar et al. · 2017 [cited by applicant]
US 9954455B2 · Lin et al. · 2018 [cited by applicant]
US 9977078B2 · Loke et al. · 2018 [cited by applicant]
US 9991879B2 · Huang · 2018 [cited by applicant]
US 10490547B1 · Ali et al. · 2019 [cited by applicant]
US 10509104B1 · Dato · 2019 [cited by applicant]
US 10530347B2 · Tang et al. · 2020 [cited by applicant]
US 11036266B2 · Srivastava et al. · 2021 [cited by applicant]
US 11081193B1 · Tang · 2021 [cited by applicant]
US 11409323B2 · Herberholz et al. · 2022 [cited by applicant]
US 11762013B2 · Landman · 2023 [cited by examiner]
US 12013800B1 · Fayneh et al. · 2024 [cited by applicant]
US 20010013111A1 · Bishop et al. · 2001 [cited by applicant]
US 20040009616A1 · Huisman et al. · 2004 [cited by applicant]
US 20040015793A1 · Saxena et al. · 2004 [cited by applicant]
US 20040230385A1 · Bechhoefer et al. · 2004 [cited by applicant]
US 20040230396A1 · Ye et al. · 2004 [cited by applicant]
US 20040267479A1 · Querbach et al. · 2004 [cited by applicant]
US 20050053162A1 · Goishi · 2005 [cited by applicant]
US 20050104175A1 · Itano · 2005 [cited by applicant]
US 20050114056A1 · Patel et al. · 2005 [cited by applicant]
US 20050134350A1 · Huang et al. · 2005 [cited by applicant]
US 20050134394A1 · Liu · 2005 [cited by applicant]
US 20050154552A1 · Stroud et al. · 2005 [cited by applicant]
US 20050193302A1 · Arguelles et al. · 2005 [cited by applicant]
US 20050285646A1 · Rashid · 2005 [cited by applicant]
US 20060049886A1 · Agostinelli, Jr. et al. · 2006 [cited by applicant]
US 20060224374A1 · Kwon et al. · 2006 [cited by applicant]
US 20070110199A1 · Momtaz et al. · 2007 [cited by applicant]
US 20070182456A1 · Agarwal et al. · 2007 [cited by applicant]
US 20070288183A1 · Bulkes et al. · 2007 [cited by applicant]
US 20080071489A1 · Wissel · 2008 [cited by applicant]
US 20080074521A1 · Olsen · 2008 [cited by applicant]
US 20080144243A1 · Mariani et al. · 2008 [cited by applicant]
US 20080147355A1 · Fields et al. · 2008 [cited by applicant]
US 20080183409A1 · Roberts et al. · 2008 [cited by applicant]
US 20080186001A1 · Singh et al. · 2008 [cited by applicant]
US 20080186044A1 · Singh · 2008 [cited by applicant]
US 20080216033A1 · Bucossi et al. · 2008 [cited by applicant]
US 20080231310A1 · Vijayaraghavan · 2008 [cited by applicant]
US 20080262769A1 · Kadosh et al. · 2008 [cited by applicant]
US 20090027077A1 · Vijayaraghavan et al. · 2009 [cited by applicant]
US 20090044160A1 · Bueti et al. · 2009 [cited by applicant]
US 20090076753A1 · Vijayaraghavan et al. · 2009 [cited by applicant]
US 20090096495A1 · Keigo · 2009 [cited by applicant]
US 20090105978A1 · Schuttert et al. · 2009 [cited by applicant]
US 20090183043A1 · Niwa · 2009 [cited by applicant]
US 20090222775A1 · Idgunji et al. · 2009 [cited by applicant]
US 20090230947A1 · Sumita · 2009 [cited by applicant]
US 20090244998A1 · Kim et al. · 2009 [cited by applicant]
US 20090273550A1 · Vieri et al. · 2009 [cited by applicant]
US 20090278576A1 · Chakravarty · 2009 [cited by applicant]
US 20090306953A1 · Liu et al. · 2009 [cited by applicant]
US 20100153896A1 · Sewall et al. · 2010 [cited by applicant]
US 20100251046A1 · Mizuno et al. · 2010 [cited by applicant]
US 20100253382A1 · Wang et al. · 2010 [cited by applicant]
US 20110093830A1 · Chen et al. · 2011 [cited by applicant]
US 20110102091A1 · Yeric · 2011 [cited by applicant]
US 20110109377A1 · Fujibe et al. · 2011 [cited by applicant]
US 20110113298A1 · Van Den Eijnden · 2011 [cited by applicant]
US 20110169537A1 · Ma · 2011 [cited by applicant]
US 20110175658A1 · Nomura · 2011 [cited by applicant]
US 20110187433A1 · Baumann et al. · 2011 [cited by applicant]
US 20110267096A1 · Chlipala et al. · 2011 [cited by applicant]
US 20110295403A1 · Higuchi et al. · 2011 [cited by applicant]
US 20110315986A1 · Kaneda et al. · 2011 [cited by applicant]
US 20120025846A1 · Minas et al. · 2012 [cited by applicant]
US 20120038388A1 · Tseng et al. · 2012 [cited by applicant]
US 20120051395A1 · Chen et al. · 2012 [cited by applicant]
US 20120063524A1 · Stott · 2012 [cited by applicant]
US 20120074973A1 · Baldwin et al. · 2012 [cited by applicant]
US 20120163074A1 · Franca-Neto et al. · 2012 [cited by applicant]
US 20120170616A1 · Tsai et al. · 2012 [cited by applicant]
US 20120187991A1 · Sathe et al. · 2012 [cited by applicant]
US 20120212246A1 · Benjamin et al. · 2012 [cited by applicant]
US 20120217976A1 · Clarkson · 2012 [cited by applicant]
US 20120221906A1 · Shetty et al. · 2012 [cited by applicant]
US 20120242490A1 · Ramaswami · 2012 [cited by applicant]
US 20130088256A1 · Chlipala et al. · 2013 [cited by applicant]
US 20130226491A1 · Miguelanez, II et al. · 2013 [cited by applicant]
US 20130241690A1 · Wallace et al. · 2013 [cited by applicant]
US 20130293270A1 · Lee et al. · 2013 [cited by applicant]
US 20130335875A1 · Baumann · 2013 [cited by applicant]
US 20140132293A1 · Abadir et al. · 2014 [cited by applicant]
US 20140132315A1 · Sharma et al. · 2014 [cited by applicant]
US 20140143586A1 · Dalumi et al. · 2014 [cited by applicant]
US 20140184243A1 · Iyer et al. · 2014 [cited by applicant]
US 20140254734A1 · Abdelmoneum et al. · 2014 [cited by applicant]
US 20150061707A1 · Balasubramanian et al. · 2015 [cited by applicant]
US 20150061721A1 · Jeong · 2015 [cited by applicant]
US 20150077136A1 · Li · 2015 [cited by applicant]
US 20150121158A1 · Wang et al. · 2015 [cited by applicant]
US 20150199223A1 · Banerjee et al. · 2015 [cited by applicant]
US 20150332451A1 · Amzaleg et al. · 2015 [cited by applicant]
US 20150355033A1 · Zhang et al. · 2015 [cited by applicant]
US 20150365049A1 · Ozawa et al. · 2015 [cited by applicant]
US 20160033574A1 · Serrer et al. · 2016 [cited by applicant]
US 20160042784A1 · Rim et al. · 2016 [cited by applicant]
US 20160072511A1 · Maekawa · 2016 [cited by applicant]
US 20160087643A1 · Nozaki · 2016 [cited by applicant]
US 20160125434A1 · Kohn · 2016 [cited by examiner]
US 20160131708A1 · Huang et al. · 2016 [cited by applicant]
US 20160153840A1 · Huang et al. · 2016 [cited by applicant]
US 20160156176A1 · Kunz, Jr et al. · 2016 [cited by applicant]
US 20160164503A1 · Kim et al. · 2016 [cited by applicant]
US 20160203036A1 · Mezic et al. · 2016 [cited by applicant]
US 20160254804A1 · Meng · 2016 [cited by applicant]
US 20170038265A1 · Abdelmoneum et al. · 2017 [cited by applicant]
US 20170093399A1 · Atkinson et al. · 2017 [cited by applicant]
US 20170160339A1 · Jenkins · 2017 [cited by applicant]
US 20170179173A1 · Mandai et al. · 2017 [cited by applicant]
US 20170199089A1 · Fritchman et al. · 2017 [cited by applicant]
US 20170199228A1 · Hsieh et al. · 2017 [cited by applicant]
US 20170214516A1 · Rivaud et al. · 2017 [cited by applicant]
US 20170329391A1 · Jaffari et al. · 2017 [cited by applicant]
US 20170344102A1 · Kolla et al. · 2017 [cited by applicant]
US 20170345490A1 · Yoshimoto et al. · 2017 [cited by applicant]
US 20170364818A1 · Wu et al. · 2017 [cited by applicant]
US 20180034549A1 · Kikuchi · 2018 [cited by applicant]
US 20180109245A1 · Takagi · 2018 [cited by applicant]
US 20180183413A1 · Wong et al. · 2018 [cited by applicant]
US 20180365974A1 · Haas et al. · 2018 [cited by applicant]
US 20190019096A1 · Yoshida et al. · 2019 [cited by applicant]
US 20190117122A1 · Kurachi et al. · 2019 [cited by applicant]
US 20190128961A1 · Heron et al. · 2019 [cited by applicant]
US 20190162783A1 · Huang · 2019 [cited by applicant]
US 20190305074A1 · Kande et al. · 2019 [cited by applicant]
US 20200028514A1 · Hanke et al. · 2020 [cited by applicant]
US 20200203333A1 · Chen et al. · 2020 [cited by applicant]
US 20200209070A1 · Tang et al. · 2020 [cited by applicant]
US 20200309850A1 · Bismuth · 2020 [cited by applicant]
US 20200313664A1 · Azam et al. · 2020 [cited by applicant]
US 20210325455A1 · Fayneh et al. · 2021 [cited by applicant]
US 20210341535A1 · Hsieh et al. · 2021 [cited by applicant]
US 20220260630A1 · Fayneh et al. · 2022 [cited by applicant]
US 20220349935A1 · Fayneh et al. · 2022 [cited by applicant]
US 20230098071A1 · Chonnad et al. · 2023 [cited by applicant]
CN 1886668A · 2006 [cited by applicant]
CN 101014991A · 2007 [cited by applicant]
CN 101241429A · 2008 [cited by applicant]
CN 101344898A · 2009 [cited by applicant]
CN 102422169A · 2012 [cited by applicant]
CN 101915625B · 2012 [cited by applicant]
CN 102273077B · 2014 [cited by applicant]
CN 105210188A · 2015 [cited by applicant]
CN 106959400A · 2017 [cited by applicant]
CN 108534866A · 2018 [cited by applicant]
CN 113466670A · 2021 [cited by applicant]
DE 102007002253A1 · 2007 [cited by applicant]
DE 102014216786B3 · 2015 [cited by applicant]
DE 102012219971A1 · 2016 [cited by applicant]
EP 962991A1 · 1999 [cited by applicant]
EP 1262755A1 · 2002 [cited by applicant]
EP 2006784A1 · 2008 [cited by applicant]
EP 2060924A1 · 2009 [cited by applicant]
EP 2413150A1 · 2012 [cited by applicant]
EP 2770313A1 · 2014 [cited by applicant]
JP S57116228A · 1982 [cited by applicant]
JP 2000215693A · 2000 [cited by applicant]
JP 2002243800A · 2002 [cited by applicant]
JP 2008147245A · 2008 [cited by applicant]
JP 2009021348A · 2009 [cited by applicant]
JP 2009065533A · 2009 [cited by applicant]
JP 2009074921A · 2009 [cited by applicant]
JP 2011204328A · 2011 [cited by applicant]
JP 2012037238A · 2012 [cited by applicant]
JP 2012088322A · 2012 [cited by applicant]
JP 2014085348A · 2014 [cited by applicant]
JP 2016111563A · 2016 [cited by applicant]
KR 101232207B1 · 2013 [cited by applicant]
KR 2013110989A · 2013 [cited by applicant]
KR 20150073199A · 2015 [cited by applicant]
TW 200914841A · 2009 [cited by applicant]
TW 201614256A · 2016 [cited by applicant]
TW 201709669A · 2017 [cited by applicant]
WO 2005080099A1 · 2005 [cited by applicant]
WO 2013070218A1 · 2013 [cited by applicant]
WO 2013027739A1 · 2015 [cited by applicant]
WO 2019097516A1 · 2019 [cited by applicant]
WO 2019102467A1 · 2019 [cited by applicant]
WO 2019135247A1 · 2019 [cited by applicant]
WO 2019202595A1 · 2019 [cited by applicant]
WO 2019244154A1 · 2019 [cited by applicant]
WO 2020141516A1 · 2020 [cited by applicant]
WO 2020230130A1 · 2020 [cited by applicant]
WO 2021019539A1 · 2021 [cited by applicant]
WO 2021111444A1 · 2021 [cited by applicant]
WO 2021214562A1 · 2021 [cited by applicant]
WO 2022009199A1 · 2022 [cited by applicant]
WO 2022215076A1 · 2022 [cited by applicant]
WO 2023238128A1 · 2023 [cited by applicant]
WO 2024166103A1 · 2024 [cited by applicant]
Mridul Agarwal et al, “Circuit Failure Prediction and Its Application to Transistor Aging”; 5th IEEE VLSI Test Symposium (VTS'07), pp. 277-286, May 6-10, 2007. doi: 10.1109/VTS.2007.22. [cited by applicant]
Keith A. Bowman et al, “Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance”; IEEE Journal of Solid-State Circuits vol. 44, Issue 1, pp. 49-63, Jan. 2009.doi: 10.1109/JSSC.2008.2… [cited by applicant]
Shidhartha Das et al, “A Self-Tuning DVS Processor Using Delay-Error Detection and Correction”; IEEE Journal of Solid-State Circuits; vol. 41, Issue 4, pp. 792-804, Apr. 2006. doi: 10.1109/JSSC.2006.870912. [cited by applicant]
Shidhartha Das et al, “Razorll: In Situ Error Detection and Correction for PVT and SER Tolerance” 2008 IEEE International Solid-State Circuits Conference—Digest of Technical Papers, Feb. 3-7, 2008. doi: 10.1109/JSSC.200… [cited by applicant]
Ramyanshu Datta et al, “On-Chip Delay Measurement for Silicon Debug”; GLSVLSI '04: Proceedings of the 14th ACM Great Lakes symposium on VLSI; pp. 145-148, Apr. 26-28, 2004. https://doi.org/10.1145/988952.988988. [cited by applicant]
Alan Drake et al, “A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor”; 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers; Feb. 11-15, 2007. doi: 10.1… [cited by applicant]
Matthias Eireiner et al, “In-Situ Delay Characterization and Local Supply Voltage Adjustment for Compensation of Local Parametric Variations”; IEEE Journal of Solid-State Circuits; vol. 42, Issue 7, pp. 1583-1592, Jul. … [cited by applicant]
Matthew Fojtik et al, “Bubble Razor: An architecture-independent approach to timing-error detection and correction”; 2012 IEEE International Solid-State Circuits Conference; Feb. 19-23, 2012. doi: 10.1109/ISSCC.2012.617… [cited by applicant]
Matthew Fojtik et al, “Bubble Razor: Eliminating Timing Margins in an ARM Cortex-M3 Processor in 45 nm CMOS Using Architecturally Independent Error Detection and Correction”; IEEE Journal of Solid-State Circuits; vol. 4… [cited by applicant]
Piero Franco et al, “On-Line Delay Testing of Digital Circuits”; Proceedings of IEEE VLSI Test Symposium; Apr. 25-28, 1994. doi: 10.1109/VTEST.1994.292318. [cited by applicant]
V. Huard et al, “Adaptive Wearout Management with in-situ aging monitors”; 2014 IEEE International Reliability Physics Symposium; Jun. 1-5, 2014. pp. 6B.4.1-6B.4.11, doi: 10.1109/IRPS.2014.6861106. [cited by applicant]
Liangzhen Lai et al, “SlackProbe: A Flexible and Efficient In Situ Timing Slack Monitoring Methodology”; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems; vol. 33, Issue 8, pp. 1168-1179, Au… [cited by applicant]
M. Saliva et al, “Digital Circuits Reliability with In-Situ Monitors in 28nm Fully Depleted SOI”; 2015 Design, Automation Mar. 9-13, 2015. doi: 10.7873/DATE.2015.0238. [cited by applicant]
Martin Wirnshofer et al, “A Variation-Aware Adaptive Voltage Scaling Technique based on In-Situ Delay Monitoring”; 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems; pp. 261-… [cited by applicant]
Martin Wirnshofer et al, “An Energy-Efficient Supply Voltage Scheme using In-Situ Pre-Error Detection for on-the-fly Voltage Adaptation to PVT Variations”; 2011 International Symposium on Integrated Circuits; pp. 94-97,… [cited by applicant]
Martin Wirnshofer et al, “On-line supply voltage scaling based on in situ delay monitoring to adapt for PVTA variations”; Journal of Circuits, Systems and Computers; vol. 21, No. 08, Mar. 7, 2012. doi: 10.1142/S02181266… [cited by applicant]
S. Mhira et al, “Dynamic Adaptive Voltage Scaling in Automotive environment”; 2017 IEEE International Reliability Physics Symposium (IRPS); pp. 3A-4.1-3A-4.7, Apr. 2-6, 2017. doi: 10.1109/IRPS.2017.7936279. [cited by applicant]
A. Benhassain et al, “Early failure prediction by using in-situ monitors: Implementation and application results”; Online at: https://ceur-ws.org/Vol-1566/Paper6.pdf, Mar. 18, 2016. [cited by applicant]
Charles R. Lefurgy et al, “Active Management of Timing Guardband to Save Energy in POWER7”; 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO); pp. 1-11; Dec. 3-7, 2011. [cited by applicant]
C. R. Lefurgy et al., “Active Guardband Management in Power7+ to Save Energy and Maintain Reliability”; in IEEE Micro, vol. 33, No. 4, pp. 35-45, Jul.-Aug. 2013. doi: 10.1109/MM.2013.52. [cited by applicant]
B. Zandian et al, “Cross-layer resilience using wearout aware design flow”; 2011 IEEE/IFIP 41st International Conference on Dependable Systems & Networks (DSN), pp. 279-290, Jun. 27-30, 2011. doi: 10.1109/DSN.2011.59582… [cited by applicant]
M. Cho et al., “Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating”; in IEEE Journal of Solid-State Circuits, vol. 52, No. 1, pp. 50-63, J… [cited by applicant]
W. Shan et al, “Timing error prediction based adaptive voltage scaling for dynamic variation tolerance”; 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 739-742, Nov. 17-20, 2014. doi: 10.1109/AP… [cited by applicant]
J. Li et al, “Robust and in-situ self-testing technique for monitoring device aging effects in pipeline circuits”; 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC), pp. 1-6, Jun. 1-5, 2014. [cited by applicant]
X. Shang et al, “A 0.44V-1.1V 9-transistor transition-detector and half-path error detection technique for low power applications”; 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 205-208, Nov. 6-8, 2017. … [cited by applicant]
Liangzhen Lai et al, “Accurate and inexpensive performance monitoring for variability-aware systems”; 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 467-473, Jan. 20-23, 2014. doi: 10.1109/… [cited by applicant]
Martin Wirnshofer et al, “Adaptive voltage scaling by in-situ delay monitoring for an image processing circuit”; 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS),… [cited by applicant]
Youhua Shi et al, “Suspicious timing error prediction with in-cycle clock gating”; International Symposium on Quality Electronic Design (ISQED), pp. 335-340, Mar. 4-6, 2013. doi: 10.1109/ISQED.2013.6523631. [cited by applicant]
Youhua Shi et al, “In-situ timing monitoring methods for variation-resilient designs”; 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 735-738, Nov. 17-20, 2014. doi: 10.1109/APCCAS.2014.7032886. [cited by applicant]
Jongho Kim et al., “Adaptive delay monitoring for wide voltage-range operation”; 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 511-516, Mar. 14-18, 2016. DOI: 10.3850/9783981537079_0330. [cited by applicant]
Xiaobin Yuan et al., “Design Considerations for Reconfigurable Delay Circuit to Emulate System Critical Paths”; in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, No. 11, pp. 2714-2718, Nov. 2… [cited by applicant]
Kan Takeuchi et al; “FEOL/BEOL wear-out estimator using stress-to-frequency conversion of voltage/temperature-sensitive ring oscillators for 28nm automotive MCUs”; IEEE, pp. 265-268, Oct. 20, 2016. doi: 10.1109/ESSCIRC.… [cited by applicant]
Kan Takeuchi et al; “Wear-out stress monitor utilising temperature and voltage sensitive ring oscillators” IET Circuits, Devices & Systems. vol. 12 No. 2, pp. 182-188, Jan. 15, 2018. doi: 10.1049/iet-cds.2017.0153. [cited by applicant]
Kan Takeuchi et al; “Experimental Implementation of 8.9Kgate Stress Monitor in 28nm MCU along with Safety Software Library for IoT Device Maintenance”; IEEE International Reliability Physics Symposium (IRPS). Mar. 31, 2… [cited by applicant]
Dan Ernst et al; “Razor: circuit-level correction of timing errors for low-power operation,” in IEEE Micro, vol. 24, No. 6, pp. 10-20, Nov.-Dec. 2004, doi: 10.1109/MM.2004.85. [cited by applicant]
Dan Ernst et al; “Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation”; Appears in the 36th Annual International Symposium on Microarchitecture (MICRO-36). Dec. 1, 2003. San Diego, CA, USA, 2003, pp. 7… [cited by applicant]
James P. Hofmeister, et al, “Ball Grid Array (BGA) Solder Joint Intermittency Detection: SJ BIST™”, IEEE Aerospace Conference Proceedings, Apr. 2008, paper #1148, Version 1. doi: 10.1109/AERO.2008.4526624. [cited by applicant]
Paulheim H, Meusel R. “A decomposition of the outlier detection problem into a set of supervised learning problems”, Machine Learning, Sep. 2015, vol. 100 Issue 2, pp. 509-531. DOI 10.1007/s10994-015-5507-y. [cited by applicant]
Zhang L, Marron JS, Shen H, Zhu Z., “Singular value decomposition and its visualization”, Journal of Computational and Graphical Statistics, Dec. 2007, vol. 6 Issue 4, pp. 833-854. DOI: 10.1198/106186007X256080. [cited by applicant]
Shinkai, Ken-ichi et al. “Device-parameter estimation with on-chip variation sensors considering random variability.”; In 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), pp. 683-688. IEEE, Jan. … [cited by applicant]
Weiwei Shan et al. “An improved timing error prediction monitor for wide adaptive frequency scaling”; IEICE Electronics Express, vol. 14, No. 21, pp. 1-6, Oct. 20, 2017. DOI: 10.1587/elex.14.20170808. [cited by applicant]
Agilent Technologies; “Clock Jitter Analysis with femto-second resolution”; Jan. 1, 2008. [cited by applicant]
Yousuke Miyake et al; “Temperature and voltage estimation using ring-oscillator-based monitor for field test”; IEEE 23rd Asian Test Symposium; pp. 156-161, Nov. 16, 2014. doi: 10.1109/ATS.2014.38. [cited by applicant]
Basab Datta at al.; “Analysis of A Ring Oscillator Based on Chip Thermal Sensor in 65nm Technology”. Online at: https://web.archive.org/web/20140328234617/http://www-unix.ecs.umass.edu/˜dkumar/lab4_658_report/lab4_repor… [cited by applicant]
Tilman Wolf et al; “Collaborative Monitors for Embedded System Security”. Jan. 1, 2006. First Workshop on Embedded System Security in conjunction with EMSOFT '06, Oct. 26, 2006, Seoul, South Korea. [cited by applicant]
Sandeep Kumar Samal et al; “Machine Learning Based Variation Modeling and Optimization for 3D ICs”; J. Inf. Commun. Converg. Eng. 14(4): 258-267, Dec. 2016. DOI: 10.6109/jicce.2016.14.4.258. [cited by applicant]
Yin-Nien Chen et al; “Impacts of Work Function Variation and Line-Edge Roughness on TFET and FinFET Devices and 32-Bit CLA Circuits”; J. Low Power Electron. Appl. 2015, 5, 101-115. May 21, 2015. doi:10.3390/jlpea5020101. [cited by applicant]
Yong Zhao et al; “A Genetic Algorithm Based Remaining Lifetime Prediction for a VLIW Processor Employing Path Delay and IDDX Testing”; IEEE; Apr. 12, 2016. 2016 11th International Conference on Design and Technology of … [cited by applicant]
Vivek S Nandakumar et al, “Statistical static timing analysis flow for transistor level macros in a microprocessor”; 2010, 11th International Symposium on Quality Electronic Design (ISQED), pp. 163-170, Mar. 22, 2010. d… [cited by applicant]
Jing Li et al, “Variation Estimation and Compensation Technique in Scaled Ltps TFT Circuits for Low-Power Low-Cost Applications”; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28(1)… [cited by applicant]
Xie Qing et al “Variation-Aware Joint Optimization of the Supply Voltage and Sleep Transistor Size for 7nm FinFET Technology”; 2014 IEEE 32nd international conference on computer design, pp. 380-385, Oct. 19, 2014. doi:… [cited by applicant]
Rebaud B et al , “Timing slack monitoring under process and environmental variations: Application to a DSP performance optimization”; Microelectronics Journal vol. 42 Issue 5, pp. 718-732, Feb. 8, 2011. doi: 10.1016/j.m… [cited by applicant]
Dierickx B et al, “Propagating variability from technology to system Level”; Physics of Semiconductor Devices, pp. 74-79, Dec. 16, 2007. doi: 10.1109/IWPSD.2007.4472457. [cited by applicant]
Zheng K., “A Comparison of Digital Droop Detection Techniques in ASAP7 FinFET”; Research Review. Sep. 2019. [cited by applicant]
Hongge Chen, “Novel Machine Learning Approaches for Modeling Variations in Semiconductor Manufacturing,” Master thesis, Jun. 2017. [cited by applicant]
Nidhal Selmane, Shivam Bhasin, Sylvain Guilley, Tarik Graba, Jean-Luc Danger. “WDDL is Protected Against Setup Time Violation Attacks.” CHES, Sep. 2009, Lausanne, Switzerland. pp. 73-83. doi: 10.1109/FDTC.2009.40. [cited by applicant]
Nidhal Selmane, Shivam Bhasin, Sylvain Guilley, Jean-Luc Danger. “Security evaluation of application-specific integrated circuits and field programmable gate arrays against setup time violation attacks.” IET Inf. Secur.… [cited by applicant]
Jianfeng Zhang et al, “Parameter Variation Sensing and Estimation in Nanoscale Fabrics”; Journal of Parallel and Distributed Computing; vol. 74, Issue 6, pp. 2504-2511, Jun. 1, 2014. https://doi.org/10.1016/j.jpdc.2013.… [cited by applicant]
I. A. K. M. Mahfuzul et al, “Variation-sensitive monitor circuits for estimation of Die-to-Die process variation”; 2011 IEEE ICMTS International Conference on Microelectronic Test Structures; pp. 153-157, Apr. 4-7, 2011… [cited by applicant]
Ying Qiao et al, “Variability-aware compact modeling and statistical circuit validation on SRAM test array”; Proceedings vol. 9781, Design-Process-Technology Co-optimization for Manufacturability X, Mar. 16, 2016. https… [cited by applicant]
David Herres, “The Eye Diagram: What is it and why is it used?”; Online at: https://www.testandmeasurementtips.com/basics-eye-diagrams/, Aug. 16, 2016. [cited by applicant]
Yu-Chuan Lin et al, “A 10-GB/s Eye-Opening Monitor Circuit for Receiver Equalizer Adaptations in 65-nm CMOS;” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, No. 1, pp. 23-34, Jan. 2020. do… [cited by applicant]
PCT International Search Report for International Application No. PCT/IL2019/050433, mailed Aug. 28, 2019, 6pp. [cited by applicant]
PCT Written Opinion for International Application No. PCT/IL2019/050433, mailed Aug. 28, 2019, 5pp. [cited by applicant]
PCT International Preliminary Report on Patentability for International Application No. PCT/IL2019/050433, issued Oct. 20, 2020, 6pp. [cited by applicant]