Patent Assignment
Reel/Frame 036293/0932
Assignment of Assignor's Interest
Recorded: 2015-08-06
Pages: 10
Assignor
INFINEON TECHNOLOGIES AG
Executed: 2015-07-08
Assignee
POLARIS INNOVATIONS LIMITED
29 EARLSFORT TERRACE, DUBLIN 2, DUBLIN, IRELAND
Covered Properties
(107)
Flexible Fuse Placement in Redunant Semiconductor Memory
Patent:
5,859,801 →
Application:
08/825,312 →
Method for Forming a Structure
Patent:
5,926,716 →
Application:
08/829,255 →
Method for Forming Metallization in Semiconductor Devices with a Self- Planarizing Material
Patent:
5,854,126 →
Application:
08/829,257 →
Device with Asymmetrical Channel Dopant Profile
Patent:
6,025,224 →
Application:
08/829,371 →
Etching of Contact Holes
Patent:
6,025,116 →
Application:
08/829,575 →
Method of Planarizing the Semiconductor Structure
Patent:
5,963,837 →
Application:
08/846,924 →
Integrated Circuits and Manufacturing Methods
Patent:
6,492,282 →
Application:
08/846,925 →
Method for Forming a Capacitar
Patent:
6,001,684 →
Application:
08/868,555 →
Improved Redundant Circuits and Methods Therefor
Patent:
5,831,916 →
Application:
08/879,726 →
Method of Reducing the Formation of Watermarks on Semiconductor Wafers
Patent:
6,074,935 →
Application:
08/882,057 →
Integrated Circuit Devices Including Shallow Trench Isolation
Patent:
5,783,476 →
Application:
08/883,356 →
Improved Chemical Mechanical Polishing Pad Conditioner
Patent:
5,885,137 →
Application:
08/884,118 →
Mitigation of Cmp-Induced Bpsg Surface Damage by an Integrated Anneal and Silicon Dioxide Deposition
Patent:
5,915,175 →
Application:
08/884,119 →
Improved Dual Damascene Structure
Patent:
6,033,977 →
Application:
08/884,729 →
Formation of Sub-Groundrule Features
Patent:
6,051,497 →
Application:
08/884,732 →
Techniques for Reducing Redundant Element Fuses in a Dynamic Random Access Memory Array
Patent:
5,831,917 →
Application:
08/884,854 →
Dynamic Access Memory Equalizer Circuits and Methods Therefor
Patent:
5,875,138 →
Application:
08/884,855 →
Cmos Integrated Circuits with Reduced Substrate Defects
Patent:
5,937,288 →
Application:
08/884,860 →
Method of Forming Multi-Level Coplanar Metal/Insulator Films Using Dual Damascene with Sacrificial Flowable Oxide
Patent:
6,300,235 →
Application:
08/884,861 →
Ocd with Low Output Capacitance
Patent:
5,889,420 →
Application:
08/885,329 →
Method of Manufacturing a Semiconductor Structure Having a Crystalline Layer
Patent:
5,966,624 →
Application:
08/901,986 →
Temperature Independent Oscillator
Patent:
5,870,345 →
Application:
08/923,300 →
Dimension Programmable Fusebanks and Methods for Making the Same
Patent:
5,835,425 →
Application:
08/923,459 →
Apparatus and Method for High-Speed Wordline Driving with Low Area Overhead
Patent:
6,034,913 →
Application:
08/932,925 →
Semiconductor Memory Having Redundancy Circuit
Patent:
6,078,534 →
Application:
08/937,570 →
A Method and Apparatus for Reducing the Bias Current in a Reference Voltage Circuit
Patent:
5,959,471 →
Application:
08/937,571 →
Method of Maximizing Chip Yield for Semiconductor Wafers
Patent:
6,070,004 →
Application:
08/937,764 →
Method of Fabricating Semiconductor Chips with Silicide and Implanted Junctions
Patent:
6,136,677 →
Application:
08/937,781 →
Metalization System Having an Enhanced Thermal Conductivity
Patent:
6,046,503 →
Application:
08/938,072 →
Deposition of Carbon into Nitride Layer for Improved Selectivity of Oxide to Nitride Etchrate for Self Aligned Contact Etching
Patent:
5,935,873 →
Application:
08/939,148 →
Multi-Level Conductive Structure Including Low Capacitance Material
Patent:
5,977,635 →
Application:
08/939,208 →
Apparatus and Method for Implementing a Bank Interlock Scheme and Related Test Mode for Multibank Memory Devices
Patent:
5,959,911 →
Application:
08/939,546 →
Methods for Performing Planarization and Recess Etches and Apparatus Therefor
Patent:
6,232,233 →
Application:
08/940,806 →
Space-Efficient Semiconductor Memory Having Hierarchical Column Select Line Architecture
Patent:
5,923,605 →
Application:
08/940,861 →
Constant Current Cmos Output Driver Circuit with Dual Gate Transistor Devices
Patent:
5,939,937 →
Application:
08/940,862 →
Endpoint Detection Method and Apparatus
Patent:
5,955,380 →
Application:
08/941,093 →
Reducing Oxidation Stress in the Fabrication of Devices
Patent:
5,867,420 →
Application:
08/943,910 →
Control of Critical Dimensions Through Measurement of Abosrbed Radiation
Patent:
6,063,530 →
Application:
08/999,926 →
Method for Producing a Cmos Circuit
Patent:
5,913,115 →
Application:
09/067,766 →
Dram Cell Configuration and Method for Its Production
Patent:
6,255,684 →
Application:
09/071,798 →
Integrated Circuit Having at Least Two Vertical Mos Transistors and Method for Manufacturing Same
Patent:
6,376,313 →
Application:
09/079,020 →
Dram Cell Arrangement Having Dynamic Self-Amplifying Memory Cells, and Method for Manufacturing Same
Patent:
6,049,105 →
Application:
09/089,539 →
Dram Cell Configuration and Method for Its Fabrication
Patent:
6,087,692 →
Application:
09/093,572 →
Circuit Configuration for Generating Digital Signals
Patent:
6,064,228 →
Application:
09/095,261 →
Method of Producing a Barrier Layer in a Semiconductor Body
Patent:
6,100,187 →
Application:
09/106,237 →
Redundancy Circuit for Semiconductor Memories
Patent:
6,188,617 →
Application:
09/115,618 →
Configuration for the Automatic Inscription or Reinscription of Wafers
Patent:
6,147,321 →
Application:
09/128,387 →
Structuring Process
Patent:
6,296,777 →
Application:
09/128,388 →
Structuring Method
Patent:
6,454,956 →
Application:
09/128,389 →
Databus
Patent:
6,060,908 →
Application:
09/128,806 →
Method and Circuit Configuration for Processing Digital Signals
Patent:
6,445,753 →
Application:
09/128,807 →
Circuit Apparatus for Evaluating the Data Content of Memory Cells
Patent:
6,097,650 →
Application:
09/133,704 →
Semiconductor Component and Method for Testing and Operating a Semiconductor Component
Patent:
6,313,655 →
Application:
09/133,893 →
Circuit Arrangement with at Least Four Transistors, and Method for the Manufacture Thereof
Patent:
6,060,911 →
Application:
09/138,160 →
Dram Cell Arrangement and Method for the Manufacture Thereof
Patent:
6,172,391 →
Application:
09/140,972 →
Fuse Configuration for a Semiconductor Storage Device
Patent:
6,180,992 →
Application:
09/143,122 →
Structuring Method
Patent:
6,315,913 →
Application:
09/146,636 →
Method for Producing Structures Having a High Aspect Ratio and Structure Having a High Aspect Ratio
Patent:
6,210,595 →
Application:
09/149,829 →
Level Converting Circuit
Patent:
5,994,944 →
Application:
09/150,789 →
Circuit Configuration for Reducing Disturbances Due to a Switching of an Output Driver
Patent:
6,069,486 →
Application:
09/160,851 →
Pulse Shaper Circuit
Patent:
6,043,691 →
Application:
09/160,862 →
O-Amino (Thio) Phenolcarboxylic Acids and Their Preparation
Patent:
5,998,662 →
Application:
09/160,875 →
Rs Flip-Flop with Enable Inputs
Patent:
5,994,936 →
Application:
09/160,880 →
Bis-O-Amino(Thio)Phenols, and Their Preparation
Patent:
6,150,558 →
Application:
09/161,144 →
O-Amino (Thio) Phenolcarboxylic Acids, and Their Preparation
Patent:
6,310,238 →
Application:
09/161,147 →
Polybenzoxazole and Polybenzothiazole Precursors
Patent:
6,153,350 →
Application:
09/161,148 →
O-Nitro(Thio)Phenol Derivatives, and Their Preparation
Patent:
6,320,081 →
Application:
09/161,149 →
Polybenzoxazole and Polybenzothiazole Precursors
Patent:
6,120,970 →
Application:
09/161,202 →
Bis-O-Amino (Thio) Phenols, and Their Preparation
Patent:
6,156,902 →
Application:
09/161,549 →
Associative Memory and Method for the Operation Thereof
Patent:
6,160,729 →
Application:
09/162,608 →
Method for the Linear Configuration of Metallic Fuse Sections on Wafers
Patent:
6,698,086 →
Application:
09/163,874 →
Process for Producing a Ceramic Layer
Patent:
6,156,673 →
Application:
09/164,115 →
Process for Producing a Ceramic Layer Containing Bi
Patent:
6,126,998 →
Application:
09/164,119 →
Integrated Circuit Configuration Having at Least One Capacitor and Method for Producing the Same
Patent:
6,441,424 →
Application:
09/176,558 →
Dram Cell Arrangement and Method for the Production Thereof
Patent:
5,977,589 →
Application:
09/191,482 →
Microstructure and Methods for Fabricating Such Structure
Patent:
6,015,988 →
Application:
09/197,391 →
Sram Cell Configuration and Method for Its Fabrication
Patent:
6,038,164 →
Application:
09/200,071 →
Chemically Amplified Resist
Patent:
6,171,755 →
Application:
09/201,728 →
Memory Cell Using Amorphous Material to Stabilize the Boundary Face Between Polychrystalline Semiconductor Material of a Capacitor and Moncrystalline Semiconductor Material of a Transistor
Patent:
6,583,464 →
Application:
09/201,733 →
Device with Asymmetrical Channel Dopant Profile
Patent:
6,355,954 →
Application:
09/251,616 →
Reduced Signal Test for Dynamic Random Access Memory
Patent:
6,453,433 →
Application:
09/281,021 →
O-Amino(Thio) Phenolcarboxylic Acids, and Their Preparation
Patent:
6,096,921 →
Application:
09/388,274 →
Integrated Cmos Circuit Configuration, and Production of Same
Patent:
6,518,628 →
Application:
09/423,864 →
Backing Film for Chemical Mechanical Planarization (Cmp) of a Semiconductor Wafer
Patent:
6,371,833 →
Application:
09/438,305 →
Input Circuit for an Integrated Circuit
Patent:
6,137,314 →
Application:
09/450,403 →
Integrated Circuit Arrangement and Method for the Manufacture Thereof
Patent:
6,913,983 →
Application:
09/462,994 →
Configuration of Memory Cells and Method of Checking the Operation of Memory Cells
Patent:
6,279,129 →
Application:
09/465,726 →
Semiconductor Circuit Apparatus and Method for Fabricating the Semiconductor Circuit Apparatus
Patent:
6,310,396 →
Application:
09/472,221 →
Method of producing a vertical mos transistor
Patent:
6,337,247 →
Application:
09/487,411 →
Polishing Agent for Semiconductor Substrates
Patent:
6,447,372 →
Application:
09/491,296 →
Read-Only Memory and Fabrication Method
Patent:
6,303,474 →
Application:
09/494,775 →
Wafer marking
Patent:
6,261,382 →
Application:
09/495,795 →
Integrated electrical circuit with passivation layer
Patent:
6,395,454 →
Application:
09/498,532 →
Digital circuit having a filter unit for suppressing glitches
Patent:
6,389,086 →
Application:
09/521,396 →
Memory Cell Configuration, Magnetic Ram, and Associative Memory
Patent:
6,490,190 →
Application:
09/528,159 →
Memory Cell Configuration and Fabrication Method
Patent:
6,417,043 →
Application:
09/528,268 →
Dynamic memory having two modes of operation
Patent:
6,191,985 →
Application:
09/528,424 →
Digital memory and method of operation for a digital memory
Patent:
6,208,562 →
Application:
09/536,029 →
Product Including a Silicon-Containing Functional Layer and an Insulating Layer Made of Silicon Dioxide, and Method Fabricating the Product
Patent:
6,410,407 →
Application:
09/539,235 →
Method of Producing an Open Form
Patent:
6,468,348 →
Application:
09/539,237 →
Method for testing bus connections of writable and readable integrated electronic circuits, in particular memory components
Patent:
6,345,372 →
Application:
09/547,683 →
Buffer circuit
Patent:
6,317,378 →
Application:
09/592,225 →
Integrated Memory with a Buffer Circuit
Patent:
6,426,899 →
Application:
09/594,911 →
Method of programming a semiconductor memory
Method for the Production of a Dram Cell Configuration
Patent:
6,420,228 →
Application:
09/851,051 →
O-Aminophenolcarboxylic Acid and O-Aminothiophenolcarboxylic Acid
Integrated Circuit Having at Least Two Vertical Mos Transistors and Method for Manufacturing Same
Related Assignments
(4)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Jan 12, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023768/0001 →
Assignment of Assignor's Interest
Jan 13, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023773/0001 →
Assignment of Assignor's Interest
Feb 22, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023963/0502 →
Assignment of Assignor's Interest
May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →