Bonded structure including a first microelectronic device direct hybrid bonded to a second microelectronic device
Layer structures for making direct metal-to-metal bonds at low temperatures and shorter annealing durations in microelectronics are provided. Example bonding interface structures enable direct metal-to-metal bonding of interconnects at low annealing temperatures of 150° C. or below, and at a lower energy budget. The example structures provide a precise metal recess distance for conductive pads and vias being bonded that can be achieved in high volume manufacturing. The example structures provide a vertical stack of conductive layers under the bonding interface, with geometries and thermal expansion features designed to vertically expand the stack at lower temperatures over the precise recess distance to make the direct metal-to-metal bonds. Further enhancements, such as surface nanotexture and copper crystal plane selection, can further actuate the direct metal-to-metal bonding at lowered annealing temperatures and shorter annealing durations.
1 . A bonded structure comprising:
a first microelectronic device comprising:
a semiconductor layer;
a first dielectric structure over the semiconductor layer, an upper surface of the first dielectric structure forming a portion of a first bonding surface of the first microelectronic device;
a buried conductive layer embedded in the first dielectric structure over the semiconductor layer, the buried conductive layer having a first horizontal dimension and a first thickness;
a buried conductive via portion embedded in the first dielectric structure over and electrically connected to the buried conductive layer, the buried conductive via portion having a second horizontal dimension less than the first horizontal dimension and a second thickness greater than the second horizontal dimension; and
a conductive contact pad portion over and extending from the buried conductive via portion, wherein the conductive contact pad portion is embedded in and surrounded by the first dielectric structure, wherein the first bonding surface comprises an upper surface of the conductive contact pad portion, wherein the conductive contact pad portion has a third horizontal dimension and a third thickness, wherein the third horizontal dimension is greater than the second horizontal dimension and less than the first horizontal dimension, wherein the third thickness is greater than 0.5 μm, wherein only a single via portion comprising the buried conductive via portion connects to the conductive contact pad portion, the single via portion comprising the buried conductive via portion; and
a second microelectronic device direct hybrid bonded to the first bonding surface without adhesive along a bond interface.
2 . The bonded structure of claim 1 , wherein the third thickness is in a range of 0.6-2 μm.
3 . The bonded structure of claim 1 , wherein the first thickness is in a range of 0.5-1.5 μm.
4 . The bonded structure of claim 3 , wherein the first thickness is in a range of 0.5-1 μm.
5 . The bonded structure of claim 1 , wherein the first dielectric structure comprises a plurality of dielectric layers of a back-end-of-line (BEOL) stack.
6 . The bonded structure of claim 1 , wherein the first dielectric structure comprises silicon oxide.
7 . The bonded structure of claim 1 , wherein a surface of the conductive contact pad portion comprises nanotwinned copper.
8 . The bonded structure of claim 1 , wherein a surface of the conductive contact pad portion comprises copper metal with lattice planes possessing mostly 111 Miller indices oriented for diffusion of copper atoms across the bond interface.
9 . The bonded structure of claim 1 , wherein at least the upper surface of the conductive contact pad portion comprises a nanotexture surface for formation of direct metal-to-metal bonds at an annealing temperature of 150° C. or less.
10 . The bonded structure of claim 9 , wherein the nanotexture surface comprises a hexagonal network of screw dislocations in copper metal.
11 . The bonded structure of claim 1 , wherein the buried conductive layer comprises an aluminum metal.
12 . The bonded structure of claim 11 , wherein the buried conductive via portion comprises a copper metal.
13 . The bonded structure of claim 11 , wherein the buried conductive layer comprises an aluminum alloy.
14 . The bonded structure of claim 1 , wherein, as seen in a side cross-section, the third horizontal dimension is 2 μm.
15 . A bonded structure comprising:
a first microelectronic device comprising:
a semiconductor layer;
a first dielectric structure over the semiconductor layer, an upper surface of the first dielectric structure forming a portion of a first bonding surface of the first microelectronic device;
a buried conductive layer embedded in the first dielectric structure over the semiconductor layer, the buried conductive layer having a first horizontal dimension and a first thickness in a range of 0.5-1.5 μm;
a buried conductive via portion embedded in the first dielectric structure over and electrically connected to the buried conductive layer, the buried conductive via portion having a second horizontal dimension less than the first horizontal dimension and a second thickness greater than the second horizontal dimension; and
a conductive contact pad portion over and extending from the buried conductive via portion, wherein the conductive contact pad portion is embedded in and surrounded by the first dielectric structure, the first bonding surface comprising an upper surface of the conductive contact pad portion, the conductive contact pad portion having a third horizontal dimension greater than the second horizontal dimension and less than the first horizontal dimension, the conductive contact pad portion having a third thickness in a range of 0.6-2 μm;
a second microelectronic device direct hybrid bonded to the first bonding surface without adhesive along a bond interface; and
a second conductive contact pad portion spaced apart from the conductive contact pad portion, the second conductive contact pad portion disposed over a second buried conductive via portion, wherein the second buried conductive via portion is a nearest conductive via to the buried conductive via portion.
16 . The bonded structure of claim 15 , wherein the first dielectric structure comprises a plurality of dielectric layers.
17 . The bonded structure of claim 16 , wherein the first dielectric structure comprises silicon oxide.
18 . The bonded structure of claim 15 , wherein a surface of the buried conductive contact pad portion comprises nanotwinned copper.
19 . The bonded structure of claim 15 , wherein a surface of the buried conductive contact pad portion comprises copper metal with lattice planes possessing mostly 111 Miller indices oriented for diffusion of copper atoms across the bond interface.
20 . The bonded structure of claim 15 , wherein the buried conductive layer comprises an aluminum metal.
21 . The bonded structure of claim 20 , wherein the buried conductive via portion comprises a copper metal.
22 . The bonded structure of claim 20 , wherein the buried conductive layer comprises an aluminum alloy.
23 . The bonded structure of claim 15 , wherein, as seen in a side cross-section, the third horizontal dimension is 2 μm.
24 . A bonded structure comprising:
a first microelectronic device comprising:
a semiconductor layer;
a first dielectric structure over the semiconductor layer, an upper surface of the first dielectric structure forming a portion of a bonding surface of the first microelectronic device;
a buried conductive layer embedded in the first dielectric structure over the semiconductor layer, the buried conductive layer having a first horizontal dimension and a thickness in a range of 0.5-1.5 μm;
a buried conductive via portion embedded in the first dielectric structure over and electrically connected to the buried conductive layer, wherein the buried conductive via portion has a second horizontal dimension less than the first horizontal dimension; and
a conductive contact pad portion over and extending from the buried conductive via portion, wherein the conductive contact pad portion is embedded in and surrounded by the first dielectric structure, the bonding surface comprising an upper surface of the conductive contact pad portion, the conductive contact pad portion having a third horizontal dimension greater than the second horizontal dimension and less than the first horizontal dimension, wherein only a single via portion comprising the buried conductive via portion connects to the conductive contact pad portion, the single via portion comprising the buried conductive via portion; and
a second microelectronic device direct hybrid bonded to the bonding surface without adhesive along a bond interface.
25 . The bonded structure of claim 24 , wherein the conductive contact pad portion has a second thickness greater than 0.5 μm.
26 . The bonded structure of claim 25 , wherein the second thickness of the conductive pad portion is in a range of 0.6-2 μm.
27 . The bonded structure of claim 24 , wherein the buried conductive via portion has a second thickness that is greater than the second horizontal dimension.
28 . The bonded structure of claim 24 , wherein the first dielectric structure comprises a plurality of dielectric layers of a back-end-of-line (BEOL) stack.
29 . The bonded structure of claim 24 , wherein the first dielectric structure comprises silicon oxide.
30 . The bonded structure of claim 24 , wherein the buried conductive via portion comprises copper metal.
31 . The bonded structure of claim 24 , wherein the buried conductive layer comprises copper.
32 . The bonded structure of claim 24 , wherein, as seen in a side cross-section, the third horizontal dimension is 2 μm.