Vertical interconnect elevator based on through silicon vias
A chip package includes a first integrated-circuit (IC) chip; a second integrated-circuit (IC) chip over the first integrated-circuit (IC) chip; a connector over the first integrated-circuit (IC) chip and on a same horizontal level as the second integrated-circuit (IC) chip, wherein the connector comprises a substrate over the first integrated-circuit (IC) chip and a plurality of through vias vertically extending through the substrate of the connector; a polymer layer over the first integrated-circuit (IC) chip, wherein the polymer layer has a portion between the second integrated-circuit (IC) chip and connector, wherein the polymer layer has a top surface coplanar with a top surface of the second integrated-circuit (IC) chip, a top surface of the substrate of the connector and a top surface of each of the plurality of through vias; and an interconnection scheme on the top surface of the polymer layer, the top surface of the second integrated-circuit (IC) chip, the top surface of the connector and the top surface of each of the plurality of through vias.
1. A multichip package comprising:
an interposer comprising a first silicon substrate, a first through-silicon via vertically in the first silicon substrate and a first interconnection scheme over the first silicon substrate;
a first metal bump at a bottom of the multichip package, under the interposer and coupling to the first through-silicon via;
a stacked chip package over the interposer and coupling to the interposer, wherein the stacked chip package comprises:
an element over the interposer, wherein the element comprises a second silicon substrate, a first insulating bonding layer over the second silicon substrate and at a top of the element and a first copper pad over the second silicon substrate and at the top of the element and in a first opening in the first insulating bonding layer, wherein the first insulating bonding layer comprises silicon,
a second metal bump between the element and interposer and coupling the element to the interposer, and
a first integrated-circuit (IC) chip on the element, wherein the first integrated-circuit (IC) chip comprises a second insulating bonding layer at a bottom of the first integrated-circuit (IC) chip and a second copper pad at the bottom of the first integrated-circuit (IC) chip and in an opening in the second insulating bonding layer, wherein the second copper pad has a bottom surface bonded to and in contact with a top surface of the first copper pad and the second insulating bonding layer has a bottom surface bonded to and in contact with a top surface of the first insulating bonding layer, wherein the second insulating bonding layer comprises silicon;
a second integrated-circuit (IC) chip over the interposer and at a same horizontal level as the stacked chip package, wherein the second integrated-circuit (IC) chip couples to the stacked chip package through the first interconnection scheme; and
a third metal bump between the second integrated-circuit (IC) chip and interposer, wherein the third metal bump has a top joining a bottom of the second integrated-circuit (IC) chip and a bottom joining a top of the interposer.
2. The multichip package of claim 1 , wherein the element comprises a third integrated-circuit (IC) chip comprising the second silicon substrate therein and a second through-silicon via vertically in the second silicon substrate.
3. The multichip package of claim 2 , wherein the second through-silicon via comprises a copper layer in an opening in the second silicon substrate and an adhesion metal layer at a sidewall of the copper layer.
4. The multichip package of claim 2 , wherein the first copper pad is vertically over and aligned with the second through-silicon via.
5. The multichip package of claim 2 , wherein the second metal bump is vertically under and aligned with the second through-silicon via.
6. The multichip package of claim 2 , wherein the third integrated-circuit (IC) chip further comprises an adhesion metal layer having a first portion at a bottom of the first copper pad and a second portion at a sidewall of the first copper pad.
7. The multichip package of claim 1 , wherein the first integrated-circuit (IC) chip further comprises a third silicon substrate, a transistor at a bottom of the third silicon substrate and a second interconnection scheme under the third silicon substrate, wherein the second insulating bonding layer is under the second interconnection scheme and the second copper pad is under and couples to the second interconnection scheme.
8. The multichip package of claim 1 , wherein the first integrated-circuit (IC) chip further comprises a first adhesion metal layer having a first portion at a top of the second copper pad and a second portion at a sidewall of the second copper pad.
9. The multichip package of claim 8 , wherein the first integrated-circuit (IC) chip further comprises a third silicon substrate, a transistor at a bottom of the third silicon substrate and an interconnection metal layer under the third silicon substrate, wherein the interconnection metal layer comprises a copper layer and a second adhesion metal layer having a first portion at a top of the copper layer and a second portion at a sidewall of the copper layer, wherein the first portion of the first adhesion metal layer is between the copper layer of the interconnection metal layer and the second copper pad and under and in contact with the copper layer of the interconnection metal layer.
10. The multichip package of claim 1 , wherein the first through-silicon via comprises a copper layer in an opening in the first silicon substrate and an adhesion metal layer at a sidewall of the copper layer.
11. The multichip package of claim 1 , wherein the stacked chip package further comprises a sealing layer having a first portion and a second portion opposite to the first portion of the sealing layer, wherein the element comprises a third integrated-circuit (IC) chip comprising the second silicon substrate therein, wherein the third integrated-circuit (IC) chip is, in a horizontal direction, between the first and second portions of the sealing layer, wherein the first portion of the sealing layer extends from a left sidewall of the third integrated-circuit (IC) chip and has a right sidewall in contact with the left sidewall of the third integrated-circuit (IC) chip and a left sidewall opposite to the right sidewall of the first portion of the sealing layer, wherein the left sidewall of the first portion of the sealing layer is at a left edge of the sealing layer, wherein the left sidewall of the first portion of the sealing layer extends in a vertical direction.
12. The multichip package of claim 11 , wherein the first integrated-circuit (IC) chip has a left sidewall recessed from the left sidewall of the first portion of the sealing layer.
13. The multichip package of claim 11 , wherein the first integrated-circuit (IC) chip has a left sidewall recessed from the left sidewall of the third integrated-circuit (IC) chip and a right sidewall opposite to the left sidewall of the first integrated-circuit (IC) chip and recessed from a right sidewall of the third integrated-circuit (IC) chip, wherein the right sidewall of the third integrated-circuit (IC) chip is opposite to the left sidewall of the third integrated-circuit (IC) chip.
14. The multichip package of claim 1 , wherein the stacked chip package further comprises a third integrated-circuit (IC) chip on the element and at a same horizontal level as the first integrated-circuit (IC) chip, wherein the element further comprises a third copper pad at the top of the element and in a second opening in the first insulating bonding layer, wherein the third integrated-circuit (IC) chip comprises a third insulating bonding layer at a bottom of the third integrated-circuit (IC) chip and a fourth copper pad at the bottom of the third integrated-circuit (IC) chip and in an opening in the third insulating bonding layer, wherein the fourth copper pad has a bottom surface bonded to and in contact with a top surface of the third copper pad and the third insulating bonding layer has a bottom surface bonded to and in contact with the top surface of the first insulating bonding layer, wherein the third insulating bonding layer comprises silicon.
15. The multichip package of claim 1 , wherein the second insulating bonding layer has a thickness between 0.1 and 2 micrometers.
16. The multichip package of claim 1 , wherein the second metal bump comprises tin.
17. The multichip package of claim 1 , wherein the first integrated-circuit (IC) chip is a logic chip.
18. The multichip package of claim 1 , wherein the first integrated-circuit (IC) chip is a graphic-processing-unit (GPU) integrated-circuit (IC) chip.
19. The multichip package of claim 1 , wherein the first integrated-circuit (IC) chip is a central-processing-unit (CPU) integrated-circuit (IC) chip.
20. The multichip package of claim 1 , wherein the first integrated-circuit (IC) chip is a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip.
21. The multichip package of claim 1 , wherein the element comprises a memory chip.
22. The multichip package of claim 1 , wherein the element comprises an input/output (I/O) chip.
23. The multichip package of claim 1 , wherein the element comprises a memory chip and the first integrated-circuit (IC) chip is a logic chip.
24. The multichip package of claim 1 , wherein the element comprises an input/output (I/O) chip and the first integrated-circuit (IC) chip is a logic chip.
25. The multichip package of claim 1 , wherein the second integrated-circuit (IC) chip is a memory chip.
26. The multichip package of claim 1 , wherein the element comprises a third integrated-circuit (IC) chip comprising the second silicon substrate, a transistor at a top of the second silicon substrate, a second through-silicon via vertically in the second silicon substrate, a second interconnection scheme over the second silicon substrate, the first insulating bonding layer over the second interconnection scheme and the first copper pad over and coupling to the second interconnection scheme.
27. The multichip package of claim 1 , wherein the element further comprises a transistor at a top of the second silicon substrate, a second through-silicon via vertically in the second silicon substrate and a second interconnection scheme over the second silicon substrate, wherein the first insulating bonding layer is over the second interconnection scheme and the first copper pad is over and couples to the second interconnection scheme.
28. The multichip package of claim 1 , wherein the stacked chip package further comprises a sealing layer having a first portion and a second portion opposite to the first portion of the sealing layer, wherein the first integrated-circuit (IC) chip is, in a horizontal direction, between the first and second portions of the sealing layer, wherein the first portion of the sealing layer extends from a left sidewall of the first integrated-circuit (IC) chip and has a right sidewall in contact with the left sidewall of the first integrated-circuit (IC) chip and a left sidewall opposite to the right sidewall of the first portion of the sealing layer, wherein the left sidewall of the first portion of the sealing layer is at a left edge of the sealing layer, wherein the left sidewall of the first portion of the sealing layer extends in a vertical direction.
29. The multichip package of claim 28 , wherein the sealing layer comprises a molding compound.