Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells
A field-programmable-gate-array (FPGA) IC chip includes multiple first non-volatile memory cells in the FPGA IC chip, wherein the first non-volatile memory cells are configured to save multiple resulting values for a look-up table (LUT) of a programmable logic block of the FPGA IC chip, wherein the programmable logic block is configured to select, in accordance with its inputs, one from the resulting values into its output; and multiple second non-volatile memory cells in the FPGA IC chip, wherein the second non-volatile memory cells are configured to save multiple programming codes configured to control a switch of the FPGA IC chip.
1. A chip package comprising:
a first semiconductor integrated-circuit (IC) chip comprising a silicon substrate, a transistor at a top of the silicon substrate, a memory cell for storing first data therein, a first and a second metal interconnect and a switch having a first node coupling to the first metal interconnect, a second node coupling to the second metal interconnect and a third node coupling to the memory cell, wherein second data at the third node is associated with the first data stored in the memory cell, wherein the first semiconductor integrated-circuit (IC) chip further comprises a first input/output (I/O) circuit coupling to the second node of the switch through the second metal interconnect;
a third metal interconnect over the first semiconductor integrated-circuit (IC) chip and coupling to the first input/output (I/O) circuit of the first semiconductor integrated-circuit (IC) chip, wherein the switch is configured for programmable interconnection between the first and third metal interconnects by controlling, in accordance with the second data, pass or no-pass of data between the first and third metal interconnects; and
a second semiconductor integrated-circuit (IC) chip over the first semiconductor integrated-circuit (IC) chip and across an edge of the first semiconductor integrated-circuit (IC) chip, wherein the second semiconductor integrated-circuit (IC) chip has an active surface facing the first semiconductor integrated-circuit (IC) chip, wherein the edge of the first semiconductor integrated-circuit (IC) chip is recessed from an edge of the second semiconductor integrated-circuit (IC) chip, wherein the second semiconductor integrated-circuit (IC) chip comprises a plurality of first metal contacts at a bottom thereof and coupling to the first semiconductor integrated-circuit (IC) chip.
2. The chip package of claim 1 , wherein the first input/output (I/O) circuit has an input capacitance smaller than 1 pF.
3. The chip package of claim 1 , wherein the first semiconductor integrated-circuit (IC) chip further comprises a second metal contact at a top thereof and coupling to one of the plurality of first metal contacts.
4. The chip package of claim 3 , wherein the second metal contact is vertically under said one of the first metal contacts.
5. The chip package of claim 3 , wherein the second metal contact comprises a copper layer.
6. The chip package of claim 1 further comprising an interconnection scheme over the first semiconductor integrated-circuit (IC) chip and across the edge of the first semiconductor integrated-circuit (IC) chip, wherein the edge of the first semiconductor integrated-circuit (IC) chip is recessed from an edge of the interconnection scheme, wherein the interconnection scheme comprises the third metal interconnect therein, wherein the second semiconductor integrated-circuit (IC) chip is over the interconnection scheme and each of the plurality of first metal contacts is bonded to and in contact with a top of the interconnection scheme and couples to the first semiconductor integrated-circuit (IC) chip through the interconnection scheme.
7. The chip package of claim 6 , wherein the first semiconductor integrated-circuit (IC) chip further comprises a second metal contact at a top thereof joining and in contact with the interconnection scheme, wherein the interconnection scheme comprises an interconnection metal layer over the first semiconductor integrated-circuit (IC) chip, across the edge of the first semiconductor integrated-circuit (IC) chip and in contact with the second metal contact.
8. The chip package of claim 7 , wherein the second metal contact is vertically under one of the plurality of first metal contacts.
9. The chip package of claim 7 , wherein the second metal contact comprises a copper layer.
10. The chip package of claim 7 , wherein the interconnection metal layer comprises a copper layer having a thickness between 1 and 10 micrometers.
11. The chip package of claim 6 , wherein the interconnection scheme comprises a first interconnection metal layer over the first semiconductor integrated-circuit (IC) chip and across the edge of the first semiconductor integrated-circuit (IC) chip, a second interconnection metal layer over the first interconnection metal layer and an insulating dielectric layer between the first and second interconnection metal layers.
12. The chip package of claim 6 further comprising a third semiconductor integrated-circuit (IC) chip over the interconnection scheme and at a same first horizontal level as the second semiconductor integrated-circuit (IC) chip, wherein the third semiconductor integrated-circuit (IC) chip comprises a plurality of second metal contacts each at a bottom thereof, at a same second horizontal level as the plurality of first metal contacts and bonded to and in contact with the top of the interconnection scheme.
13. The chip package of claim 12 , wherein each of the plurality of first and second metal contacts comprises tin.
14. The chip package of claim 12 , wherein each of the plurality of first and second metal contacts comprises a copper layer.
15. The chip package of claim 12 further comprising a molded polymer in a space over the interconnection scheme, at the same first horizontal level as the second and third semiconductor integrated-circuit (IC) chips and beyond a sidewall of each of the second and third semiconductor integrated-circuit (IC) chips.
16. The chip package of claim 1 , wherein each of the plurality of first metal contacts is a metal bump at the bottom of the second semiconductor integrated-circuit (IC) chip.
17. The chip package of claim 1 further comprising an underfill between the first and second semiconductor integrated-circuit (IC) chips and in contact with a sidewall of each of the plurality of first metal contacts.
18. The chip package of claim 1 further comprising a sealing layer in a space at a same horizontal level as the first semiconductor integrated-circuit (IC) chip and beyond a sidewall of the first semiconductor integrated-circuit (IC) chip.
19. The chip package of claim 18 , wherein the sealing layer comprises a molding compound.
20. The chip package of claim 18 further comprising a first interconnection scheme over the first semiconductor integrated-circuit (IC) chip and sealing layer, wherein the first interconnection scheme comprises the third metal interconnect therein, wherein the second semiconductor integrated-circuit (IC) chip is over the first interconnection scheme, wherein each of the plurality of first metal contacts is bonded to and in contact with a top of the first interconnection scheme and couples to the first semiconductor integrated-circuit (IC) chip through the first interconnection scheme.
21. The chip package of claim 20 further comprising a metal pillar vertically in the sealing layer, at the same second horizontal level as the sealing layer and first semiconductor integrated-circuit (IC) chip and under and coupling to the first interconnection scheme.
22. The chip package of claim 21 , wherein the second semiconductor integrated-circuit (IC) chip couples to the metal pillar through the first interconnection scheme.
23. The chip package of claim 21 further comprising a second interconnection scheme under the first semiconductor integrated-circuit (IC) chip, sealing layer and metal pillar and coupling to the first interconnection scheme through the metal pillar.
24. The chip package of claim 21 , wherein the metal pillar comprises a copper layer having a thickness between 5 and 300 micrometers.
25. The chip package of claim 1 further comprising a first interconnection scheme over the first semiconductor integrated-circuit (IC) chip and across the edge of the first semiconductor integrated-circuit (IC) chip, wherein the first interconnection scheme comprises a first metal line for use as the third metal interconnect therein, wherein the second semiconductor integrated-circuit (IC) chip is over the first interconnection scheme, wherein each of the plurality of first metal contacts of the second semiconductor integrated-circuit (IC) chip is bonded to and in contact with a top of the first interconnection scheme and couples to the first semiconductor integrated-circuit (IC) chip through the first interconnection scheme, wherein the first semiconductor integrated-circuit (IC) chip comprises a second interconnection scheme over the silicon substrate, wherein the second interconnection scheme comprises a second metal line for use as the first metal interconnect therein and a third metal line for use as the second metal interconnect therein.
26. The chip package of claim 1 , wherein the third metal interconnect is a vertical interconnect between the first and second semiconductor integrated-circuit (IC) chips.
27. The chip package of claim 1 further comprising a fourth metal interconnect over the first semiconductor integrated-circuit (IC) chip, wherein the first semiconductor integrated-circuit (IC) chip further comprises a second input/output (I/O) circuit coupling to the first node of the switch through the first metal interconnect and coupling to the fourth metal interconnect, wherein the switch is configured for programmable interconnection between the third and fourth metal interconnects by controlling, in accordance with the second data, pass or no-pass of data between the third and fourth metal interconnects.