Logic drive based on standard commodity FPGA IC chips
A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.
1 . A chip package comprising:
a first semiconductor integrated-circuit (IC) chip comprising a memory cell for storing first data therein, a first and a second metal interconnect and a switch having a first node coupling to the first metal interconnect, a second node coupling to the second metal interconnect and a third node coupling to the memory cell, wherein second data at the third node is associated with the first data stored in the memory cell, wherein the first semiconductor integrated-circuit (IC) chip further comprises a first input/output (I/O) circuit coupling to the second node of the switch through the second metal interconnect; and
a third metal interconnect over the first semiconductor integrated-circuit (IC) chip and coupling to the first input/output (I/O) circuit of the first semiconductor integrated-circuit (IC) chip, wherein the switch is configured for programmable interconnection between the first and third metal interconnects by controlling, in accordance with the second data, pass or no-pass of data between the first and third metal interconnects.
2 . The chip package of claim 1 , wherein the third metal interconnect is a vertical interconnect.
3 . The chip package of claim 1 further comprising a fourth metal interconnect over the first semiconductor integrated-circuit (IC) chip, wherein the first semiconductor integrated-circuit (IC) chip further comprises a second input/output (I/O) circuit coupling to the first node of the switch through the first metal interconnect and coupling to the fourth metal interconnect, wherein the switch is configured for programmable interconnection between the third and fourth metal interconnects by controlling, in accordance with the second data, pass or no-pass of data between the third and fourth metal interconnects.
4 . The chip package of claim 1 , wherein the third metal interconnect extends across an edge of the first semiconductor integrated-circuit (IC) chip.
5 . The chip package of claim 1 , wherein the memory cell is a static-random-access memory (SRAM) cell.
6 . The chip package of claim 1 further comprising a metal bump at a top of the chip package, wherein the metal bump couples to the third metal interconnect, wherein the switch is configured for the metal bump to be programmable by controlling, in accordance with the second data, pass or no-pass of data between the metal bump and first metal interconnect.
7 . The chip package of claim 6 , wherein the metal bump comprises tin.
8 . The chip package of claim 6 , wherein the metal bump comprises a copper layer.
9 . The chip package of claim 6 further comprising an interconnection scheme over the first semiconductor integrated-circuit (IC) chip and across a first and a second edge of the first semiconductor integrated-circuit (IC) chip, wherein the first edge of the first semiconductor integrated-circuit (IC) chip is recessed from a first edge of the interconnection scheme and the second edge of the first semiconductor integrated-circuit (IC) chip is recessed from a second edge of the interconnection scheme, wherein the interconnection scheme comprises the third metal interconnect therein and the metal bump is on the interconnection scheme.
10 . The chip package of claim 1 further comprising a second semiconductor integrated-circuit (IC) chip coupling to the second metal interconnect through the third metal interconnect.
11 . The chip package of claim 10 further comprising a third semiconductor integrated-circuit (IC) chip at a same horizontal level as the second semiconductor integrated-circuit (IC) chip and an interconnection scheme over the first semiconductor integrated-circuit (IC) chip, across a first and a second edge of the first semiconductor integrated-circuit (IC) chip and coupling the third semiconductor integrated-circuit (IC) chip to the first metal interconnect, wherein the interconnection scheme comprises the third metal interconnect therein.
12 . The chip package of claim 11 , wherein each of the second and third semiconductor integrated-circuit (IC) chips is under the interconnection scheme.
13 . The chip package of claim 1 further comprising an interconnection scheme over the first semiconductor integrated-circuit (IC) chip and across a first and a second edge of the first semiconductor integrated-circuit (IC) chip, wherein the first edge of the first semiconductor integrated-circuit (IC) chip is recessed from a first edge of the interconnection scheme and the second edge of the first semiconductor integrated-circuit (IC) chip is recessed from a second edge of the interconnection scheme, wherein the interconnection scheme comprises the third metal interconnect therein, wherein the first semiconductor integrated-circuit (IC) chip further comprises a metal contact at a top thereof coupling to the interconnection scheme, wherein the interconnection scheme comprises an interconnection metal layer over the first semiconductor integrated-circuit (IC) chip, across the first and second edges of the first semiconductor integrated-circuit (IC) chip and in contact with the metal contact of the first semiconductor integrated-circuit (IC) chip and a polymer layer on the interconnection metal layer.
14 . The chip package of claim 13 , wherein the metal contact comprises a copper layer.
15 . The chip package of claim 13 , wherein the interconnection metal layer comprises a copper layer having a thickness between 1 and 10 micrometers.
16 . The chip package of claim 1 further comprising an interconnection scheme over the first semiconductor integrated-circuit (IC) chip and across a first and a second edge of the first semiconductor integrated-circuit (IC) chip, wherein the first edge of the first semiconductor integrated-circuit (IC) chip is recessed from a first edge of the interconnection scheme and the second edge of the first semiconductor integrated-circuit (IC) chip is recessed from a second edge of the interconnection scheme, wherein the interconnection scheme comprises the third metal interconnect therein, wherein the interconnection scheme comprises a first interconnection metal layer over the first semiconductor integrated-circuit (IC) chip and across the first and second edges of the first semiconductor integrated-circuit (IC) chip, a second interconnection metal layer over the first interconnection metal layer and an insulating dielectric layer between the first and second interconnection metal layers.
17 . The chip package of claim 1 further comprising a first interconnection scheme over the first semiconductor integrated-circuit (IC) chip and across a first and a second edge of the first semiconductor integrated-circuit (IC) chip and a second interconnection scheme under the first semiconductor integrated-circuit (IC) chip, across the first and second edges of the first semiconductor integrated-circuit (IC) chip and coupling to the first interconnection scheme, wherein the first interconnection scheme comprises the third metal interconnect therein.
18 . The chip package of claim 17 , wherein the second interconnection scheme comprises a metal pad at a bottom thereof, wherein the metal pad couples to the third metal interconnect, wherein the switch is configured for the metal pad to be programmable by controlling, in accordance with the second data, pass or no-pass of data between the metal pad and first metal interconnect.
19 . The chip package of claim 18 further comprising a metal bump on a bottom surface of the metal pad.
20 . The chip package of claim 19 , wherein the metal bump comprises tin.
21 . The chip package of claim 1 further comprising a first interconnection scheme over the first semiconductor integrated-circuit (IC) chip and across a first and a second edge of the first semiconductor integrated-circuit (IC) chip and a sealing layer under the first interconnection scheme and at a same horizontal level as the first semiconductor integrated-circuit (IC) chip, wherein the first interconnection scheme comprises the third metal interconnect therein.
22 . The chip package of claim 21 further comprising a metal pillar vertically in the sealing layer, under the first interconnection scheme, at the same horizontal level as the first semiconductor integrated-circuit (IC) chip and sealing layer and coupling to the first interconnection scheme.
23 . The chip package of claim 22 , wherein the third metal interconnect couples to the metal pillar, wherein the switch is configured for the metal pillar to be programmable by controlling, in accordance with the second data, pass or no-pass of data between the metal pillar and first metal interconnect.
24 . The chip package of claim 22 further comprising a second interconnection scheme under the first semiconductor integrated-circuit (IC) chip, sealing layer and metal pillar, across the first and second edges of the first semiconductor integrated-circuit (IC) chip and coupling to the first interconnection scheme through the metal pillar.
25 . The chip package of claim 24 , wherein the second interconnection scheme comprises a metal pad at a bottom thereof, wherein the metal pad couples to the third metal interconnect, wherein the switch is configured for the metal pad to be programmable by controlling, in accordance with the second data, pass or no-pass of data between the metal pad and first metal interconnect.
26 . The chip package of claim 25 further comprising a metal bump on a bottom surface of the metal pad.
27 . The chip package of claim 22 , wherein the metal pillar comprises a copper layer having a thickness between 5 and 300 micrometers.
28 . The chip package of claim 21 , wherein the sealing layer comprises a molding compound.
29 . The chip package of claim 1 further comprising a second semiconductor integrated-circuit (IC) chip therein, wherein the second semiconductor integrated-circuit (IC) chip comprises a second input/output (I/O) circuit coupling to the first input/output (I/O) circuit of the first semiconductor integrated-circuit (IC) chip through the third metal interconnect, wherein the switch is configured for controlling, in accordance with the second data, pass or no-pass of data between the second input/output (I/O) circuit and the first metal interconnect through the third metal interconnect, first input/output (I/O) circuit and second metal interconnect.
30 . The chip package of claim 29 , wherein each of the first and second input/output (I/O) circuits has an input capacitance smaller than 1 pF.
31 . The chip package of claim 29 , wherein the third metal interconnect is a vertical interconnect.
32 . The chip package of claim 29 further comprising a first interconnection scheme over the first semiconductor integrated-circuit (IC) chip and across a first and a second edge of the first semiconductor integrated-circuit (IC) chip, wherein the first edge of the first semiconductor integrated-circuit (IC) chip is recessed from a first edge of the first interconnection scheme and the second edge of the first semiconductor integrated-circuit (IC) chip is recessed from a second edge of the first interconnection scheme, wherein the first interconnection scheme comprises a first metal line for use as the third metal interconnect therein, wherein the first semiconductor integrated-circuit (IC) chip comprises a silicon substrate, a transistor at a top of the silicon substrate and a second interconnection scheme over the silicon substrate, wherein the second interconnection scheme comprises a second metal line for use as the first metal interconnect therein and a third metal line for use as the second metal interconnect therein.
33 . The chip package of claim 1 further comprising a first interconnection scheme over the first semiconductor integrated-circuit (IC) chip and across a first and a second edge of the first semiconductor integrated-circuit (IC) chip, wherein the first edge of the first semiconductor integrated-circuit (IC) chip is recessed from a first edge of the first interconnection scheme and the second edge of the first semiconductor integrated-circuit (IC) chip is recessed from a second edge of the first interconnection scheme, wherein the first interconnection scheme comprises a first metal line for use as the third metal interconnect therein, wherein the first semiconductor integrated-circuit (IC) chip comprises a silicon substrate, a transistor at a top of the silicon substrate and a second interconnection scheme over the silicon substrate, wherein the second interconnection scheme comprises a second metal line for use as the first metal interconnect therein and a third metal line for use as the second metal interconnect therein.