IP Library › Granted Patent US 12,302,639
Granted Patent B2
US 12,302,639 · App. 18/616,481 · Granted May 13, 2025

Metal oxide film and method for forming metal oxide film

Inventors: Masahiro Takahashi (Kanagawa, JP); Takuya Hirohashi (Kanagawa, JP); Masashi Tsubuku (Kanagawa, JP); Noritaka Ishihara (Kanagawa, JP); Masashi Oota (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H10D86/60C23C14/086G01N23/207G02F1/1368H01L22/12H10D30/6755H10D30/6756H10D62/40H10D62/80H10D86/423H10D99/00H01L21/0237H01L21/02422H01L21/02554H01L21/02565H01L21/02631H01L2924/0002
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Quick Facts
Patent No.
US 12,302,639
App. No.
18/616,481
Granted
May 13, 2025
Kind
B2
Abstract

A metal oxide film including a crystal part and having highly stable physical properties is provided. The size of the crystal part is less than or equal to 10 nm, which allows the observation of circumferentially arranged spots in a nanobeam electron diffraction pattern of the cross section of the metal oxide film when the measurement area is greater than or equal to 5 nmφ and less than or equal to 10 nmφ.

Claims (57)

1. A display device comprising:

a first transistor, a second transistor, a light-emitting element, and a capacitor,

wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to a gate electrode of the second transistor and one electrode of the capacitor,

wherein another electrode of the capacitor is electrically connected to a power supply line,

wherein a potential of the power supply line is supplied to the light-emitting element at least through a channel of the second transistor,

wherein at least one of the first transistor and the second transistor comprises a gate electrode, an oxide semiconductor layer, and a gate insulating film between the gate electrode and the oxide semiconductor layer,

wherein a plurality of circumferentially distributed spots are observable in a nanobeam electron diffraction pattern of the oxide semiconductor layer,

wherein the plurality of circumferentially distributed spots do not have regularity that represents crystal parts aligned with a specific plane,

wherein the oxide semiconductor layer comprises a region in contact with a top surface of an insulating film,

wherein the insulating film comprises silicon oxide, and

wherein the gate insulating film comprises silicon oxide.

2. The display device according to claim 1 , wherein, when the oxide semiconductor layer is irradiated with electron beam whose beam diameter is converged to 1 nmφ for a minute, change in the electron diffraction pattern before and after the irradiation does not occur.

3. The display device according to claim 1 ,

wherein the oxide semiconductor layer comprises carbon, and

wherein a concentration of carbon is less than 4×10 21 atoms/cm 3 .

4. The display device according to claim 1 ,

wherein the oxide semiconductor layer comprises hydrogen, and

wherein a concentration of hydrogen is less than 1×10 22 atoms/cm 3 .

5. The display device according to claim 1 , wherein the nanobeam electron diffraction pattern is measured using electron beam whose beam diameter is 1 nmφ.

6. The display device according to claim 1 ,

wherein the oxide semiconductor layer includes a plurality of crystals,

wherein surface orientations of the plurality of crystals are random, and

wherein a crystalline peak corresponding to the plurality of crystals is not observable in an XRD spectrum with respect to a region of the oxide semiconductor layer.

7. The display device according to claim 6 ,

wherein a size of each of the plurality of crystals is greater than or equal to 1 nm and smaller than or equal to 10 nm.

8. A display device comprising:

a first transistor, a second transistor, a light-emitting element, and a capacitor,

wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to a gate electrode of the second transistor and one electrode of the capacitor,

wherein another electrode of the capacitor is electrically connected to a power supply line,

wherein a potential of the power supply line is supplied to the light-emitting element at least through a channel of the second transistor,

wherein at least one of the first transistor and the second transistor comprises a first conductive layer serving as a gate electrode, a first insulating film over the first conductive layer, and an oxide semiconductor layer in contact with a top surface of the first insulating film,

wherein a plurality of circumferentially distributed spots are observable in a nanobeam electron diffraction pattern of the oxide semiconductor layer,

wherein the plurality of circumferentially distributed spots do not have regularity that represents crystal parts aligned with a specific plane,

wherein a second insulating film comprises a region in contact with a top surface of the oxide semiconductor layer,

wherein the first insulating film comprises silicon oxide, and

wherein the second insulating film comprises silicon oxide.

9. The display device according to claim 8 ,

wherein, when the oxide semiconductor layer is irradiated with electron beam whose beam diameter is converged to 1 nmφ for a minute, change in the electron diffraction pattern before and after the irradiation does not occur.

10. The display device according to claim 8 ,

wherein the oxide semiconductor layer comprises carbon, and

wherein a concentration of carbon is less than 4×10 21 atoms/cm 3 .

11. The display device according to claim 8 ,

wherein the oxide semiconductor layer comprises hydrogen, and

wherein a concentration of hydrogen is less than 1×10 22 atoms/cm 3 .

12. The display device according to claim 8 , wherein the nanobeam electron diffraction pattern is measured using electron beam whose beam diameter is 1 nmφ.

13. The display device according to claim 8 ,

wherein the oxide semiconductor layer includes a plurality of crystals,

wherein surface orientations of the plurality of crystals are random, and

wherein a crystalline peak corresponding to the plurality of crystals is not observable in an XRD spectrum with respect to a region of the oxide semiconductor layer.

14. The display device according to claim 13 , wherein a size of each of the plurality of crystals is greater than or equal to 1 nm and smaller than or equal to 10 nm.

15. A display device comprising:

a first transistor, a second transistor, a light-emitting element, and a capacitor,

wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to a gate electrode of the second transistor and one electrode of the capacitor,

wherein another electrode of the capacitor is electrically connected to a power supply line,

wherein a potential of the power supply line is supplied to the light-emitting element at least through a channel of the second transistor,

wherein at least one of the first transistor and the second transistor comprises a first conductive layer serving as a gate electrode, a first insulating film over the first conductive layer, and an oxide semiconductor layer in contact with a top surface of the first insulating film, and

wherein a plurality of circumferentially distributed spots are observable in a nanobeam electron diffraction pattern of the oxide semiconductor layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 26, 2024
From: TAKAHASHI, MASAHIRO; HIROHASHI, TAKUYA; TSUBUKU, MASASHI; ISHIHARA, NORITAKA; OOTA, MASASHI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 066898/0820 →
Priority Claims (3)
JP 2012-245992 · Nov 8, 2012 · national
JP 2013-016242 · Jan 30, 2013 · national
JP 2013-056768 · Mar 19, 2013 · national
Continuity (6)
Continuation 18137032 · Apr 20, 2023
Continuation 17144550 · Jan 8, 2021
Continuation 16024997 · Jul 2, 2018
Continuation 15879506 · Jan 25, 2018
Continuation 14071932 · Nov 5, 2013
Related Publication 20240321897A1 · Sep 26, 2024
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