IP Library › Granted Patent US 12,199,107
Granted Patent B2
US 12,199,107 · App. 18/197,805 · Granted Jan 14, 2025

Liquid crystal display device and method for manufacturing the same

Inventors: Shunpei Yamazaki (Tokyo, JP); Kaoru Hatano (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L27/124G02F1/1333G02F1/1343G02F1/136213H01L27/1225H01L27/1259H01L29/24H01L29/78618H01L29/7869H01L29/78696G02F1/136227G02F1/136231G02F2201/50
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Quick Facts
Patent No.
US 12,199,107
App. No.
18/197,805
Granted
Jan 14, 2025
Kind
B2
Abstract

Provided is a method to manufacture a liquid crystal display device in which a contact hole for the electrical connection of the pixel electrode and one of the source and drain electrode of a transistor and a contact hole for the processing of a semiconductor layer are formed simultaneously. The method contributes to the reduction of a photography step. The transistor includes an oxide semiconductor layer where a channel formation region is formed.

Claims (98)

1. A display device comprising:

a pixel portion comprising:

a first conductive layer comprising a region configured to serve as a gate electrode of a transistor and a region configured to serve as a first wiring;

a second conductive layer comprising a region configured to serve as a capacitor wiring;

a first insulating layer comprising a region over the first conductive layer and a region over the second conductive layer;

a semiconductor layer in contact with an upper surface of the first insulating layer, the semiconductor layer comprising a channel formation region of the transistor;

a third conductive layer electrically connected to the semiconductor layer, the third conductive layer comprising a region configured to serve as one of a source electrode and a drain electrode of the transistor and a region configured to serve as a second wiring;

a fourth conductive layer electrically connected to the semiconductor layer, the fourth conductive layer comprising a region configured to serve as the other of the source electrode and the drain electrode of the transistor;

a fifth conductive layer over the first insulating layer, the fifth conductive layer comprising a region overlapping with the second conductive layer;

a second insulating layer comprising a region in contact with an upper surface of the third conductive layer, a region in contact with an upper surface of the fourth conductive layer, and a region in contact with an upper surface of the fifth conductive layer; and

a pixel electrode comprising a region overlapping with the second insulating layer and a region in contact with the upper surface of the fourth conductive layer through a contact hole in the second insulating layer; and

a connection portion outside the pixel portion, the connection portion comprising:

a sixth conductive layer comprising a region in contact with an insulating surface; and

a seventh conductive layer comprising a region in contact with an upper surface of the sixth conductive layer, the seventh conductive layer comprising the same material as the pixel electrode,

wherein the fourth conductive layer comprises a first region having a first width in a first direction,

wherein the fourth conductive layer comprises a second region having a second width in the first direction,

wherein the second width is larger than the first width,

wherein an entirety of the contact hole in the second insulating layer overlaps with the second region of the fourth conductive layer,

wherein each of the first conductive layer and the second conductive layer comprises a region in contact with the insulating surface,

wherein the first conductive layer and the second conductive layer comprise the same material,

wherein the third conductive layer, the fourth conductive layer, and the fifth conductive layer comprise the same material,

wherein the semiconductor layer comprises a region where the semiconductor layer and the first conductive layer overlap each other,

wherein the semiconductor layer comprises a region where the semiconductor layer and the second conductive layer overlap each other,

wherein the semiconductor layer comprises a region where the semiconductor layer and the third conductive layer overlap each other,

wherein the semiconductor layer comprises a region where the semiconductor layer and the fourth conductive layer overlap each other,

wherein the semiconductor layer comprises a region where the semiconductor layer and the fifth conductive layer overlap each other, and

wherein the third conductive layer comprises a U-shaped region surrounding at least part of the fourth conductive layer.

2. The display device according to claim 1 , wherein the semiconductor layer comprises indium, gallium, zinc, and oxygen.

3. The display device according to claim 1 , further comprising:

a liquid crystal material over the second insulating layer.

4. The display device according to claim 1 , wherein the first conductive layer and the third conductive layer overlap each other.

5. The display device according to claim 1 , wherein the channel formation region comprises crystals with c-axis alignment.

6. A display device comprising:

a pixel portion comprising:

a first conductive layer comprising a region configured to serve as a gate electrode of a transistor and a region configured to serve as a first wiring;

a second conductive layer comprising a region configured to serve as a capacitor wiring;

a first insulating layer comprising a region over the first conductive layer and a region over the second conductive layer;

a semiconductor layer in contact with an upper surface of the first insulating layer, the semiconductor layer comprising a channel formation region of the transistor;

a third conductive layer electrically connected to the semiconductor layer, the third conductive layer comprising a region configured to serve as one of a source electrode and a drain electrode of the transistor and a region configured to serve as a second wiring;

a fourth conductive layer electrically connected to the semiconductor layer, the fourth conductive layer comprising a region configured to serve as the other of the source electrode and the drain electrode of the transistor;

a fifth conductive layer over the first insulating layer, the fifth conductive layer comprising a region overlapping with the second conductive layer;

a second insulating layer comprising a region in contact with an upper surface of the third conductive layer, a region in contact with an upper surface of the fourth conductive layer, and a region in contact with an upper surface of the fifth conductive layer; and

a pixel electrode comprising a region overlapping with the second insulating layer and a region in contact with the upper surface of the fourth conductive layer through a contact hole in the second insulating layer; and

a connection portion outside the pixel portion, the connection portion comprising:

a sixth conductive layer comprising a region in direct contact with an insulating surface; and

a seventh conductive layer comprising a region in contact with an upper surface of the sixth conductive layer, the seventh conductive layer comprising the same material as the pixel electrode,

wherein the fourth conductive layer comprises a first region having a first width in a first direction,

wherein the fourth conductive layer comprises a second region having a second width in the first direction,

wherein the second width is larger than the first width,

wherein an entirety of the contact hole in the second insulating layer overlaps with the second region of the fourth conductive layer,

wherein each of the first conductive layer and the second conductive layer comprises a region in direct contact with the insulating surface,

wherein the first conductive layer and the second conductive layer comprise the same material,

wherein the third conductive layer, the fourth conductive layer, and the fifth conductive layer comprise the same material,

wherein the semiconductor layer comprises a region where the semiconductor layer and the first conductive layer overlap each other,

wherein the semiconductor layer comprises a region where the semiconductor layer and the second conductive layer overlap each other,

wherein the semiconductor layer comprises a region where the semiconductor layer and the third conductive layer overlap each other,

wherein the semiconductor layer comprises a region where the semiconductor layer and the fourth conductive layer overlap each other,

wherein the semiconductor layer comprises a region where the semiconductor layer and the fifth conductive layer overlap each other, and

wherein the third conductive layer comprises a U-shaped region surrounding at least part of the fourth conductive layer.

7. The display device according to claim 6 , wherein the semiconductor layer comprises indium, gallium, zinc, and oxygen.

8. The display device according to claim 6 , further comprising:

a liquid crystal material over the second insulating layer.

9. The display device according to claim 6 , wherein the first conductive layer and the third conductive layer overlap each other.

10. The display device according to claim 6 , wherein the channel formation region comprises crystals with c-axis alignment.

11. A display device comprising:

a pixel portion comprising:

a first conductive layer comprising a region configured to serve as a gate electrode of a transistor and a region configured to serve as a first wiring;

a second conductive layer comprising a region configured to serve as a capacitor wiring;

a first insulating layer comprising a region over the first conductive layer and a region over the second conductive layer;

a semiconductor layer in contact with an upper surface of the first insulating layer, the semiconductor layer comprising a channel formation region of the transistor;

a third conductive layer electrically connected to the semiconductor layer, the third conductive layer comprising a region configured to serve as one of a source electrode and a drain electrode of the transistor and a region configured to serve as a second wiring;

a fourth conductive layer electrically connected to the semiconductor layer, the fourth conductive layer comprising a region configured to serve as the other of the source electrode and the drain electrode of the transistor;

a fifth conductive layer over the first insulating layer, the fifth conductive layer comprising a region overlapping with the second conductive layer;

a second insulating layer comprising a region in contact with an upper surface of the third conductive layer, a region in contact with an upper surface of the fourth conductive layer, and a region in contact with an upper surface of the fifth conductive layer; and

a pixel electrode comprising a region overlapping with the second insulating layer and a region in contact with the upper surface of the fourth conductive layer through a contact hole in the second insulating layer; and

a connection portion outside the pixel portion, the connection portion comprising:

a sixth conductive layer comprising a region in contact with an insulating surface; and

a seventh conductive layer comprising a region in contact with an upper surface of the sixth conductive layer, the seventh conductive layer comprising the same material as the pixel electrode,

wherein the fourth conductive layer comprises a first region having a first width in a first direction,

wherein the fourth conductive layer comprises a second region having a second width in the first direction,

wherein the second width is larger than the first width,

wherein an entirety of the contact hole in the second insulating layer overlaps with the second region of the fourth conductive layer,

wherein each of the first conductive layer and the second conductive layer comprises a region in contact with the insulating surface,

wherein the first conductive layer and the second conductive layer comprise the same material,

wherein the third conductive layer, the fourth conductive layer, and the fifth conductive layer comprise the same material,

wherein the semiconductor layer comprises a region where the semiconductor layer and the first conductive layer overlap each other,

wherein the semiconductor layer comprises a region where the semiconductor layer and the second conductive layer overlap each other,

wherein the semiconductor layer comprises a region where the semiconductor layer and the third conductive layer overlap each other,

wherein the semiconductor layer comprises a region where the semiconductor layer and the fourth conductive layer overlap each other,

wherein the semiconductor layer comprises a region where the semiconductor layer and the fifth conductive layer overlap each other,

wherein the semiconductor layer comprises a region where the semiconductor layer and the sixth conductive layer overlap each other,

wherein the semiconductor layer comprises a region where the semiconductor layer and the seventh conductive layer overlap each other, and

wherein the third conductive layer comprises a U-shaped region surrounding at least part of the fourth conductive layer.

12. The display device according to claim 11 , wherein the semiconductor layer comprises indium, gallium, zinc, and oxygen.

13. The display device according to claim 11 , further comprising:

a liquid crystal material over the second insulating layer.

14. The display device according to claim 11 , wherein the first conductive layer and the third conductive layer overlap each other.

15. The display device according to claim 11 , wherein the channel formation region comprises crystals with c-axis alignment.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 16, 2023
From: YAMAZAKI, SHUNPEI; HATANO, KAORU
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 063652/0839 →
Priority Claims (1)
JP 2010-204930 · Sep 13, 2010 · national
Continuity (8)
Continuation 17859054 · Jul 7, 2022
Continuation 17331826 · May 27, 2021
Continuation 16724666 · Dec 23, 2019
Continuation 15916362 · Mar 9, 2018
Continuation 15088200 · Apr 1, 2016
Continuation 14023515 · Sep 11, 2013
Continuation 13227092 · Sep 7, 2011
Related Publication 20230282651A1 · Sep 7, 2023
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