Granted Patent B2

US 12,302,760 · App. 18/670,641 · Granted May 13, 2025

Inventors: Thorsten Lill (Kalaheo, HI); Ivan L. Berry, III (Green Valley, AZ)

Assignee: Lam Research Corporation

H10N50/01G11C11/161H10B61/00H10N50/10H10N50/80H10N50/85

Abstract

Claims (26)

1. An apparatus for performing ion beam etching, the apparatus comprising:

an ion beam source chamber;

a processing chamber coupled to the ion beam source chamber;

a controller configured to provide instructions to perform the following operations:

dispose a plurality of MRAM layers on a substrate in the processing chamber, the plurality of MRAM layers including one or more magnetic layers and a tunnel barrier layer;

etch through the plurality of MRAM layers disposed on the substrate to form patterned MRAM stacks, wherein the etch through the plurality of MRAM layers includes ion beam etching (IBE) through at least the tunnel barrier layer;

form a gapfill dielectric material in spaces between the patterned MRAM stacks; and

perform an IBE trim etch to remove at least some of the gapfill dielectric material and electrically conductive materials deposited on sidewalls of the patterned MRAM stacks.

2. The apparatus of claim 1 , wherein the controller configured to provide instructions to form the gapfill dielectric material is further configured to provide instructions to perform the following operation:

deposit the gapfill dielectric material in the spaces between the patterned MRAM stacks and over the patterned MRAM stacks.

3. The apparatus of claim 2 , wherein the controller configured to provide instructions to form the gapfill dielectric material is further configured to provide instructions to perform the following operation:

selectively etch the gapfill dielectric material to an etch depth above the depth of the tunnel barrier layer.

4. The apparatus of claim 3 , wherein the controller is further configured to provide instructions to perform the following operation:

planarize the gapfill dielectric material deposited over the patterned MRAM stacks before selectively etching the gapfill dielectric material.

5. The apparatus of claim 1 , wherein the gapfill dielectric material comprises silicon nitride, silicon oxide, silicon oxycarbide, germanium oxide, magnesium oxide, germanium nitride, or combinations thereof.

6. The apparatus of claim 5 , wherein the gapfill dielectric material comprises one or both of silicon nitride and silicon oxide.

7. The apparatus of claim 1 , wherein the controller configured to provide instructions to ion beam etch through at least the tunnel barrier layer is further configured to provide instructions to apply a first ion beam to the substrate having an energy between about 200 eV and about 10,000 eV, and wherein the controller configured to provide instructions to perform the IBE trim etch is further configured to apply a second ion beam to the substrate having an energy between about 20 eV and about 400 eV.

8. The apparatus of claim 1 , wherein the gapfill dielectric material is formed to a sufficient depth above an underlayer disposed between the substrate and the plurality of MRAM layers so that performing the IBE trim etch does not cause recess into the underlayer.

9. The apparatus of claim 8 , wherein the sufficient depth above the underlayer is between 1 nm and 20 nm above a top surface of the underlayer.

10. The apparatus of claim 1 , wherein a remainder of the gapfill dielectric material after the IBE trim etch is at a depth below the tunnel barrier layer and above an underlayer disposed between the substrate and the plurality of MRAM layers.

11. The apparatus of claim 1 , the controller configured with instructions to etch through the plurality of MRAM layers, form the gapfill dielectric material, and perform the IBE trim etch is configured with instructions to perform the aforementioned operations without introducing a vacuum break in between operations.

12. The apparatus of claim 1 , wherein the plurality of MRAM layers comprises a first magnetic layer, a second magnetic layer, the tunnel barrier layer between the first magnetic layer and the second magnetic layer, and an underlayer disposed below the second magnetic layer, wherein the underlayer includes a dielectric material, and wherein the tunnel barrier layer includes a non-magnetic insulating material.

13. The apparatus of claim 12 , wherein the controller configured with instructions to etch through the plurality of MRAM layers is configured with instructions to ion beam etch through the first magnetic layer, the tunnel barrier layer, and the second magnetic layer without etching through the underlayer.

14. The apparatus of claim 12 , wherein the controller configured with instructions to etch through the plurality of MRAM layers is configured with instructions to reactive ion etch (RIE) through the first magnetic layer and ion beam etch through the tunnel barrier layer.

15. The apparatus of claim 12 , wherein the controller configured with instructions to etch through the plurality of MRAM layers is configured with instructions to etch through the first magnetic layer, the tunnel barrier layer, and the second magnetic layer, wherein etching through the plurality of MRAM layers is stopped on the underlayer.

16. The apparatus of claim 1 , wherein the electrically conductive materials comprise tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), cobalt (Co), nickel (Ni), iron (Fe) platinum (Pt), ruthenium (Ru), or combinations thereof, and wherein the sidewalls of the patterned MRAM stacks are substantially free of the electrically conductive materials deposited on the sidewalls of the patterned MRAM stacks after performing the IBE trim etch.

Continuity (3)

References Cited (308)