IP Library › Assignment 011796/0615
Patent Assignment
Reel/Frame 011796/0615

Assignment of Assignor's Interest

Recorded: 2001-05-18 Pages: 43
Assignor
LUCENT TECHNOLOGIES INC.
Executed: 2001-01-31
Assignee
AGERE SYSTEMS GUARDIAN CORP.
9333 S. JOHN YOUNG PARKWAY, ORLANDO, FLORIDA, 32819
Covered Properties (129)
Method of Fabricating Polysilicon Electrodes
Patent: 4,347,656 →
Application: 06/218,952 →
Method of Fabricating High-Conductivity Silicide-on-Polysilicon Structures for Mos Devices
Patent: 4,362,597 →
Application: 06/226,104 →
Ion Implanted Cmos Devices
Patent: 4,684,971 →
Application: 06/243,621 →
Hydrogen Etching of Semiconductors and Oxides
Patent: 4,361,461 →
Application: 06/243,622 →
Method of Preparing Semiconductor Surfaces
Patent: 4,380,490 →
Application: 06/248,549 →
Assembling an Electronic Device
Patent: 4,399,610 →
Application: 06/249,752 →
Apparatus and Method for Plasma-Assisted Etching of Wafers
Patent: 4,419,201 →
Application: 06/295,531 →
Apparatus and Method for Plasma-Assisted Etching of Wafers
Patent: 4,397,724 →
Application: 06/295,839 →
Cobalt Silicide Metallization for Semiconductor Integrated Circuits
Patent: 4,378,628 →
Application: 06/296,914 →
Solid State Device with Chain-Shaped Grain Structure
Patent: 4,438,450 →
Application: 06/328,149 →
Etching Apparatus and Method
Patent: 4,400,235 →
Application: 06/362,045 →
Iii-V Based Semiconductor Devices and a Process for Fabrication
Patent: 4,493,142 →
Application: 06/376,178 →
Method for Making Integrated Semiconductor Circuit Structure with Formation of Ti or Ta Silicide
Patent: 32,207 →
Application: 06/429,299 →
Integrated Circuit Including Logic Array with Distributed Ground Connections
Patent: 4,516,123 →
Application: 06/453,180 →
Wafer Holding Apparatus and Method
Patent: 4,473,455 →
Application: 06/473,261 →
Compound Current Mirror
Patent: 4,477,782 →
Application: 06/495,063 →
Chipset Synchronization Arrangement
Patent: 4,514,647 →
Application: 06/519,495 →
Ohmic Contacts for Semiconductor Devices
Patent: 4,510,514 →
Application: 06/521,443 →
Removal of Coating from Periphery of a Semiconductor Wafer
Patent: 4,510,176 →
Application: 06/535,916 →
Switched Current Mirror
Patent: 4,544,878 →
Application: 06/538,946 →
Silicon Gigabit Metal-Oxide-Semiconductor Device Processing
Patent: 4,532,697 →
Application: 06/557,638 →
Deposition Technique
Patent: 4,574,093 →
Application: 06/566,918 →
Integrated Circuit Chip and Substrate Assembly
Patent: 4,670,770 →
Application: 06/582,079 →
Integrated Circuit Contact Technique
Patent: 4,535,532 →
Application: 06/598,179 →
Metallization Process for Headless Contact Using Deposited Smoothing Material
Patent: 4,641,420 →
Application: 06/645,549 →
Field Effect Transistor Current Source
Patent: 4,645,948 →
Application: 06/656,343 →
Multilayering Process for Stress Accommodation in Deposited Polysilicon
Patent: 4,742,020 →
Application: 06/680,140 →
Fast Column Access Memory
Patent: 4,649,522 →
Application: 06/700,459 →
Fabrication of Dielectrically Isolated Devices Utilizing Buried Oxygen Implant and Subsequent Heat Treatment at Temperatures Above 1300 C
Patent: 4,676,841 →
Application: 06/781,407 →
Transistor Sizing System for Integrated Circuits
Patent: 4,827,428 →
Application: 06/798,557 →
Depletion Stop Transistor
Patent: 4,750,025 →
Application: 06/823,985 →
Semiconductor Package with High Density I/O Lead Connection
Patent: 4,774,635 →
Application: 06/866,931 →
Deep-Uv Lithography
Patent: 4,773,750 →
Application: 06/939,278 →
Balanced Output Analog Differential Amplifier Circuit
Patent: 4,742,308 →
Application: 07/037,301 →
Protection of Igfet Integrated Circuits from Electrostatic Discharge
Patent: 4,821,089 →
Application: 07/059,194 →
Stress Relief in Epitaxial Wafers
Patent: 4,769,689 →
Application: 07/073,296 →
Laser-Blown Links
Patent: 4,853,758 →
Application: 07/084,531 →
Cmos to Ecl Output Buffer
Patent: 4,912,347 →
Application: 07/089,284 →
High Speed Mos Circuits
Patent: 4,782,253 →
Application: 07/099,702 →
Multiple Output Field Effect Transistor Logic
Patent: 4,851,714 →
Application: 07/131,872 →
Deep-Uv Lithography
Patent: 4,883,352 →
Application: 07/231,803 →
Cmos Integrated Circuit Having Improved Isolation
Patent: 5,045,898 →
Application: 07/238,362 →
Integrated Circuit Power Supply Contact
Patent: 4,947,228 →
Application: 07/246,713 →
Semiconductor Device Having Tungsten Plugs
Patent: 4,981,550 →
Application: 07/270,389 →
Anisotropic Deposition of Silicon Dioxide
Patent: 5,013,691 →
Application: 07/386,650 →
Compensation of Lithographic and Etch Proximity Effects
Patent: 5,057,462 →
Application: 07/413,356 →
Metallization Processing
Patent: 4,999,317 →
Application: 07/414,888 →
Delay Generator
Patent: 5,014,286 →
Application: 07/419,427 →
Thin Coatings for Use in Semiconductor Integrated Circuits and Processes as Antireflectiion Coating Consisting of Tungsten Silicide
Patent: 5,106,786 →
Application: 07/425,134 →
Method of Integrated Circuit Manufacturing Using Deposited Oxide
Patent: 5,328,872 →
Application: 07/459,167 →
Devices Having Shallow Junctions
Patent: 5,063,422 →
Application: 07/515,550 →
Tungsten Metallization
Patent: 5,227,335 →
Application: 07/517,973 →
Article Comprising a Stacked Array of Electronic Subassemblies
Patent: 5,049,982 →
Application: 07/519,728 →
Transistor Fabrication Method
Patent: 5,045,486 →
Application: 07/543,592 →
Self-Adjusting Heat Sink Design for Vlsi Packages
Patent: 5,107,330 →
Application: 07/599,948 →
Mos Devices Having Improved Threshold Match
Patent: 5,040,035 →
Application: 07/634,930 →
Idle Channel Tone and Periodic Noise Suppression for Sigma-Delta Modulators Using High-Level Dither
Patent: 5,144,308 →
Application: 07/703,527 →
Gaas Mesfets with Enhanced Schottky Barrier
Patent: 5,106,771 →
Application: 07/710,594 →
Electronic Device Interconnection Techniques
Patent: 5,155,302 →
Application: 07/720,067 →
Digitally Controlled Element Sizing
Patent: 5,243,229 →
Application: 07/724,559 →
Digitally Controlled Element Sizing
Patent: 5,194,765 →
Application: 07/724,560 →
Contact Metallization of Semiconductor Integrated-Circuit Devices
Patent: 5,102,827 →
Application: 07/732,947 →
Silicide Formation on Polysilicon
Patent: 5,147,820 →
Application: 07/749,762 →
Process for Fabricating Integrated Circuits Having Shallow Junctions
Patent: 5,149,672 →
Application: 07/754,361 →
Pseudo-Electroless, Followed by Electroless, Metallization of Nickel on Metallic Wires, as for Semiconductor Chip-to-Chip Interconnections
Patent: 5,264,107 →
Application: 07/809,694 →
Balanced Line Driver for Local Area Networks or the Like
Patent: 5,285,477 →
Application: 07/810,632 →
Transistor Fabrication Method
Patent: 5,278,096 →
Application: 07/814,981 →
Semiconductor Integrated Circuit Packages
Patent: 34,269 →
Application: 07/837,573 →
Method of Making an Article Comprising a Periodic Heteroepitaxial Semiconductor Structure
Patent: 5,213,995 →
Application: 07/869,980 →
Transconductance Cell with Improved Linearity
Patent: 5,311,088 →
Application: 07/918,172 →
Permanent Metallic Bonding Method
Patent: 5,234,153 →
Application: 07/938,195 →
Anisotropic Conductor Techniques
Patent: 5,304,460 →
Application: 07/954,190 →
High-Speed Modem Synchronized to a Remote Codec
Patent: 5,394,437 →
Application: 07/963,539 →
Method for Selectively Etching Algaas
Patent: 5,380,398 →
Application: 07/982,194 →
Digital Programmable Frequency Generator
Patent: 5,416,446 →
Application: 07/987,917 →
Power Supply Loss Sensor
Patent: 5,457,414 →
Application: 07/994,732 →
Automatic Control of Buffer Speed
Patent: 5,334,885 →
Application: 08/003,751 →
Method of Making a Compound Semiconductor Device
Patent: 5,346,581 →
Application: 08/042,385 →
Forming a Device Dielectric on a Deposited Semiconductor Having Sub-Layers
Patent: 5,298,436 →
Application: 08/076,949 →
Low Temperature Deposition of Silicon Oxides for Device Fabrication
Patent: 5,643,838 →
Application: 08/116,309 →
Planar Isolation Technique for Integrated Circuits
Patent: 5,373,180 →
Application: 08/121,082 →
Surface Mount Solder Assembly of Leadless Integrated Circuit Packages to Substrates
Patent: 5,346,118 →
Application: 08/128,492 →
Method of Fabricating Semiconductor Devices Having Electrodes Comprising Layers of Doped Tungsten Disilicide
Patent: 5,395,799 →
Application: 08/131,508 →
Fully Scalable Memory Apparatus
Patent: 5,355,345 →
Application: 08/132,068 →
Multi-Voltage Compatible Bidirectional Buffer
Patent: 5,381,062 →
Application: 08/144,594 →
Composition and Method for Off-Axis Growth Sites on Nonpolar Substrates
Patent: 5,443,685 →
Application: 08/146,511 →
Integrated Circuit Fabrication with a Raised Feature as Mask
Patent: 5,439,847 →
Application: 08/147,368 →
Digital Receiver with Minimum Cost Index Register
Patent: 5,513,220 →
Application: 08/152,805 →
Digital Signal Processor
Patent: 5,454,014 →
Application: 08/152,807 →
Power and Time Saving Initial Tracebacks
Patent: 5,490,178 →
Application: 08/153,333 →
Low-Power-Dissipation Cmos Oscillator Circuits
Patent: 5,396,195 →
Application: 08/165,433 →
Variable Gain Voltage Signal Amplifier
Patent: 5,412,346 →
Application: 08/166,488 →
Method of Fabricating Semiconductor Devices and Integrated Circuits Using Sidewall Spacer Technology
Patent: 5,573,965 →
Application: 08/169,482 →
High Speed Quantization-Level-Sampling Modem with Equalization Arrangement
Patent: 5,528,625 →
Application: 08/176,742 →
Mlse Before Derotation and After Derotation
Patent: 5,724,390 →
Application: 08/205,962 →
Soft Symbol Decoding
Patent: 5,471,500 →
Application: 08/208,156 →
Integrated Circuit Clock Driver Having Improved Layout
Patent: 5,416,431 →
Application: 08/216,203 →
Process for Fabricating a Device
Patent: 5,750,312 →
Application: 08/236,706 →
Method for Interconnecting an Electronic Device Using a Removable Solder Carrying Medium
Patent: 5,591,037 →
Application: 08/251,547 →
Low Voltage Output Buffer with Improved Speed
Patent: 5,418,476 →
Application: 08/281,899 →
Masks with Low Stress Multilayer Films and a Process for Controlling the Stress of Multilayer Films
Patent: 5,500,312 →
Application: 08/321,362 →
Methodology for Monitoring Solvent Quality
Patent: 5,670,376 →
Application: 08/355,787 →
Multi-Component Electronic Devices and Methods for Making Them
Patent: 5,607,882 →
Application: 08/359,973 →
Ultra-Fast Mos Device Circuits
Patent: 5,475,345 →
Application: 08/365,857 →
In-Place Present State/Next State Registers
Patent: 5,619,514 →
Application: 08/366,195 →
Multiple Layer Tungsten Deposition Process
Patent: 5,489,552 →
Application: 08/366,529 →
Novel Barrier Layer Treatments for Tungsten Plug
Patent: 5,599,739 →
Application: 08/366,867 →
Method of Treating Metal Nitride Films to Reduce Silicon Migration Therein
Patent: 5,712,193 →
Application: 08/367,377 →
Oxynitride-Dioxide Composite Gate Dielectric Process for Mos Manufacture
Patent: 5,464,783 →
Application: 08/382,956 →
Method and Apparatus Compensating for Effects of Digital Loss Insertion in Signal Transmissions Between Modems
Patent: 5,724,393 →
Application: 08/390,185 →
Packaging Multi-Chip Modules Without Wire-Bond Interconnection
Patent: 5,608,262 →
Application: 08/393,628 →
Enhanced Rc Coupled Electrostatic Discharge Protection
Patent: 5,559,659 →
Application: 08/410,427 →
Self-Calibrating High Speed D/a Converter
Patent: 5,646,619 →
Application: 08/427,927 →
Integrated Circuit Capacitor
Patent: 5,654,581 →
Application: 08/472,033 →
Circuitry for Delivering a Signal to Different Load Elements Loacted in an Electronic System
Patent: 5,519,350 →
Application: 08/497,350 →
Doping of Silicon Layers
Patent: 5,712,176 →
Application: 08/497,470 →
Integrated Circuit with Active Devices Under Bond Pads
Patent: 5,751,065 →
Application: 08/549,990 →
Solder Medium for Circuit Interconnection
Patent: 5,618,189 →
Application: 08/588,193 →
Integrated Circuit Employing Quantized Feedback
Patent: 5,708,389 →
Application: 08/615,561 →
Process for Device Fabrication in Which a Thin Layer of Cobalt Silicide Is Formed
Patent: 5,728,625 →
Application: 08/627,560 →
Method of Integrated Circuit Fabrication Including a Step of Depositing Tungsten
Patent: 5,693,561 →
Application: 08/645,852 →
Composition for Off-Axis Growth Sites on Non-Polar Substrates
Patent: 5,668,023 →
Application: 08/676,989 →
Method of Depositing an Aluminum-Rich Layer
Patent: 5,807,760 →
Application: 08/706,932 →
Method and Apparatus for Terahertz Imaging
Patent: 5,710,430 →
Application: 08/711,823 →
Digital Processor with Viterbi Process
Patent: 5,748,650 →
Application: 08/743,925 →
Gaas-Based Mosfet, and Method of Making Same
Patent: 5,903,037 →
Application: 08/804,782 →
Method for Depositing Metal
Patent: 5,935,396 →
Application: 08/843,125 →
Near Field Terahertz Imaging
Patent: 5,894,125 →
Application: 08/912,631 →
Wireless Lan with Enhanced Capture Provision
Patent: 5,987,033 →
Application: 08/925,416 →
Related Assignments (25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignors Interest. Jan 19, 1981
From: FRASER DAVID B.; KINSBRON ELIEZER; VRATNY FREDERICK
To: BELL TELEPHONE LABORATORIES
Reel/Frame 003856/0042 →
Assignment of Assignors Interest. Mar 13, 1981
From: CHANG ROBERT P. H.
To: BELL TELEPHONE LABORATORIES, INCORPORATED
Reel/Frame 003873/0673 →
Assignment of Assignors Interest. Mar 13, 1981
From: PAYNE RICHARD S.
To: BELL TELEPHONE LABORATORIES, INCORPORATED
Reel/Frame 003873/0672 →
Assignment of Assignors Interest. Mar 27, 1981
From: ASPNES DAVID E.; STUDNA AMBROSE A.
To: BELL TELEPHONE LABORATORIES, INCORPORATED, A CORP. OF NY.
Reel/Frame 003875/0003 →
Assignment of Assignors Interest. Apr 1, 1981
From: MOYER HAROLD W.
To: WESTERN ELECTRIC COMPANY, INCORPORATED, 222 BROADWAY, NEW YORK, NY 10038, A CORP. OF NY
Reel/Frame 003877/0799 →
Assignment of Assignors Interest. Aug 24, 1981
From: LEVINSTEIN, HYMAN J.; VRATNY, FREDERICK
To: BELL TELEPHONE LABORATORIES, INCORPORATED
Reel/Frame 003912/0983 →
Assignment of Assignors Interest. Aug 24, 1981
From: MORAN, JOSEPH M.
To: BELL TELEPHONE LAORATORIES, INCORPORATED
Reel/Frame 003913/0441 →
Assignment of Assignors Interest. Aug 27, 1981
From: LEVINSTEIN, HYMAN J.; MURARKA, SHYAM P.; SINHA, ASHOK K.
To: BELL TELEPHONE LABORATORIES, INCORPORATED
Reel/Frame 003916/0068 →
Assignment of Assignors Interest. Mar 25, 1982
From: COQUIN, GERALD A.; MORAN, JOSEPH M.; TAYLOR, GARY N.
To: BELL TELEPHONE LABORATORIES, INCORPORATED
Reel/Frame 003985/0392 →
Assignment of Assignors Interest. May 7, 1982
From: HWANG, JAMES CHENG-MIN
To: BELL TELEPHONE LABORATORIES, INCORPORATED, A CORP. OF NY
Reel/Frame 003994/0697 →
Assignment of Assignors Interest. Dec 27, 1982
From: SHOJI, MASAKAZU
To: BELL TELEPHONE LABORATORIES, INCORPORATED, A CORP. OF N.Y.
Reel/Frame 004085/0323 →
Assignment of Assignors Interest. May 13, 1983
From: SWANSON, ERIC J.
To: BELL TELEPHONE LABORATORIES, INCORPORATED 600 MOUNTAIN AVE., MURRAY HILL, NJ 07974 A NY CORP.
Reel/Frame 004130/0243 →
Assignment of Assignors Interest. Aug 8, 1983
From: CAMLIBEL, IRFAN; CHIN, ALAND KWANG-YU
To: BELL TELEPHONE LABORATORIES, INCORPORATED, A NY CORP.
Reel/Frame 004163/0406 →
Assignment of Assignors Interest. Aug 11, 1983
From: SHOJI, MASAKAZU
To: BELL TELEPHONE LABORATORIES, INCORPORATED, A CORP. OF NY
Reel/Frame 004163/0012 →
Assignment of Assignors Interest. Sep 26, 1983
From: CUTHBERT, JOHN D.; SOOS, NICHOLAS A.
To: BELL TELEPHONE LABORATORIES, INCORPORATED, A NY CORP.
Reel/Frame 004179/0563 →
Assignment of Assignors Interest. Oct 4, 1983
From: GANESAN, APPARAJAN
To: WESTERN ELECTRIC COMPANY, INCORPORATED, A NY CORP.
Reel/Frame 004184/0067 →
Assignment of Assignors Interest. Oct 4, 1983
From: BEALE, RICHARD G.; GANESAN, APPARAJAN
To: BELL TELEPHONE LABORATORIES, INCORPORATED, A NY CORP.
Reel/Frame 004184/0066 →
Assignment of Assignors Interest. Dec 2, 1983
From: KO, PING K.
To: BELL TELEPHONE LABORATORIES, INCORPORATED, 600 MOUNTAIN AVE., MURRAY HILL, NJ 07974 A NY CORP.
Reel/Frame 004203/0846 →
Assignment of Assignors Interest. Dec 30, 1983
From: COX, HERBERT M.
To: BELL TELEPHONE LABORATORIES, INCORPORATED
Reel/Frame 004219/0488 →
Change of Name Effective Jan. 3,1984 Mar 19, 1984
From: WESTERN ELECTRIC COMPANY, INCORPORATED
To: AT & T TECHNOLOGIES, INC.,
Reel/Frame 004251/0868 →
Assignment of Assignors Interest. Apr 9, 1984
From: LANCASTER, LOREN T.
To: BELL TELEPHONE LABORATORIES, INCORPORATED A CORP OF NEW YORK
Reel/Frame 004247/0873 →
Assignment of Assignors Interest. Apr 23, 1984
From: TAI, KING L.
To: BELL TELEPHONE LABORATORES, INCORPORATED
Reel/Frame 004279/0573 →
Assignment of Assignors Interest. Aug 30, 1984
From: LEE, KUO-HUA
To: BELL TELEPHONE LABORATORIES, INCORPORATED A CORP OF NEW YORK
Reel/Frame 004308/0570 →
Conditional Assignment of and Security Interest in Patent Rights Apr 5, 2001
From: AGERE SYSTEMS GUARDIAN CORP. (DE CORPORATION)
To: CHASE MANHATTAN BANK, AS ADMINISTRATIVE AGENT, THE
Reel/Frame 011667/0148 →
Security Agreement Oct 3, 2002
From: SYCHIP, INC.
To: SILICON VALLEY BANK
Reel/Frame 013305/0798 →