IP Library › Assignment 016602/0895
Patent Assignment
Reel/Frame 016602/0895

Release of Security Interest

Recorded: 2005-04-28 Pages: 83
Assignor
LEHMAN COMMERICAL PAPER INC.
Executed: 2005-01-07
Assignees
SYMBIOS, INC.
2001 DANFIELD CT., FORT COLLINS, COLORADO, 80525
HYUNDAI ELECTRONICS AMERICA
3101 NORTH FIRST STREET, SAN JOSE, CALIFORNIA, 95134
Covered Properties (352)
Device Having Implantation for Controlling Gate Parasitic Action
Patent: 4,454,524 →
Application: 05/884,060 →
Narrow Channel Fet Device and Method for Making
Patent: 4,212,683 →
Application: 05/890,425 →
Alignment Film for a Liquid Crystal Display Cell and Method of Making Same
Patent: 4,165,923 →
Application: 05/931,583 →
Character Position Control for a Matrix Printer
Patent: 4,247,214 →
Application: 05/958,856 →
Cisfet Processingg Including Simultaneous Doping of Silicon Components and Fet Channels
Patent: 4,212,684 →
Application: 05/962,423 →
High Density Rom Cell
Patent: 4,192,014 →
Application: 05/962,572 →
Input-Keep Alive Arrangement for Plasma Charge Transfer Device
Patent: 4,233,544 →
Application: 06/037,586 →
Random Access Memory Imaging System
Patent: 4,344,091 →
Application: 06/040,009 →
Topography for Integrated Circuit Pattern Recognition Array
Patent: 4,287,507 →
Application: 06/043,929 →
Topography for Integrated Circuit Pattern Recognition Array
Patent: 4,275,380 →
Application: 06/043,930 →
Ribbon Cassette with Bi-Color Capability
Patent: 31,117 →
Application: 06/059,864 →
Multiline Charge Transfer Panel Input and Hold System
Patent: 4,283,660 →
Application: 06/069,158 →
Apparatus for Advancing a Record Medium
Patent: 4,279,524 →
Application: 06/076,055 →
Narrow Channel Fet Device and Method for Making
Patent: 4,485,390 →
Application: 06/080,828 →
Latching Schmitt Trigger Circuit
Patent: 4,301,379 →
Application: 06/085,827 →
Static Volatile/Non-Volatile Ram Cell
Patent: 4,271,487 →
Application: 06/093,780 →
Method and Circuitry for Synchronizing the Read and Update Functions of a Timer/Counter Circuit
Patent: 4,341,950 →
Application: 06/114,925 →
Associative Memory System
Patent: 4,376,974 →
Application: 06/135,792 →
Cursor for Plasma Shift Register Display
Patent: 4,336,535 →
Application: 06/140,649 →
Polysilicon-To-Substrate Contact Processing
Patent: 4,305,760 →
Application: 06/177,307 →
Ac Drive System for Plasma Display Panels
Patent: 4,346,379 →
Application: 06/177,329 →
Method and Apparatus for Selecting Elements
Patent: 4,361,858 →
Application: 06/180,220 →
Low Voltage Nonvolatile Memory Device
Patent: 4,353,083 →
Application: 06/192,977 →
Method for Fabricating an Integrated Circuit
Patent: 4,345,365 →
Application: 06/194,658 →
Method for Conditioning Nitride Surface
Patent: 4,330,569 →
Application: 06/195,806 →
Self-Aligned All-N Polysilicon Cmos Process
Patent: 4,345,366 →
Application: 06/198,428 →
Method of Plasmac Ii Drive to Reduce Flash and Create Dimming
Patent: 4,350,932 →
Application: 06/198,562 →
Ball Bearing Slide
Patent: 4,348,063 →
Application: 06/219,758 →
Earom Cell Matrix and Logic Arrays with Common Memory Gate
Patent: 4,380,804 →
Application: 06/220,644 →
Mos Sense Amplifier
Patent: 4,412,143 →
Application: 06/247,683 →
Silicon Nitride S/D Ion Implant Mask in Cmos Device Fabrication
Patent: 4,382,827 →
Application: 06/258,189 →
Write/Restore/Erase Signal Generator for Volatile/Non-Volatile Memory System
Patent: 4,405,868 →
Application: 06/272,605 →
High Speed Write Control for Synchronous Registers
Patent: 4,409,680 →
Application: 06/296,753 →
End Point Detection Using Gas Flow
Patent: 4,345,968 →
Application: 06/296,754 →
Method of Making Coplanar Mos Ic Structures
Patent: 4,372,033 →
Application: 06/300,318 →
Method for Making Low Leakage Polyorystlline Silicon-to-Subatrate Contacts
Patent: 4,397,076 →
Application: 06/301,557 →
Clipped Speech-Linear Predictive Coding Speech Processor
Patent: 4,477,925 →
Application: 06/329,776 →
Thermoelctric (Peltier Effect) Hot/Cold Socket for Packaged I. C. Microprobing
Patent: 4,402,185 →
Application: 06/337,786 →
Mixed Dielectric Process and Nonvolatile Memory Device Fabricated Thereby
Patent: 4,534,104 →
Application: 06/352,734 →
Image Pick-Up Tube Arrangement
Patent: 4,488,085 →
Application: 06/360,436 →
Transparent Instruction Word Bus Memory System
Patent: 4,520,464 →
Application: 06/383,869 →
Method of Making Cmos by Twin-Tub Process Integrated with a Vertical Bipolar Transistor
Patent: 4,507,847 →
Application: 06/391,068 →
Process for Forming Mnos Dual Dielectric Structure
Patent: 4,438,157 →
Application: 06/396,995 →
Precision Ic Alignment Keys and Method
Patent: 4,523,851 →
Application: 06/407,204 →
Epitaxial Contact Fabrication Process
Patent: 4,464,824 →
Application: 06/409,193 →
Method of Making Cmos Device and Contacts Therein by Enhanced Oxidation of Selectively Implanted Regions
Patent: 4,470,852 →
Application: 06/414,737 →
Priority Interrupt System for Microcomputer
Patent: 4,523,277 →
Application: 06/429,580 →
High Voltage Pass Circuit
Patent: 4,527,074 →
Application: 06/433,292 →
Integrated Circuit Dual Polarity High Voltage Multiplier for Extended Operating Temperature Range
Patent: 4,485,433 →
Application: 06/452,239 →
Method of Fabricating Zener Diodes
Patent: 4,473,941 →
Application: 06/452,343 →
Method of Reworking Upper Metal in Multilayer Metal Integrated Circuits
Patent: 4,415,606 →
Application: 06/456,689 →
X-And-Or Memory Array
Patent: 4,602,354 →
Application: 06/456,938 →
System and Method for Stabilizing Asynchronous State Machines
Patent: 4,562,427 →
Application: 06/461,905 →
Oxide Trench Structure for Polysilicon Gates and Interconnects
Patent: 4,503,601 →
Application: 06/486,275 →
Paging Register for Memory Devices
Patent: 4,613,953 →
Application: 06/487,554 →
Recrystallized Silicon-on-Insulator Nonvolatile Memory Device
Patent: 4,876,582 →
Application: 06/490,743 →
Unified Cmos/Snos Semiconductor Fabrication Process
Patent: 4,516,313 →
Application: 06/499,044 →
Metal Bevel Process for Multi-Level Metal Semiconductor Applications
Patent: 4,425,183 →
Application: 06/521,509 →
Process for Fabricating a Bipolar Transistor with a Thin Base and an Abrupt Base-Collector Junction
Patent: 4,523,370 →
Application: 06/558,252 →
Device for Focusing a Laser on a Recording Medium by Wavelength Modulation
Patent: 4,595,810 →
Application: 06/571,886 →
Fault Tolerant Memory
Patent: 4,692,923 →
Application: 06/655,854 →
Direct-Write Silicon Nitride Eeprom Cell
Patent: 4,616,245 →
Application: 06/665,874 →
Method for Forming Trench Isolation Structures
Patent: 4,571,819 →
Application: 06/667,181 →
Twin Well Single Mask Cmos Process
Patent: 4,584,027 →
Application: 06/669,275 →
Process for Forming Retrograde Dopant Distributions Utilizing Simultaneous Outdiffusion of Dopants
Patent: 4,578,128 →
Application: 06/677,636 →
Method for Forming Channel Stops in Vertical Semiconductor Surfaces
Patent: 4,666,557 →
Application: 06/680,034 →
Fet Driver Circuit with Mask Programmable Transition Rates
Patent: 4,634,893 →
Application: 06/705,296 →
Current Sinking Responsive Mos Sense Amplifier
Patent: 4,636,664 →
Application: 06/705,298 →
Method of Making Laser Recrystallized Silicon-Insulator Nonvolatile Memory Device
Patent: 4,619,034 →
Application: 06/710,192 →
Digitally Compensated Multiplying Digital to Analog Converter
Patent: 4,779,029 →
Application: 06/710,658 →
Negative Input Voltage Cmos Circuit
Patent: 4,647,798 →
Application: 06/723,016 →
Two Bit Vertically/Horizontally Integrated Memory Cell
Patent: 4,667,217 →
Application: 06/725,039 →
Method for Forming Trench Isolation Structures
Patent: 4,576,834 →
Application: 06/735,515 →
Method of Making an Imaging Array Having Higher a Sensitivity
Patent: 4,658,497 →
Application: 06/740,719 →
Use of Selectively Deposited Tungsten for Contact Formation and Shunting Metallization
Patent: 4,648,175 →
Application: 06/743,849 →
Binary Autocorrelation Processor
Patent: 4,860,357 →
Application: 06/762,234 →
Pocket Calculator with Credit Card Controller and Dispenser
Patent: 4,719,338 →
Application: 06/764,903 →
Method of Fabricating a High Density, Low Power Merged Vertical Fuse/Biopolar Transisitor
Patent: 4,651,409 →
Application: 06/771,855 →
High Speed Master-Slave Flip-Flop
Patent: 4,656,368 →
Application: 06/775,928 →
Common Cell I/O Interface Circuit
Patent: 4,745,305 →
Application: 06/779,379 →
Amplitude Enhanced Sampled Clipped Speech Encoder and Decoder
Patent: 5,136,652 →
Application: 06/798,057 →
Two Mask Technique for Planarized Trench Oxide Isolation of Integrated Devices
Patent: 4,753,901 →
Application: 06/798,511 →
High Speed Counter with Decoding Means and Means for Selecting Second and Higher Order Counter Stages to Be Toggled
Patent: 4,669,101 →
Application: 06/808,984 →
Totally Self-Aligned Cmos Process
Patent: 4,701,423 →
Application: 06/811,187 →
Asynchronous Fifo Status Circuit
Patent: 4,694,426 →
Application: 06/811,851 →
Non-Destructive Method and Circuit to Determine the Programmability of a One Time Programmable Device
Patent: 4,718,042 →
Application: 06/811,983 →
Formation and Planarization of Silicon-on-Insulator Structures
Patent: 4,604,162 →
Application: 06/812,531 →
Trench Filling and Planarization Process
Patent: 4,671,970 →
Application: 06/826,402 →
Fabrication Process for Aligned and Stacked Cmos Devices
Patent: 4,654,121 →
Application: 06/833,686 →
Cmos Memory Margining Control Circuit for a Nonvolatile Memory
Patent: 4,658,380 →
Application: 06/834,995 →
Programmable Read Only Memory Using a Tungsten Fuse
Patent: 4,647,340 →
Application: 06/846,395 →
Circuit for Initiating Test Modes
Patent: 4,714,876 →
Application: 06/851,620 →
Digital System and Method for Compressing Speech Signals for Storage and Transmission
Patent: 4,802,221 →
Application: 06/887,492 →
Nonvolatile Multiconfifurable Circuit
Patent: 4,754,432 →
Application: 06/889,543 →
Formation of Self-Aligned Stacked Cmos Structures by Lift-Off
Patent: 4,679,299 →
Application: 06/895,407 →
Two Transistor Full Wave Rectifier
Patent: 4,875,151 →
Application: 06/895,408 →
High Speed Nonvolatile Memory Cell
Patent: 4,748,593 →
Application: 06/904,586 →
Shared Line Direct Write Nonvolatile Memory Cell Array
Patent: 4,769,788 →
Application: 06/910,053 →
Fiber Optic Coupling System
Patent: 4,798,428 →
Application: 06/918,744 →
Mosfet Process Using Implantation Through Silicon
Patent: 4,682,404 →
Application: 06/922,221 →
Method and Apparatus for Encoding and Decoding Speech Signal Primary Information
Patent: 4,817,154 →
Application: 06/939,971 →
Digitally Controlled Delay Circuit
Patent: 5,111,085 →
Application: 07/043,778 →
Driver Circuit Providing Load and Time Adaptive Current
Patent: 4,829,199 →
Application: 07/072,831 →
Cmos Integrated Devices in Seeded Islands
Patent: 4,799,097 →
Application: 07/078,959 →
Multiple Photoresist Layer Process Using Selective Hardening
Patent: 4,859,573 →
Application: 07/089,014 →
Digital Data Bus Architecture for Computer Disk Drive Controller
Patent: 4,866,601 →
Application: 07/100,498 →
Synchronizer Circuit with Asynchronous Clearing
Patent: 5,012,127 →
Application: 07/100,499 →
Method and Apparatus for Controlling Data Transfers Through Multiple Buffers
Patent: 4,843,544 →
Application: 07/101,354 →
Architectural Arrangement for a Scsi Disk Controller Integrated Circuit
Patent: 4,965,801 →
Application: 07/101,452 →
Compact Register Set Using a Psram Array
Patent: 4,870,616 →
Application: 07/102,075 →
Surface Mount Electronic Device Package
Patent: 4,754,880 →
Application: 07/103,563 →
Native Oxide Reduction for Sealing Nitride Deposition
Patent: 4,855,258 →
Application: 07/111,377 →
Logical Drawing and Transparency Circuits for Bit Mapped Video Display Controllers
Patent: 4,893,116 →
Application: 07/120,902 →
Isolation of Regions in a Cmos Structure Using Selective Epitaxial Growth
Patent: 4,820,654 →
Application: 07/130,481 →
Nonvolatile Electronic Odometer with Excess Write Cycle Protection
Patent: 4,803,707 →
Application: 07/135,200 →
Self-Correcting Digitally Controlled Timing Circuit
Patent: 4,868,430 →
Application: 07/154,768 →
Digitally Compensated Multiplying Digital to Analog Converter
Patent: 4,920,344 →
Application: 07/205,046 →
Low Noise Output Buffer Circuit
Patent: 4,880,997 →
Application: 07/233,506 →
Bandgap Voltage Reference Including a Process and Temperature Insensitive Start-Up Circuit and Power-Down Capability
Patent: 4,857,823 →
Application: 07/248,218 →
A Method of Making Cmos Integrated Devices in Seeded Islands
Patent: 4,997,780 →
Application: 07/248,265 →
Method for Providing an Improved Human User Interface to a Knowledge Based System
Patent: 4,965,741 →
Application: 07/258,961 →
Method for Forming Epitaxial Silicon on Insulator Structures Using Oxidized Porous Silicon
Patent: 4,910,165 →
Application: 07/267,899 →
Buffer Circuit with Load Sensitive Transition Control
Patent: 4,906,867 →
Application: 07/269,022 →
Multiple Port Bus Interface Controller with Slave Bus
Patent: 4,935,868 →
Application: 07/276,602 →
Random Access Memory Device with Integral Logic Capability
Patent: 5,023,838 →
Application: 07/279,606 →
Digital Frequency Divider
Patent: 4,991,188 →
Application: 07/282,547 →
Matched Current Source Serial Bus Driver
Patent: 4,890,010 →
Application: 07/288,655 →
Control Method and Apparatus for Controlling the Data Flow Rate in a Fifo Memory, for Synchronous Scsi Data Transfers
Patent: 5,237,660 →
Application: 07/289,859 →
High Frequency Integrated Circuit Channel Capacitor
Patent: 4,866,567 →
Application: 07/294,154 →
Gate Isolated Base Cell Structure with Off-Grid Gate Polysilicon Pattern
Patent: 4,928,160 →
Application: 07/297,355 →
Bus Executed Scan Testing Method and Apparatus
Patent: 4,947,395 →
Application: 07/308,917 →
Activity Display Panel for a Data Processor or the Like
Patent: 316,708 →
Application: 07/322,819 →
Method of Making Asymmetrically Optimized Cmos Field Effect Transistors
Patent: 4,874,713 →
Application: 07/345,875 →
Semiconductor Field Oxide Formation Process Using a Sealing Sidewall of Consumable Nitride
Patent: 4,923,563 →
Application: 07/356,591 →
Gate Isolated I.O Cell Architecture for Diverse Pad and Drive Configurations
Patent: 4,975,758 →
Application: 07/360,691 →
Integrated Controller Using Alternately Filled and Emptied Buffers for Controlling Bi-Directional Data Transfer Between a Processor and a Data Storage Device
Patent: 5,163,132 →
Application: 07/363,352 →
Memory Control System and Method
Patent: 5,283,763 →
Application: 07/410,773 →
Clock Generating Circuit for Asynchronous Pulses
Patent: 4,968,906 →
Application: 07/412,030 →
Base for Stackable Assemblies
Patent: 4,996,628 →
Application: 07/423,914 →
Method and Apparatus for Bus Executed Boundary Scanning
Patent: 5,115,435 →
Application: 07/423,924 →
Ac Power Interconnect for Stacked Electronic Devices
Patent: 4,950,178 →
Application: 07/424,049 →
Enclosure for Electronic Equipment
Patent: 329,640 →
Application: 07/424,837 →
Current Limiting Output Driver
Patent: 4,962,345 →
Application: 07/432,260 →
Arbitration Apparatus for a Parallel Bus
Patent: 5,081,578 →
Application: 07/432,422 →
Circuit and Method for Regulating the Current Flow in a Distributorless Ignition System Coil
Patent: 5,043,633 →
Application: 07/435,308 →
Nonvolatile Differential Memory Device and Method
Patent: 5,168,464 →
Application: 07/442,809 →
Supply Connection Integrity Monitor
Patent: 5,077,521 →
Application: 07/456,759 →
Integrated Circuit Driver for Serial Bus Having Output Over Voltage Protection
Patent: 5,019,720 →
Application: 07/491,795 →
Structure and Process for Forming Semiconductor Field Oxide Using a Sealing Sidewall of Consumable Nitride
Patent: 4,986,879 →
Application: 07/496,567 →
Process for Forming Self-Aligned Titanium Silicide by Heating in an Oxygen Rich Environment
Patent: 5,288,666 →
Application: 07/496,720 →
Low Current Driver for Gate Array
Patent: 5,029,283 →
Application: 07/500,621 →
Process for Forming Titanium Silicide Local Interconnect
Patent: 5,443,996 →
Application: 07/522,775 →
High Frequency Asynchronous Data Synchronizer
Patent: 5,047,658 →
Application: 07/532,005 →
High Accuracy Analog-to-Digital Converter with Rail-to-Rail Reference and Input Voltage Ranges
Patent: 5,016,014 →
Application: 07/538,354 →
Bit Mapped Color Cursor
Patent: 5,146,211 →
Application: 07/566,014 →
High Speed Cmos Flip-Flop Employing Clocked Tristate Inverters
Patent: 5,140,180 →
Application: 07/572,596 →
Sample-And-Hold Switch with Low on Resistance and Reduced Charge Injection
Patent: 5,111,072 →
Application: 07/574,176 →
Transient Immune Input Buffer
Patent: 5,041,741 →
Application: 07/582,461 →
Coating Solution for Forming Glassy Layers
Patent: 5,302,198 →
Application: 07/582,570 →
Single Element Security Fusible Link
Patent: 5,270,983 →
Application: 07/582,705 →
High Density Input/Output Cell Arrangement for Integrated Circuits
Patent: 5,063,429 →
Application: 07/583,754 →
Apparatus for Arbitrating for a High Speed Direct Memory Access Bus
Patent: 5,471,639 →
Application: 07/602,610 →
High Speed Data Synchronizer
Patent: 5,132,990 →
Application: 07/608,854 →
Method for Scheduling the Execution of Disk I/O Operations
Patent: 5,644,786 →
Application: 07/610,633 →
Method and Apparatus for Controlling Noise on Power Supply Buses
Patent: 5,059,822 →
Application: 07/617,846 →
Structure for Improving Gate Oxide Integrity for a Semiconductor Formed by a Recessed Sealed Sidewall Field Oxidation Process
Patent: 5,248,350 →
Application: 07/622,107 →
Method of Estimating Logic Cell Delay Time
Patent: 5,274,568 →
Application: 07/623,310 →
Low Power Pseudo-Static Rom
Patent: 5,226,014 →
Application: 07/633,733 →
Silica-Based Anti-Reflective Planarizing Layer
Patent: 5,100,503 →
Application: 07/637,903 →
Drive Canister Mounting Module
Patent: 5,124,886 →
Application: 07/659,771 →
Method and Apparatus for Generating Disk Array Interrupt Signals
Patent: 5,179,704 →
Application: 07/668,641 →
Multiple Configuration Data Path Architecture for a Disk Array Controller
Patent: 5,345,565 →
Application: 07/668,660 →
Bus Configuration Validation for a Multiple Source Disk Array Bus
Patent: 5,430,747 →
Application: 07/669,554 →
Trinary to Binary Level Conversion Circuit
Patent: 5,045,728 →
Application: 07/683,581 →
Electrical Connection Between Buses on a Semiconductor Integrated Circuit
Patent: 5,185,652 →
Application: 07/706,428 →
Method for Designing a Scan Path for a Logic Circuit and Testing of the Same
Patent: 5,291,495 →
Application: 07/729,282 →
Spin-On Glass Composition
Patent: 5,152,834 →
Application: 07/732,009 →
Disk Controller Having Host Interface and Bus Switches for Selecting Buffer and Drive Busses Respectively Based on Configuration Control Signals
Patent: 5,257,391 →
Application: 07/746,399 →
Voltage Variable Delay Circuit
Patent: 5,231,319 →
Application: 07/749,006 →
Battery Back-Up for Electronic Circuits
Patent: 5,608,273 →
Application: 07/796,992 →
Ttl Compatible Input Buffer
Patent: 5,276,361 →
Application: 07/796,993 →
Detection of Tri-State Logic Signals
Patent: 5,432,440 →
Application: 07/796,995 →
Bufferless Scsi to Scsi Data Transfer Scheme for Disk Array Applications
Patent: 5,287,462 →
Application: 07/811,481 →
Device and Method for Approximating the Square Root of a Number
Patent: 5,268,857 →
Application: 07/818,302 →
Memory Security Device
Patent: 5,233,563 →
Application: 07/820,170 →
Connection System for Integrated Circuits
Patent: 5,288,949 →
Application: 07/829,838 →
Semiconductor Fuse Structure
Patent: 5,376,820 →
Application: 07/832,177 →
Method and Apparatus for Generating Reed-Solomon Error Correcting Code Across Multiple Word Boundaries
Patent: 5,375,127 →
Application: 07/856,613 →
Method and Apparatus for Synchronizing Disk Drive Requests Within a Disk Array
Patent: 5,375,217 →
Application: 07/857,539 →
Mos Amplifier with Gain Control
Patent: 5,455,816 →
Application: 07/885,711 →
Cmos Circuit for Receiving Ecl Signals
Patent: 5,283,482 →
Application: 07/909,266 →
Multi-Chip Module with Multiple Compartments
Patent: 5,369,552 →
Application: 07/913,100 →
High Speed Current/Voltage Controlled Ring Oscillator Circuit
Patent: 5,300,898 →
Application: 07/921,157 →
Semiconductor Fuse and Method
Patent: 5,672,905 →
Application: 07/935,306 →
Repeatedly Programmable Logic Array Using Dynamic Access Memory
Patent: 5,432,388 →
Application: 07/935,945 →
Balanced Voltage Comparator
Patent: 5,287,070 →
Application: 07/939,225 →
Cmos Driver for Fast Single-Ended Bus
Patent: 5,576,640 →
Application: 07/952,674 →
Controllable Multi-Phase Ring Oscillators with Variable Current Sources and Capacitances
Patent: 5,302,920 →
Application: 07/959,868 →
Selective Sidewall Diffusion Process Using Doped Sog
Patent: 5,308,790 →
Application: 07/961,967 →
Method for Forming a Bipolar Emitter Using Doped Sog
Patent: 5,322,805 →
Application: 07/961,973 →
Reluctance Sensor Having Variable Thresholde Detection Circuit
Patent: 5,446,375 →
Application: 07/961,974 →
Phase-And-Frequency Mode/Phase Mode Detector with the Same Gain in Both Modes
Patent: 5,307,028 →
Application: 07/961,975 →
Global Planarization Using Sog and Cmp
Patent: 5,312,512 →
Application: 07/965,309 →
Method of Making a Shallow Junction by Using First and Second Sog Layers
Patent: 5,340,770 →
Application: 07/965,822 →
Method for Forming a Bipolar Transistor Using Doped Sog
Patent: 5,340,752 →
Application: 07/965,823 →
Delayed Initiation of Read-Modify-Write Parity Operations in a Raid Level 5 Disk Array
Patent: 5,388,108 →
Application: 07/966,106 →
Fast Write I/O Handling in a Disk Array Using Spare Drive for Buffering
Patent: 5,418,925 →
Application: 07/966,107 →
Method and Device for Processing Multiple, Asynchronous Interrupt Signals
Patent: 5,584,028 →
Application: 07/966,620 →
Concurrent Image Backup for Disk Storage System
Patent: 5,487,160 →
Application: 07/985,710 →
Threshold Controlled Input Circuit for an Integrated Circuit
Patent: 5,341,046 →
Application: 07/986,184 →
Method and Apparatus for a Dynamic, Timed-Loop Arbitration
Patent: 5,301,332 →
Application: 07/995,731 →
Terminating Access of an Agent to a Shared Resource When a Timer, Started After a Low Latency Agent Requests Access, Reaches a Predetermined Value
Patent: 5,506,968 →
Application: 07/996,992 →
Multi-Chip Module Board
Patent: 5,303,121 →
Application: 07/996,993 →
Apparatus and Method for Matching Data Rates to Transfer Data Between Two Asynchronous Devices
Patent: 5,592,629 →
Application: 07/997,426 →
Solid-State Ink-Jet Print Head
Patent: 5,459,501 →
Application: 08/011,592 →
System and Method for Transferring Data Between Independent Busses
Patent: 5,455,913 →
Application: 08/068,582 →
Array Storage System for Returning an I/O Complete Signal to a Virtual I/O Daemon That Is Separated from Software Array Driver and Physical Device Driver
Patent: 5,598,549 →
Application: 08/076,652 →
Fast Cmos Charge Pump Circuit
Patent: 5,363,066 →
Application: 08/078,880 →
Method and Apparatus for Pseudo-Aligned Transfers of Data to Memory Wherein a Re-Alignment Is Performed Based on the Data Byte Control Header
Patent: 5,680,642 →
Application: 08/082,862 →
Multiclock Controller
Patent: 5,587,675 →
Application: 08/105,990 →
Single Element Security Fusible Link
Patent: 5,309,394 →
Application: 08/118,161 →
Structure and Method for Remotely Measuring Process Data
Patent: 5,466,614 →
Application: 08/123,664 →
Voltage-To-Current Converter Without Series Sensing Resistor
Patent: 5,519,310 →
Application: 08/125,267 →
Cmos Power Fet Driver Including Multiple Power Mosfet Transistors Connected in Parallel, Each Carrying an Equivalent Portion of the Total Driver Current
Patent: 5,442,218 →
Application: 08/128,428 →
Lightly Doped Drain Ballast Resistor
Patent: 5,498,892 →
Application: 08/129,231 →
Method for Partitioning Disk Drives Within a Physical Disk Array and Selectively Assigning Disk Drive Partitions into a Logical Disk Array
Patent: 5,568,629 →
Application: 08/148,031 →
Multi-Chip Module Packaging System
Patent: 5,497,027 →
Application: 08/159,898 →
Method and Apparatus for Calculating Dynamic Power Dissipation in Cmos Integrated Circuits
Patent: 5,521,834 →
Application: 08/159,976 →
Method for Using Low Dielectric Constant Material in Integrated Circuit Fabrication
Patent: 5,438,022 →
Application: 08/165,872 →
Current Limited Output Driver for a Gate Array Circuit
Patent: 5,444,401 →
Application: 08/198,656 →
Multi-Phase Charge Sharing Method and Apparatus
Patent: 5,574,633 →
Application: 08/200,612 →
Synchronous Telemetry Channel
Patent: 5,608,390 →
Application: 08/200,721 →
Coating Solution for Forming Glassy Layers
Patent: 5,472,488 →
Application: 08/210,386 →
Electronic Device with a Spin-on Glass Dielectric Layer
Patent: 5,527,872 →
Application: 08/214,477 →
Integrated Circuit Oscillator with High Voltage Feedback Network
Patent: 5,457,434 →
Application: 08/221,346 →
Method for Forming an Amorphous Silicon Programmable Element
Patent: 5,447,880 →
Application: 08/224,609 →
Aspiration Needle and Syringe for Use Therewith, Apparatus Incorporating the Same and Kit for Use in Fine Needle Aspiration Cytology, and Method
Patent: 5,645,537 →
Application: 08/228,551 →
Differential Analog Transistors Constructed from Digital Transistors
Patent: 5,488,249 →
Application: 08/239,166 →
Method and Apparatus for Separating Data and Clock from a Digital Data Stream
Patent: 5,598,443 →
Application: 08/247,386 →
Multi-Device Adapter Card for Computer
Patent: 5,577,213 →
Application: 08/253,530 →
Electrostatic Discharge Protection System for Mixed Voltage Application Specific Integrated Circuit Design
Patent: 5,616,943 →
Application: 08/259,240 →
Multi-Range Voltage Controlled Oscillator
Patent: 5,559,473 →
Application: 08/264,815 →
Extendible-Range Voltage Controlled Oscillator
Patent: 5,477,198 →
Application: 08/264,863 →
Elevated Emitter for Double Poly Bicmos Devices
Patent: 5,557,131 →
Application: 08/275,094 →
Compensation of Stylus Signals in Digitizing Tablet
Patent: 6,005,200 →
Application: 08/286,720 →
Polysilicon Fuse Array Structure for Integrated Circuits
Patent: 5,536,968 →
Application: 08/291,326 →
Multi-Chip Module with Multiple Compartments
Patent: 5,480,840 →
Application: 08/292,448 →
A Method and Apparatus for Reducing Current Consumption in a Cmos Inverter Circuit
Patent: 5,491,429 →
Application: 08/307,111 →
Supply Voltage Tolerant Phase-Locked Loop Circuit
Patent: 5,463,352 →
Application: 08/311,469 →
5-Volt Tolerant Bi-Directional I/O Pad for 3-Volt-Optimized Integrated Circuits
Patent: 5,528,447 →
Application: 08/315,799 →
Noise Cancellation for Non-Ideal Electrostatic Shielding `
Patent: 5,574,262 →
Application: 08/317,952 →
Circuit and Method for Generating a Clock Signal
Patent: 5,477,180 →
Application: 08/320,361 →
Method and Apparatus for Managing Video Data for Faster Access by Selectively Caching Video Data
Patent: 5,581,731 →
Application: 08/323,420 →
High-Frequency Phase Locked Loop Circuit
Patent: 5,675,620 →
Application: 08/329,367 →
Method of Making Bi-Cmos Integrated Circuit Having a Polysilicon Emitter
Patent: 5,516,718 →
Application: 08/331,235 →
Color Image Array Scanner with High Resolution Monochrome Mode
Patent: 5,521,640 →
Application: 08/332,272 →
Signal Generator with Supply Voltage Tolerance
Patent: 5,677,642 →
Application: 08/333,014 →
Wall Outlet with Direct Current Output
Patent: 5,563,782 →
Application: 08/337,591 →
Communications Transceiver Using an Adaptive Directional Antenna
Patent: 5,617,102 →
Application: 08/342,328 →
Cmos Disk Drive Motor Control Circuit Having Back-Emf Regulator Circuitry
Patent: 5,600,217 →
Application: 08/343,275 →
Method and Apparatus for Polymer Coating of Substrates
Patent: 5,545,440 →
Application: 08/349,640 →
Process for Forming Titanium Silicide Local Interconnect
Patent: 5,543,361 →
Application: 08/351,843 →
Peripheral Component Interfacing System with Bus Voltage/Logic Supply Comparison Means
Patent: 5,469,082 →
Application: 08/352,331 →
Mixed Format Video Ram
Patent: 5,644,336 →
Application: 08/355,413 →
Disk Array Storage System Architecture for Parity Operations Simultaneous with Other Data Operations
Patent: 5,634,033 →
Application: 08/357,847 →
Method for Maintaining Parity-Data Consistency in a Disk Array
Patent: 5,533,190 →
Application: 08/360,198 →
Data Compression in Digitizing Tablet
Patent: 5,668,352 →
Application: 08/360,527 →
Method and Apparatus for Determining and Maintaining Drive Status from Codes Written to Disk Drives of an Arrayed Storage Subsystem
Patent: 5,644,767 →
Application: 08/385,387 →
High Speed Boundary Scan Multiplexer
Patent: 5,519,355 →
Application: 08/389,427 →
Memory with Latched Output
Patent: 5,526,310 →
Application: 08/389,429 →
High Speed, Low Power Input/Output Circuit for a Multi-Chip Module
Patent: 5,481,207 →
Application: 08/427,916 →
Method for Transferring Data Between Two Devices That Insures Data Recovery in the Event of a Fault
Patent: 5,588,110 →
Application: 08/447,377 →
Sea-Of-Cells Array of Transistors
Patent: 5,671,397 →
Application: 08/455,503 →
Method for Manufacturing a Monitor Element
Patent: 5,576,224 →
Application: 08/460,287 →
A Method for Making a Solid-State Ink Jet Print Head
Patent: 5,581,861 →
Application: 08/460,485 →
Method for Performing on-Line Reconfiguration of a Disk Array Concurrent with Execution of Disk I/O Operations
Patent: 5,574,851 →
Application: 08/482,425 →
Analog Output Driver for Gate Arrays
Patent: 5,541,548 →
Application: 08/484,197 →
Differential Analog Transistors Constructed from Digital Transistors
Patent: 5,610,429 →
Application: 08/517,641 →
Cmos Disk Drive Motor Control Circuit Having Back-Emf Blocking Circuitry
Patent: 5,521,476 →
Application: 08/521,374 →
System for Testing the Functionality of Video Card and Monitor by Using Program to Enable User to View List of Modes and Select Compatible Mode
Patent: 5,581,788 →
Application: 08/535,364 →
Data Storage Device Matrix Architecture
Patent: 5,550,986 →
Application: 08/539,663 →
I/O System for Reducing Main Processor Overhead in Initiating I/O Requests and Servicing I/O Completion Events
Patent: 5,671,365 →
Application: 08/546,003 →
5 Volt Driver in a 3 Volt Cmos Process
Patent: 5,684,415 →
Application: 08/575,793 →
Method for Polishing a Wafer
Patent: 5,645,736 →
Application: 08/580,674 →
Method and Apparatus for the Protection of Write Data in a Disk Array
Patent: 5,596,708 →
Application: 08/591,366 →
Architectural Arrangement for a Video Server
Patent: 5,625,405 →
Application: 08/603,694 →
Electronic Device with a Spin-on Glass Dielectric Layer
Patent: 5,665,845 →
Application: 08/609,589 →
Universal Power Interface Adapter for Burn-in Board
Patent: 5,672,981 →
Application: 08/614,925 →
Linearization Method and Apparatus for Voltage Controlled Oscillator
Patent: 5,748,050 →
Application: 08/625,452 →
Decision Based Time-Varying Equalizers
Patent: 6,437,932 →
Application: 08/648,849 →
Method for Fabricating a Low Trigger Voltage Silicon Controlled Rectifier and Thick Field Device
Patent: 5,966,599 →
Application: 08/651,018 →
High Speed Clock Recovery Circuit Using Complimentary Dividers
Patent: 5,953,386 →
Application: 08/667,150 →
Reduced Skew Differential Receiver
Patent: 5,801,564 →
Application: 08/671,850 →
Meta-Hardened Flip-Flop
Patent: 5,999,029 →
Application: 08/671,862 →
Method and System for Recovering Digital Data from a Transmitted Balanced Signal
Patent: 5,990,716 →
Application: 08/672,180 →
System for Cd-Rom Audio Playback Utilizing Blocking of Data Writing, Resuming Writing Responsive to Detecting Data in Response to Difference Between Desired Address and Present Address
Patent: 5,931,921 →
Application: 08/672,796 →
Inter-Bus Bridge Circuit with Integrated Memory Port
Patent: 5,881,254 →
Application: 08/674,592 →
Non-Volatile Memory Which Is Programmable from a Power Source
Patent: 5,648,930 →
Application: 08/674,593 →
Subsonic to Supersonic and Ultrasonic Conditioning of a Polishing Pad in a Chemical Mechanical Polishing Apparatus
Patent: 5,868,608 →
Application: 08/696,445 →
Method and Structure for Independent Disk and Host Transfers in a Storage Subsystem Target Device
Patent: 6,148,326 →
Application: 08/719,830 →
Method and Structure for Automated Switching Between Multiple Contexts in a Storage Subsystem Target Device
Patent: 6,247,040 →
Application: 08/720,393 →
Drain Excluded Eprom Cell
Patent: 5,661,687 →
Application: 08/720,601 →
Support for Direct Connect Disk Drives
Patent: 5,908,325 →
Application: 08/721,078 →
Method to Store Initiator Information for Scsi Data Transfer
Patent: 6,112,278 →
Application: 08/723,110 →
An Automated Coalesced Read with Optional Skipped Hit
Application: 08/723,294 →
System for Switching Multiple Context in Storage Subsystem Target Device Based on Determination That the Resources of the Target Device Are Underrutilized
Patent: 6,081,849 →
Application: 08/724,385 →
Method and Apparatus Having Automated Write Data Transfer with Optional Skip by Processing Two Commands as a Single Write Command
Patent: 6,029,226 →
Application: 08/724,522 →
Method and Apparatus for Improving Fairness in Scsi Bus Arbitration
Patent: 6,016,527 →
Application: 08/724,596 →
Shallow Trench Isolation in Integrated Circuits
Patent: 5,677,564 →
Application: 08/736,651 →
Hard Disk Rotational Latency Simulator
Patent: 6,135,648 →
Application: 08/747,485 →
Variable Step Height Control of Lithographic Patterning Through Transmitted Light Intensity Variation
Patent: 5,821,013 →
Application: 08/763,373 →
On/Off Control for a Balanced Differential Current Mode Driver
Patent: 5,880,599 →
Application: 08/764,547 →
Apparatus and Methods for Providing Robust Powering
Patent: 5,881,215 →
Application: 08/766,920 →
Electrode Assembly for Plasma Reactor
Patent: 5,976,309 →
Application: 08/767,698 →
Simple Bicmos Process for Creation of Low Trigger Voltage Scr and Zener Diode Pad Protection
Patent: 5,821,572 →
Application: 08/768,905 →
Compact Ventilation Unit for Electronic Apparatus
Patent: 5,772,500 →
Application: 08/770,890 →
Method of Secondary to Secondary Data Transfer with Mirroring
Patent: 6,654,853 →
Application: 08/772,443 →
Method and Apparatus for Providing Loop Coherency
Patent: 5,991,891 →
Application: 08/772,616 →
Method for Capturing Asic I/O Pin Data for Tester Compatibility Analysis
Patent: 5,995,740 →
Application: 08/773,469 →
Method for Tungsten Nucleation from WF6 Using Titanium as a Reducing Agent
Patent: 5,963,828 →
Application: 08/773,471 →
Method and Device for Isolating Noise Sensitive Circuitry from Switching Current Noise on Semiconductor Substrate
Patent: 6,097,218 →
Application: 08/777,686 →
System for Fast Posting to Shared Queues in Multi-Processor Environments Utilizing Interrupt State Checking
Patent: 5,966,547 →
Application: 08/781,871 →
Use of Mev Implantation to Form Vertically Modulated N+ Buried Layer in an Npn Bipolar Transistor
Patent: 5,858,828 →
Application: 08/801,668 →
Method and Apparatus for Setting a Plurality of Addresses
Patent: 5,918,241 →
Application: 08/804,326 →
Inter-Bus Bridge Circuit with Integratedshared Memory Interface and Loopback Test Capability and Method for Use of Same
Patent: 6,016,525 →
Application: 08/819,018 →
Fully Digital Clock Synthesizer
Patent: 5,920,211 →
Application: 08/825,082 →
System for Inverse Multiplexing Analog Channels
Patent: 6,198,749 →
Application: 08/826,496 →
Coordinate Based Data Input System
Application: 08/828,608 →
Method and Apparatus for Terminating a Bus
Patent: 6,070,206 →
Application: 08/829,409 →
Audio Transient Suppression Device
Patent: 6,040,740 →
Application: 08/833,816 →
Device and Method for Storing and Retrieving Original and Redundant Data
Patent: 6,061,194 →
Application: 08/843,419 →
Method and Apparatus for Using a Standby Network Interface for Control Messages in a Redundant Server Environment
Application: 08/845,304 →
Method and Apparatus for Maintaining Automatic Termination of a Bus in the Event of a Host Failure
Patent: 6,061,806 →
Application: 08/854,298 →
Compact Ventilation Unit with Exhaust Ports for Electronic Apparatus
Patent: 6,042,474 →
Application: 08/869,267 →
Recovery Circuit Having Long Hold Time and Phase Range
Patent: 5,939,912 →
Application: 08/878,160 →
Auto-Termination Method and Apparatus for Use with Either Active High or Active Low Terminators
Patent: 6,029,216 →
Application: 08/884,233 →
Method and Apparatus for Storage of Multiple Host Storage Management Information on a Storage Subsystem
Patent: 5,895,493 →
Application: 08/884,707 →
Method and Apparatus for Terminating a Bus at a Device Interface
Patent: 6,092,131 →
Application: 08/901,273 →
Method and Apparatus for Managing Power Consumption of a Digitizing Panel
Patent: 6,058,485 →
Application: 08/902,146 →
Method for Accelerating Disk Array Write Operations Using Segmented Cache Memory and Data Logging
Patent: 6,148,368 →
Application: 08/904,107 →
Software Recognition of Drive Removal or Insertion in a Storage System
Patent: 6,178,520 →
Application: 08/904,444 →
Offset Adjustment of Cmos Matched Pairs with Body Voltage
Application: 08/904,734 →
Method and Apparatus for Reducing Flat Panel Display Horizontal Scan Signal Interference in the Electrostatic Pen Operated Digitizer
Patent: 6,124,848 →
Application: 08/904,735 →
Automatic Power Supply Sensing with on-Chip Regulation
Patent: 6,262,567 →
Application: 08/904,736 →
Digitizer Stylus Storing Handwriting Data
Patent: 6,195,446 →
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Telementry by Digitizer Stylus
Patent: 5,883,338 →
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Standardized Gas Isolation Box (Gib) Installation
Patent: 5,915,414 →
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Method and Apparatus for Concurrent Execution of Operating Systems
Patent: 6,269,409 →
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Digital Clock Recovery Circuit with Phase Interpolation
Patent: 6,122,336 →
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Method and Apparatus for Touch Detection Based on the Current Flow Generated by an Object Relative to a Sensor Panel
Patent: 6,138,523 →
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Method for Virtual to Physical Mapping in a Mapped Compressed Virtual Storage Subsystem
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Testing a Peripheral Bus for Data Transfer Integrity by Detecting Corruption of Transferred Data
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Related Assignments (5)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignors Interest. Aug 11, 1980
From: TRUDEL MURRAY L.
To: NCR CORPORATION, A CORP. OF MD.
Reel/Frame 003794/0499 →
Change of Name Oct 12, 2004
From: HYUNDAI ELECTRONICS AMERICA
To: HYNIX SEMICONDUCTOR AMERICA INC.
Reel/Frame 015246/0599 →
Assignment of Assignor's Interest Oct 12, 2004
From: HYNIX SEMICONDUCTOR AMERICA, INC.
To: HYNIX SEMICONDUCTOR INC.
Reel/Frame 015279/0556 →
Assignment of Assignor's Interest Jan 10, 2005
From: HYNIX SEMICONDUCTOR, INC.
To: MAGNACHIP SEMICONDUCTOR, LTD.
Reel/Frame 016216/0649 →
Assignment of Assignor's Interest Feb 7, 2019
From: WOOD, TIMOTHY D.
To: SPRING MEADOW NURSERY, INC.
Reel/Frame 048285/0188 →