Patent Assignment
Reel/Frame 024120/0587
Assignment of Assignor's Interest
Recorded: 2010-02-18
Pages: 30
Assignor
SIEMENS AKTIENGESELLSCHAFT
Executed: 1999-03-31
Assignee
INFINEON TECHNOLOGIES AG
ST.-MARTIN-STR. 53, MUNICH, 81541, GERMANY
Covered Properties
(162)
Three-Dimensional One-Dimensional Cell Arrangement for Dynamic Semiconductor Memories and Method for the Manufacture of a Bit Line Contact
Patent:
5,025,295 →
Application:
07/464,685 →
Static Memory Having Pipeline Registers
Patent:
5,093,809 →
Application:
07/487,932 →
Integrated Semiconductor Memory of the Dram Type and Method for Testing the Same
Patent:
5,184,326 →
Application:
07/494,122 →
Photosensitive Mixture
Patent:
5,081,000 →
Application:
07/494,614 →
Preparing Highly Thermoresistant Relief Structures
Patent:
5,104,773 →
Application:
07/501,600 →
Planarizing Dielectric
Patent:
5,037,876 →
Application:
07/504,931 →
Etch-Resistant Deep Ultraviolet Resist Process Having an Aromatic Treating Step After Development
Patent:
5,173,393 →
Application:
07/513,570 →
A Method in a Parallel Test Apparatus for Semiconductor Memories
Patent:
5,224,107 →
Application:
07/528,552 →
Circuit Configuration for Identification of Integrated Semiconductor Circuitries
Patent:
5,027,322 →
Application:
07/546,008 →
Integrated Circuit with a Configuration Circuit
Patent:
5,124,587 →
Application:
07/547,605 →
Integratable Transistor Circuit for Outputting Logical Levels
Patent:
5,172,015 →
Application:
07/665,782 →
Method for Producing a Resist Structure
Patent:
5,229,258 →
Application:
07/682,142 →
Method for Producing a Resist Structure
Patent:
5,262,283 →
Application:
07/692,364 →
Planar Pn-Junction of High Electric Strength
Patent:
5,113,237 →
Application:
07/698,332 →
Method for Data Transfer for a Semiconductor Memory Using Combined Control Signals to Provide High Speed Transfer, and Semiconductor Memory for Carrying Out the Method
Patent:
5,357,469 →
Application:
07/769,172 →
Integrated Circuit with Anti Latch-Up Circuit in Complementary Mos Circuit Technology
Patent:
5,126,816 →
Application:
07/774,733 →
Protection Apparatus for Series Pass Mosfets
Patent:
5,333,093 →
Application:
07/788,642 →
Integrated Semiconductor Circuit
Patent:
5,276,643 →
Application:
07/799,907 →
Production of Photolithographic Structures
Patent:
5,384,220 →
Application:
07/811,706 →
Process for Producing N-Tertiary Butoxycarbonyl-Maleinimide
Patent:
5,194,629 →
Application:
07/812,582 →
Photostructuring Process
Patent:
5,250,375 →
Application:
07/812,585 →
Process for Producing an Arsenic-Doped Smooth Polycrystalline Silicon Layer for Very Large Scale Integrated Circuits
Patent:
5,310,698 →
Application:
07/812,712 →
Integrated Circuit for Generating a Reset Signal
Patent:
5,166,546 →
Application:
07/823,860 →
Regulating Circuit for a Substrate Bias Voltage Generator
Patent:
5,327,072 →
Application:
07/839,787 →
Refractory Metal Capped Low Resisitivity Metal Conductor Lines and Vias
Patent:
5,262,354 →
Application:
07/841,693 →
Level Inverter Circuit
Patent:
5,245,228 →
Application:
07/854,379 →
Cmos/Ecl Signal Level Converter
Patent:
5,331,229 →
Application:
07/869,472 →
Integrated Semiconductor Memory with Redundancy Arrangement
Patent:
5,459,690 →
Application:
07/920,315 →
On-Chip Intermediate Driver for Discrete Wsi Systems
Patent:
5,233,235 →
Application:
07/921,425 →
Circuit Configuration for Identification of Integrated Semiconductor Circuitries
Patent:
5,222,043 →
Application:
07/945,598 →
Method for the Production of a Bottom Resist
Patent:
5,368,901 →
Application:
07/945,766 →
Arrangement with Self-Amplifying Dynamic Mos Transistor Storage Cells
Patent:
5,327,374 →
Application:
07/956,896 →
Integrated Semiconductor Memory with Parallel Test Capability and Redundancy Method
Patent:
5,293,386 →
Application:
07/974,855 →
Circuit Arrangement for Testing a Semiconductor Memory by Means of Parallel Tests Using Various Test Bit Patterns
Patent:
5,436,912 →
Application:
07/983,866 →
Bit Line Arrangement for Integrated Circuits
Patent:
5,315,542 →
Application:
07/984,376 →
Dynamic Semiconductor Memory Having Local Read Amplifier Driver Circuits Which Are Optimized with Respect to Their Drive Function
Patent:
5,333,121 →
Application:
07/984,579 →
Dynamic Semiconductor Memory Having a Read Amplifier Drive Circuit for Achieving Short Access Times with a Low Total Peak Current
Patent:
5,293,343 →
Application:
07/988,956 →
Method of Manufacturing a Perforated Workpiece
Patent:
5,262,021 →
Application:
08/006,939 →
Positive 0-Quinone Diazide Photoresist Containing Base Copolymer Utilizing Monomer Having Anhydride Function and Further Monomer That Increases Etch Resistance
Patent:
5,360,693 →
Application:
08/059,518 →
Method for the Selective Deposition of Tungsten on a Silicon Surface
Patent:
5,387,438 →
Application:
08/073,622 →
Ferroelectric Memory Cell Arrangement
Patent:
5,471,417 →
Application:
08/087,814 →
Switching Stage
Patent:
5,397,932 →
Application:
08/088,153 →
Manufacturing Method for a Self-Aligned Through Hole and Semiconductor Structure
Patent:
5,432,381 →
Application:
08/122,302 →
Ternary/Binary Converter Circuit
Patent:
5,498,980 →
Application:
08/126,333 →
Integrated Circuit for Generating a Reset Signal
Patent:
5,442,312 →
Application:
08/129,959 →
Method of Depositing Conductors in High Aspect Ratio Apertures Under High Temperature Conditions
Patent:
5,529,670 →
Application:
08/172,017 →
Compact Semiconductor Storage Arrangement and Method for Its Production
Patent:
5,378,907 →
Application:
08/182,187 →
Semiconductor Memory Device with Trench Capacitor and Method for the Production Thereof
Patent:
5,701,022 →
Application:
08/192,188 →
Off-Chip Driver with Voltage Regulated Predrive
Patent:
5,440,258 →
Application:
08/193,317 →
Zag Fuse for Reduced Blow-Current Application
Patent:
5,420,456 →
Application:
08/193,927 →
Column Redundance Circuit Configuration for a Memory
Patent:
5,457,655 →
Application:
08/198,502 →
Amorphous, Hydrogentated Carbon as an Insulator in Device Fabrication
Patent:
5,427,985 →
Application:
08/209,027 →
Method for Manufacturing Tunnel-Effect Sensors
Patent:
5,472,916 →
Application:
08/217,854 →
Method for Manufacturing Rod-Shaped Silicon Structures
Patent:
5,449,310 →
Application:
08/222,597 →
Shallow Trench Isolation with Thin Nitride Liner
Patent:
5,447,884 →
Application:
08/268,378 →
P-Mosfets with Enhanced Anomalous Narrow Channel Effect
Patent:
5,559,050 →
Application:
08/269,857 →
Method for Producing a Semiconductor Layer Structure Having a Planarized Surface and the Use Thereof in the Manufacture of Bipolar Transistors and Drams
Patent:
5,643,836 →
Application:
08/279,106 →
Voltage Generator Circuit
Patent:
5,592,063 →
Application:
08/279,918 →
Charge Pump
Patent:
5,546,296 →
Application:
08/279,919 →
Process for Making a Contact Between a Capacitor Electrode Disposed in a Trench and an Mos Transistor Source/Drain Region Disposed Outside the Trench
Patent:
5,432,115 →
Application:
08/284,502 →
Method for Manufacturing a Bit Line via Hole in a Memory Cell
Patent:
5,500,384 →
Application:
08/294,333 →
Method for the Production of a Bottom Resist
Patent:
5,512,334 →
Application:
08/301,285 →
Method of Making Contact for Semiconductor Device
Patent:
5,464,793 →
Application:
08/317,151 →
Negative Resists with High Thermal Stability Comprising End Capped Polybenzoxazole and Bisazide
Patent:
5,486,447 →
Application:
08/330,227 →
Personalized Area Leadframe Coining or Half Etching for Reduced Mechanical Stress at Device Edge
Patent:
5,545,921 →
Application:
08/334,478 →
Unit Cell Layout and Transfer Gate Design for High Density Drams Having a Trench Capacitor with Signal Electrode Composed of Three Diffently Doped Polysilicon Layers
Patent:
5,936,271 →
Application:
08/340,500 →
Process for Producing Storage Capacitors for Dram Cells
Patent:
5,496,757 →
Application:
08/351,464 →
Embedded Phase Shifting Photomasks and Method for Manufacturing Same
Patent:
5,679,483 →
Application:
08/359,790 →
Global Planarization Using Self Aligned Polishing or Spacer Technique and Isotropic Etch Process
Patent:
5,663,107 →
Application:
08/362,399 →
Process for Fabricating a Dram Trench Capacitor
Patent:
5,677,219 →
Application:
08/365,649 →
Microelectronic Component
Patent:
5,540,977 →
Application:
08/365,932 →
Integrated Semiconductor Memory Device Capable of Switching from a Memory Mode to an Internal Test Mode
Patent:
5,497,350 →
Application:
08/366,361 →
Integrated Semiconductor Memory Circuit and Method for Its Operation
Patent:
5,553,027 →
Application:
08/371,829 →
Circuit Array for Amplifying and Holding Data with Different Supply Voltages
Patent:
5,546,036 →
Application:
08/376,683 →
Method for Manufacturing a Cubically Integrated Circuit Arrangement
Patent:
5,529,950 →
Application:
08/377,049 →
Dram-Type Memory Cell Arrangement on a Substrate
Patent:
5,600,162 →
Application:
08/382,048 →
Photoresists Which Are Suitable for Producing Sub-Micron Size Structures
Patent:
6,110,637 →
Application:
08/386,136 →
Ablation Patterning of Multi-Layered Structures
Patent:
5,843,363 →
Application:
08/414,241 →
Method for Checking Semiconductor Wafers and Apparatuses for Carrying Out the Method
Patent:
5,742,395 →
Application:
08/425,827 →
Isotropic Silicon Etch Process That Is Highly Selective to Tungsten
Patent:
5,670,018 →
Application:
08/430,011 →
Two-Step Chemical Mechanical Polish Surface Planarization Technique
Patent:
6,069,081 →
Application:
08/430,972 →
Copolymers
Patent:
5,616,667 →
Application:
08/434,955 →
Multilayer Printed Circuit Boards and Multichip-Module Substrates with Layers of Amorphous Hydrogenated Carbon
Patent:
5,601,902 →
Application:
08/443,298 →
Personalized Area Leadframe Coining or Half Etching for Reduced Mechanical Stress at Device Edge
Patent:
5,576,246 →
Application:
08/458,848 →
Connection and Build-Up Technique for Multichip Modules
Patent:
5,556,812 →
Application:
08/495,246 →
Module Board Including Conductor Tracks Having Disconnectable Connecting Elements
Patent:
5,572,457 →
Application:
08/498,165 →
Method for Hierarchic Logic Verification of Vlsi Circuits
Patent:
5,671,399 →
Application:
08/498,687 →
Redundant Circuit Configuration for an Integrated Semiconductor Memory
Patent:
5,657,279 →
Application:
08/514,602 →
Process for Depositing a Surface-Wide Layer Through a Mask and Optionally Closing Said Mask
Patent:
5,786,235 →
Application:
08/537,915 →
Integrated Semiconductor Memory
Patent:
36,061 →
Application:
08/542,360 →
Contact Structure for Vertical Chip Connections
Patent:
5,846,879 →
Application:
08/545,647 →
Process for Producing Semiconductor Components Between Which Contact Is Made Vertically
Patent:
5,767,001 →
Application:
08/545,650 →
Transistor Isolation Process
Patent:
5,854,112 →
Application:
08/563,882 →
Radiation-Sensitive Resist Composition Comprising a Diazoketone
Patent:
5,648,195 →
Application:
08/571,879 →
Flexible Ecc/Parity Bit Architecture
Patent:
5,966,389 →
Application:
08/603,409 →
Test Circuit and Testing Method for Function Testing of Electronic Circuits
Patent:
6,107,815 →
Application:
08/605,901 →
Semiconductor Memory with Cells Combined into Individually Addressable Units, and Method for Operating Such Memories
Patent:
5,671,184 →
Application:
08/610,047 →
An Integrated Circuit Board with Built-in Terminal Connection Testing Circuitry
Patent:
5,815,001 →
Application:
08/617,125 →
Methods for Producing Polybenzoxazol Precursors and Corresponding Resist Solutions
Patent:
5,688,631 →
Application:
08/618,488 →
Low Power Sense Amplifier for Gain Memory Cells
Patent:
5,610,540 →
Application:
08/625,840 →
Serially Accessible Memory Means with High Error Correctability
Patent:
5,751,742 →
Application:
08/626,512 →
Process of Making a Dram Cell Arrangement
Patent:
5,817,552 →
Application:
08/635,526 →
A Ferroelectric Memory Device and Method for Producing the Device
Patent:
5,869,860 →
Application:
08/637,163 →
Semiconductor Memory Device and Method for Its Production
Patent:
5,828,092 →
Application:
08/639,123 →
Dram Cell Arrangement and Method for Its Manufacture
Patent:
5,736,761 →
Application:
08/645,503 →
Apparatus and Method for Cleaning Photomasks
Patent:
5,634,230 →
Application:
08/647,154 →
Memory Apparatus with Dynamic Memory Cells Having Different Capacitor Values
Patent:
5,706,225 →
Application:
08/652,915 →
Method for the Production of Poly-0-Hydroxyamides
Patent:
5,750,638 →
Application:
08/666,177 →
Method for the Production of Poly-O-Hydroxyamides
Patent:
5,777,066 →
Application:
08/666,182 →
Fuse Bank
Patent:
5,661,331 →
Application:
08/671,796 →
Method for the Production of a Three-Dimensional Circuit Arrangement
Patent:
5,741,733 →
Application:
08/676,164 →
Bootstrap Circuit and Integrated Memory Circuit Having the Bootstrap Circuit
Patent:
5,783,962 →
Application:
08/679,372 →
Unit Cell Layout and Transfer Gate Design for High Density Drams
Patent:
6,004,844 →
Application:
08/680,765 →
Memory Cell Arrangement of Memory Cells Arranged in the Form of a Matrix
Patent:
5,825,701 →
Application:
08/682,022 →
Capacitor in a Semiconductor Configuration and Process for Its Production
Patent:
5,989,972 →
Application:
08/685,847 →
Memory Device and Production Method
Patent:
5,774,414 →
Application:
08/694,531 →
Integrated Semiconductor Memory Device
Patent:
5,675,543 →
Application:
08/694,533 →
Integrated Semiconductor Memory
Patent:
5,666,316 →
Application:
08/694,534 →
Novel Dicarboxylic Acid Derivatives
Patent:
5,750,711 →
Application:
08/704,213 →
Preparation of Poly-O-Hydroxyamides and Poly O-Mercaptoamides
Patent:
5,807,969 →
Application:
08/705,099 →
Preparation of Poly-O-Hydroxyamides and Poly O-Mercaptoamides
Patent:
5,922,825 →
Application:
08/705,446 →
Preparation of Poly-O-Hydroxyamides and Poly-O-Mercaptoamides
Patent:
5,696,218 →
Application:
08/705,469 →
Preparation of Poly-O-Hydroxymides and Poly O-Mercaptoamides
Patent:
5,783,654 →
Application:
08/705,575 →
Preparation of Poly-O-Hydroxyamides and Poly O-Mercaptoamides
Patent:
5,726,279 →
Application:
08/705,576 →
A Semiconductor Configuration for an Insulating Transistor
Patent:
5,962,901 →
Application:
08/715,932 →
Low Loss Integrated Circuit with Reduced Clock Swing
Patent:
5,854,567 →
Application:
08/716,440 →
Mixed Polymers
Patent:
5,703,186 →
Application:
08/717,652 →
Dram Cell Array with Dynamic Gain Memory Cells
Patent:
5,854,500 →
Application:
08/721,546 →
Integrated Circuit Interconnection Employing Tungsten/Aluminum Layers
Patent:
5,840,625 →
Application:
08/726,443 →
Microelectronic Component and Process for Its Production
Patent:
5,828,076 →
Application:
08/727,440 →
A Semiconductor Memory Device Having a Transistor, a Bit Line, a Word- Line and a Stacked Capacitor
Patent:
5,714,779 →
Application:
08/730,644 →
Method of Producing and Arrangement Containing Self-Amplifying Dynamic Mos Transistor Memory Cells
Patent:
5,710,072 →
Application:
08/737,236 →
Dry-Developable Positive Resist
Patent:
5,733,706 →
Application:
08/737,989 →
Memory Cell Configuration and Method for Its Production
Patent:
6,300,652 →
Application:
08/755,456 →
Process for Manufacturing Capacitors in a Solid State Configuration
Patent:
5,817,553 →
Application:
08/766,977 →
Method for Producing a Contact Hole to a Doped Region
Patent:
5,731,218 →
Application:
08/769,311 →
Apparatus and Method for Detecting and Assessing a Spatially Discrete Dot Pattern
Patent:
5,950,181 →
Application:
08/779,365 →
Method of Amufacturing a Fuse Structure
Patent:
5,827,759 →
Application:
08/781,571 →
Photolithographic Pattern Generation
Patent:
5,851,733 →
Application:
08/793,310 →
Photolithographic Pattern Generation
Patent:
5,863,705 →
Application:
08/793,546 →
Fuse Structure for an Integrated Circuit Element
Patent:
5,789,794 →
Application:
08/811,327 →
Portable Data Carrier Configuration to Be Operated on a Data Bus and Data Processing System Having at Least One Portable Data Carrier Configuration
Patent:
5,884,319 →
Application:
08/828,538 →
Data Carrier Card, Assembly of at Least Two Data Carrier Cards and Method of Accessing at Least One of the Data Carrier Cards
Patent:
5,925,928 →
Application:
08/828,697 →
Ablation Pattering of Multilayered Structures
Patent:
5,766,497 →
Application:
08/829,370 →
Scanning Electron Microscopic Ruler and Method
Patent:
5,822,875 →
Application:
08/867,772 →
Multi-Value Read-Only Memory Cell Having an Improved Signal-to-Noise Ratio
Patent:
5,825,686 →
Application:
08/875,955 →
Photolithographic Structure Generation Process
Patent:
6,042,993 →
Application:
08/875,957 →
Methods for Reducing Anomalous Narrow Channel Effect in Trench-Bounded Buried-Channel P-Mosfets
Patent:
5,858,825 →
Application:
08/893,053 →
Semiconductor Memory Device with Trench Capacitor and Method for the Production Thereof
Patent:
5,843,819 →
Application:
08/898,514 →
Gtl Output Amplifier for Coupling an Input Signal at the Input to a Transmission Line at the Output
Patent:
6,075,383 →
Application:
08/930,535 →
Device in a Semicondutor Manufacturing Installation in Particular for Integrated Circuits
Patent:
6,075,358 →
Application:
09/005,067 →
Integrated Circuit Interconnection Employing Tungsten / Aluminum Layers
Patent:
6,016,008 →
Application:
09/024,998 →
Device for the Jump-Like Addressing of Specific Lines of a Serially Operating Digital Memory
Patent:
6,138,227 →
Application:
09/043,046 →
Method for Producing a Memory Device
Patent:
6,100,109 →
Application:
09/081,910 →
Method for Operating a Sram Mos Transistor Memory Cell
Patent:
5,973,965 →
Application:
09/091,713 →
Read-Only Memory Cell Device and Method for Its Production
Patent:
6,211,019 →
Application:
09/130,051 →
Method for Producing Semiconductor Memory Device Having a Capacitor
Patent:
6,083,765 →
Application:
09/135,623 →
Method for Producing a Capacitor
Patent:
6,232,169 →
Application:
09/200,095 →
Method for Reading and Refreshing a Dynamic Semiconductor Memory
Patent:
5,978,296 →
Application:
09/205,624 →
Device in a semiconductor manufacturing installation in particular for integrated circuits
Application:
09/824,315 →
Method for Producing a Semiconductor Memory Device with a Multiplicity of Memory Cells
Method for checking a semiconductor memory device
Related Assignments
(1)
Other recorded transfers of the patents in this record — the chain of ownership.