IP Library › Assignment 014102/0224
Patent Assignment
Reel/Frame 014102/0224

Change of Name

Recorded: 2003-11-03 Pages: 23
Assignor
Assignee
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
20555 SH 249, HOUSTON, TEXAS, 77070
Covered Properties (939)
Data Processing System Having a Data Structure with a Single, Simple Primitive
Patent: 5,664,177 →
Application: 07/181,105 →
Programmable Data Transfer Timing
Patent: 5,335,337 →
Application: 07/303,624 →
Information Object Transport System
Patent: 5,422,999 →
Application: 07/368,681 →
Re-Execution of Edit-Compile-Link -Run Cycles for Changed Lines of Source Code with Storage of Associated Data in Buffers
Patent: 5,313,387 →
Application: 07/375,384 →
Extensible Entity Management System Including a Dispatching Kernel and Modules Which Independently Interpret and Execute Commands
Patent: 5,345,587 →
Application: 07/402,391 →
Information Transfer Arrangement for Distributed Computer System
Patent: 5,701,427 →
Application: 07/408,751 →
Instruction Storage Method with a Compressed Format Using a Mask Word
Patent: 5,057,837 →
Application: 07/476,108 →
Method for Executing Trusted-Path Commands
Patent: 6,507,909 →
Application: 07/479,666 →
Reticular Discrimination Network for Specifying Real-Time Conditions
Patent: 5,390,286 →
Application: 07/499,039 →
Process and System for Making Computer-Aided Drawings Using a Contour Inclusion Tree Associated Planar Map Data Structure
Patent: 5,337,404 →
Application: 07/513,247 →
Lattice Scheduler Method for Reducing the Impact of Covert-Channel Countermeasures
Patent: 5,574,912 →
Application: 07/519,238 →
Data Processor Performance Advisor
Patent: 5,062,055 →
Application: 07/528,321 →
Method and Apparatus for Implementing More Stream Transactions
Patent: 5,416,907 →
Application: 07/538,656 →
Digital Processor with Bit Mask for Counting Registers for Fast Register Saves
Patent: 5,321,823 →
Application: 07/542,636 →
An Apparatus and Method for an Improved Content Addressable Memory
Patent: 5,317,708 →
Application: 07/546,414 →
Frequency Independent Encoding Technique and Apparatus for Digital Communications
Patent: 5,303,265 →
Application: 07/546,422 →
Prefetch Instruction for Improving Performance in Reduced Instruction Set Processor
Patent: 5,778,423 →
Application: 07/547,630 →
Method and Apparatus for Performing Diagnosis Scanning of a Memory Unit Regardless of the State of the System Clock and Without Affecting the Store Data
Patent: 5,313,623 →
Application: 07/547,656 →
Method of Displaying Descriptive Data Representing a Candidate as a Plurality of Lines on an Output Device
Patent: 5,606,653 →
Application: 07/559,278 →
Language for Economically Building Complex, Large-Scale Efficient, Rule -Based Systems and Sub-Systems
Patent: 5,303,332 →
Application: 07/559,342 →
Normalization of Vectors Associated with Display Pixels of Computer Generated Images
Patent: 5,369,737 →
Application: 07/568,529 →
Single-Keyed Indexed File for Tp Queue Repository
Patent: 5,327,557 →
Application: 07/573,393 →
Compound Principals in Access Control Lists
Patent: 5,315,657 →
Application: 07/589,923 →
System for Distributed Computation Processing Including Dynamic Assignment of Predicates to Define Interdependencies
Patent: 5,329,626 →
Application: 07/601,990 →
Methods and Apparatus for Accessing Non-Relational Data Files Using Relational Queries
Patent: 5,379,419 →
Application: 07/623,762 →
Text Searching System
Patent: 5,369,577 →
Application: 07/650,812 →
System and Method for Jacketing Cross-Domain Calls in a Multi-Code Execution and Debugging System Within a Multi-Architecture Environment
Patent: 5,339,422 →
Application: 07/665,752 →
System for Linking Program Units by Binding Symbol Vector Index in the Symbol Table into Calling Image to Obtain Current Value of the Target Image
Patent: 5,297,291 →
Application: 07/666,023 →
System and Method for Preserving Instruction Granularity When Translating Program Code from a Computer Having a First Architecture to a Computer Having a Second Reduced Architecture During the Occurrence of Interrupts Due to Asynchronous Events
Patent: 5,307,504 →
Application: 07/666,025 →
Branch Resolution via Backward Symbolic Execution
Patent: 5,428,786 →
Application: 07/666,070 →
Tracking Condition Codes in Translating Code for Different Machine Architectures
Patent: 5,598,560 →
Application: 07/666,082 →
Use of Stack Depth to Identify Architecture and Calling Standard Dependencies in Machine Code
Patent: 5,301,325 →
Application: 07/666,083 →
Register Usage Tracking in Translating Code for Different Machine Architectures by Forward and Reverse Tracing Through the Program Flow Graph
Patent: 5,339,238 →
Application: 07/666,084 →
Mapping Assembly Language Argument List References in Translating Code for Different Machine Architectures
Patent: 5,307,492 →
Application: 07/666,085 →
Successive Translation, Execution and Interpretation of Computer Program Having Code at Unknown Locations Due to Execution Transfer Instructions Having Computed Destination Addresses
Patent: 5,507,030 →
Application: 07/666,196 →
Use of Stack Depth to Identify Machine Code Mistakes
Patent: 5,450,575 →
Application: 07/666,210 →
Analysis of Computer Programs for Locating Translatable Code by Resolving Callbacks and Other Conflicting Mutual Dependencies
Patent: 5,317,740 →
Application: 07/666,223 →
A Coupled Memory Multiprocessor Computer System Including Cache Coherency Management Protocols
Patent: 5,303,362 →
Application: 07/673,766 →
Computer Apparatus and Method for Finite Element Identification in Interactive Modeling
Patent: 5,289,567 →
Application: 07/678,691 →
Computer Peripheral Device Network with Peripheral Address Resetting Capabilities
Patent: 5,317,693 →
Application: 07/680,313 →
Expert System for Identifying Likely Failure Points in a Digital Data Processing System
Patent: 5,469,463 →
Application: 07/700,112 →
System for Reporting Errors of a Translated Program and Using a Boundry Instruction Bitmap to Determine the Corresponding Instruction Address in a Source Program
Patent: 5,432,795 →
Application: 07/700,770 →
Rule Structure for Insertion of New Elements in a Circuit Design Synthesis Procedure
Patent: 5,452,226 →
Application: 07/703,706 →
Photo-Definable Template for Semiconductor Chip Alignment
Patent: 5,413,964 →
Application: 07/720,262 →
System of Device Independent File Directories Using a Tag Between the Directories and File Descriptors That Migrate with the Files
Patent: 5,333,315 →
Application: 07/722,008 →
Workflow Management and Control System
Patent: 5,301,320 →
Application: 07/722,691 →
System for Reconstructing Prior Versions of Indexes Using Records Indicating Changes Between Successive Versions of the Indexes
Patent: 5,347,653 →
Application: 07/722,696 →
System for Constructing and Loading a Table Data Structure Based on an Associated Configuration Data Structure
Patent: 5,446,575 →
Application: 07/722,750 →
System for Constructing a Table Data Sturcture Based on an Associated Configuration Data Structure and Loading It with Checmial Sample Physical Data
Patent: 5,434,971 →
Application: 07/722,751 →
Translation Buffer for Virtual Machines with Address Space Match
Patent: 5,319,760 →
Application: 07/722,869 →
Method and Apparatus for Efficient Morphological Text Analysis Using a High-Level Language for Compact Specification of Inflectional Paradigms
Patent: 5,559,693 →
Application: 07/723,145 →
Frame Assembly for Rack-Mountable Equipment
Patent: 5,372,262 →
Application: 07/723,396 →
System and Method for Construction of Language Independent Print Format Statements Through Use of Data Structures for Arbitrary Ordering of Print Parameters
Patent: 5,339,240 →
Application: 07/724,573 →
Multilevel Transaction Recovery in a Database System Which Loss Parent Transaction Undo Operation Upon Commit of Child Transaction
Patent: 5,287,501 →
Application: 07/728,661 →
Method and Apparatus for Efficient Morphological Text Analysis Using a High-Level Language for Compact Specification of Inflectional Paradigms
Patent: 5,475,587 →
Application: 07/729,445 →
System for Translation of Virtual to Physical Addresses by Opearting Memory Management Processor for Calculating Location of Physical Address in Memory Concurrently with Cache Comparing Virtual Addresses for Translation
Patent: 5,349,651 →
Application: 07/746,007 →
Graphics Command Processing Method in a Computer Graphics System
Patent: 5,315,696 →
Application: 07/748,352 →
Address Method for Computer Graphics System
Patent: 5,321,810 →
Application: 07/748,353 →
Method and Apparatus for Varying Command Length in a Computer Graphics System
Patent: 5,315,698 →
Application: 07/748,354 →
Translation of Virtual Addresses in a Computer Graphics System
Patent: 5,313,577 →
Application: 07/748,357 →
Method and Apparatus for Transmitting Graphics Command in a Computer Graphics System
Patent: 5,321,806 →
Application: 07/748,360 →
Predictive Cache System
Patent: 5,305,389 →
Application: 07/753,096 →
Compiler Allocating a Register to a Data Item Used Between a Use and Store of Another Data Item Previously Allocated to the Register
Patent: 5,339,428 →
Application: 07/754,549 →
Update Synchronizer
Patent: 5,294,842 →
Application: 07/763,795 →
Correcting Crossover Distortion Produced When Analog Signal Thresholds Are Used to Remove Noise from Signal
Patent: 5,287,534 →
Application: 07/775,681 →
System and Method for Analyzing Complex Sequences in Trace Arrays Using Multiple Finite Automata
Patent: 5,299,206 →
Application: 07/781,889 →
Attribute Inductive Data Analysis
Patent: 5,956,692 →
Application: 07/794,298 →
Fast Tag Compare and Bank Select in Set Associative Cache
Patent: 5,353,424 →
Application: 07/794,865 →
Computer Method and Apparatus for Converting Compressed Characters for Display in Full Size
Patent: 5,404,436 →
Application: 07/800,666 →
Method for Analyzing the Flow of Data Through a Complex Information Exchange System
Patent: 5,487,131 →
Application: 07/804,481 →
Generic Remote Boot for Networked Workstations by Creating Local Bootable Code Image
Patent: 5,452,454 →
Application: 07/805,572 →
Attribute Based Multiple Data Structures in Host for Network Received Traffic
Patent: 5,303,347 →
Application: 07/815,007 →
Multiprocessor Buffer System
Patent: 5,315,707 →
Application: 07/818,608 →
Compiler Using Clean Lines Table with Entries Indicating Unchanged Text Lines for Incrementally Compiling Only Changed Source Text Lines
Patent: 5,325,531 →
Application: 07/819,611 →
Image Rendering Clip Registers
Patent: 5,414,524 →
Application: 07/820,533 →
System and Method for Exclusive Two-Level Caching
Patent: 5,386,547 →
Application: 07/823,671 →
Memory Selection /Deselection Circuitry Having a Wordline Discharge Circuit
Patent: 5,301,163 →
Application: 07/830,768 →
Molded Video Display Screen Bezel
Patent: 5,565,934 →
Application: 07/831,720 →
Method of Forming Trench Isolated Regions with Sidewall Doping
Patent: 5,296,392 →
Application: 07/841,239 →
Apparatus and Method for Synchronization of Access to Main Memory Signal Groups in a Multiprocessor Data Processing System
Patent: 5,291,581 →
Application: 07/844,968 →
Window Dependent Pixel Datatypes in a Computer Video Graphics System
Patent: 5,396,263 →
Application: 07/849,784 →
System for Achieving Atomic Non-Sequential Multi-Word Operations in Shared Memory
Patent: 5,428,761 →
Application: 07/849,887 →
Clocking System for Asynchronous Operations
Patent: 5,319,678 →
Application: 07/854,519 →
Method and Apparatus for Text Classification
Patent: 5,371,807 →
Application: 07/855,378 →
Data Bus Using Open Drain Drivers and Differential Receivers Together with Distributed Termination Impedances
Patent: 5,311,081 →
Application: 07/861,747 →
Intelligent and Compact Bucketing Method for Region Queries in Two-Dimensional Space
Patent: 5,319,743 →
Application: 07/862,467 →
Integrated Computer Assembly
Patent: 5,294,994 →
Application: 07/863,612 →
Locating Mobile Objects in a Distributed Computer System
Patent: 5,325,524 →
Application: 07/864,371 →
Sequential Multilayer Process for Using Fluorinated Hydrocarbons as a Dielectric
Patent: 5,387,495 →
Application: 07/864,375 →
Queue Apparatus and Mechanics for a Communications Interface Architecture
Patent: 5,386,514 →
Application: 07/869,648 →
System for Accessing Information in a Data Processing System
Patent: 5,386,524 →
Application: 07/869,668 →
Dynamic Arbitration for System Bus Control in Multiprocessor Data Processing System
Patent: 5,301,283 →
Application: 07/870,134 →
Memory Bank Management and Arbitration in Multiprocessor Computer System
Patent: 5,412,788 →
Application: 07/870,448 →
Dual Addressing Arrangement for a Communications Interface Architecture
Patent: 5,657,471 →
Application: 07/870,491 →
Error Detecting and Correcting Apparatus and Method with Transparent Test Mode
Patent: 5,357,529 →
Application: 07/872,977 →
Identification Panel for Electronic Equipment Cabinet
Patent: 5,363,578 →
Application: 07/873,319 →
Interconnect Arrangement for Electronic Components Disposed on a Circuit Board
Patent: 5,297,107 →
Application: 07/873,922 →
System for Radial Clock Distribution and Skew Regulation for Synchronous Clocking of Components of a Computing System
Patent: 5,428,764 →
Application: 07/873,923 →
Processor Identification Mechanism for a Multiprocessor System
Patent: 5,388,224 →
Application: 07/873,924 →
Method of Using Stream Buffer to Perform Operation Under Normal Operation Mode and Selectively Switching to Test Mode to Check Data Integrity During System Operation
Patent: 5,452,418 →
Application: 07/874,071 →
System for Sequential Read of Memory Stream Buffer Detecting Page Mode Cycles Availability, Fetching Data into a Selected Fifo, and Sending Data Without Accessing Memory
Patent: 5,461,718 →
Application: 07/874,076 →
Stream Buffer Memory Having a Multiple-Entry Address History Buffer for Detecting Sequential Reads to Intiate Prefetching
Patent: 5,371,870 →
Application: 07/874,080 →
Aborting Synchronizer
Patent: 5,305,354 →
Application: 07/874,237 →
Self-Configuring Bus Termination Component
Patent: 5,309,569 →
Application: 07/874,288 →
Duplicate Tag Store for a Processor Having Primary and Backup Cache Memories in a Multiprocessor Computer System
Patent: 5,319,766 →
Application: 07/874,289 →
Scheme for Error Handling in a Computer System
Patent: 5,361,267 →
Application: 07/874,321 →
Self-Compensating Voltage Level Shifting Circuit
Patent: 5,287,517 →
Application: 07/874,322 →
Application Design Interface Enhancement
Patent: 5,557,729 →
Application: 07/874,750 →
Method and Apparatus for Protecting the Confidentiality of Passwords in a Distributed Data Processing System
Patent: 5,418,854 →
Application: 07/875,050 →
Method of Mounting a Tape Automated Bonded Semiconductor in a Housing Using a Compressor
Patent: 5,298,464 →
Application: 07/890,984 →
Quadrant-Based Binding of Pointer Device Buttons
Patent: 5,319,385 →
Application: 07/892,189 →
Video Teleconferencing for Networked Workstations
Patent: 5,375,068 →
Application: 07/893,074 →
Method of Making an Electrical Interconnect Device
Patent: 5,428,891 →
Application: 07/893,220 →
Power Converter with Controller for Switching Between Primary and Battery Power Sources
Patent: 5,289,046 →
Application: 07/896,250 →
Modular Housing for Batteries and Battery Charger
Patent: 5,366,827 →
Application: 07/896,251 →
Static Timing Verification
Patent: 5,355,321 →
Application: 07/898,920 →
Semiconductor Chip Test Jig
Patent: 5,347,215 →
Application: 07/900,631 →
Hybrid Lock Escalation and De-Escalation Protocols
Patent: 5,414,839 →
Application: 07/901,590 →
Method and Apparatus for Ordering Read and Write Operations Using Conflict Bits in a Write Queve
Patent: 5,432,918 →
Application: 07/901,646 →
Processor and Method for Preventing Access to a Locked Memory Block by Recording a Lock in a Content Addressable Memory with Outstanding Cache Fills
Patent: 5,404,482 →
Application: 07/902,122 →
Digital Computer System with Cache Controller Coordinating Both Vector and Scalar Operations
Patent: 5,418,973 →
Application: 07/902,149 →
Processing and Method for Delaying the Processing of Cache Coherency Transactions During Outstanding Cache Fills
Patent: 5,404,483 →
Application: 07/902,156 →
Method and Apparatus for Testing Processor-Based Computer Modules
Patent: 5,359,547 →
Application: 07/904,784 →
Smart Recompilation of Performing Matchup/Difference After Code Generation
Patent: 5,367,683 →
Application: 07/904,816 →
Method and System for Decreasing Recovery Time for Failed Atomic Transactions by Keeping Copies of Altered Control Structures in Main Memory
Patent: 5,414,840 →
Application: 07/905,555 →
Durable Atomic Storage Update Manager
Patent: 5,469,562 →
Application: 07/905,901 →
Hint Generation in Smart Recompilation
Patent: 5,446,899 →
Application: 07/906,212 →
Method and Apparatus for Coordinating Access to and Modifying Multiple Element Data Objects in a Shared Memory
Patent: 5,553,267 →
Application: 07/907,330 →
High-Speed, Low-Noise, Cmos Output Driver
Patent: 5,313,118 →
Application: 07/909,549 →
Distributed Transaction Processing Using Two-Phase Commit Protocol with Presumed-Commit Without Log Force
Patent: 5,335,343 →
Application: 07/909,556 →
Fifo Based Parity Generator
Patent: 5,335,235 →
Application: 07/909,875 →
Color Information Storage and Processing System
Patent: 5,465,104 →
Application: 07/912,570 →
Ensuring Write Ordering Under Writeback Cache Error Conditions
Patent: 5,347,648 →
Application: 07/914,777 →
Video Data Scaling for Video Teleconferencing Workstations Communicating by Digital Data Network
Patent: 5,475,421 →
Application: 07/915,087 →
Audio/Video Storage and Retrieval for Multimedia Workstations by Interleaving Audio and Video Data in Data File
Patent: 5,623,690 →
Application: 07/915,088 →
Asynchronous Bus Interface for Generating Individual Handshake Signal for Each Data Transfer Based on Associated Propagation Delay Within a Transaction
Patent: 5,469,547 →
Application: 07/916,327 →
Multi-Element Susceptibility Room
Patent: 5,302,960 →
Application: 07/916,459 →
Sort and Merge System Using Tags Associated with the Current Records Being Sorted to Lookahead and Determine the Next Record to Be Sorted
Patent: 5,349,684 →
Application: 07/918,871 →
Long-Term Storage of Controller Performance
Patent: 5,410,545 →
Application: 07/920,766 →
Procedure State Descriptor System for Digital Data Processors
Patent: 5,388,263 →
Application: 07/923,022 →
Method Apparatus for Scheduling Tasks in Repeated Iterations in a Digital Data Processing System Having Multiple Processors
Patent: 5,293,620 →
Application: 07/927,785 →
Optimized Stripe Detection for Redundant Arrays of Disk Drives
Patent: 5,315,602 →
Application: 07/929,076 →
Data and Parity Prefetching for Redundant Arrays of Disk Drives
Patent: 5,309,451 →
Application: 07/929,080 →
Method for Merging Memory Blocks, Fetching Associated Disk Chunk, Merging Memory Blocks with the Disk Chunk, and Writing the Merged Data
Patent: 5,420,983 →
Application: 07/929,085 →
Method and Apparatus for Realignment of Synchronous Data
Patent: 5,359,630 →
Application: 07/929,623 →
Apparatus and Method for Main Memory Unit Protection Using Access and Fault Logic Signals
Patent: 5,317,717 →
Application: 07/932,913 →
Register Conflict Scoreboard in Pipelined Computer Using Pipelined Reference Counts
Patent: 5,488,730 →
Application: 07/934,351 →
Microprocessor System for Selectively Accessing a Processor Internal Register When the Processor Has Control of the Bus and Partial Address Identifying the Register
Patent: 5,408,612 →
Application: 07/942,246 →
System for Predicting Memory Fault in Vector Processor by Sending Indication Signal to Scalar Processor to Continue a Next Vector Instruction Issuance
Patent: 5,319,791 →
Application: 07/943,165 →
High Bandwidth Multiple Computer Bus Apparatus
Patent: 5,307,506 →
Application: 07/945,571 →
Thread Private Memory Storage of Multi-Thread Digital Data Processors Using Access Descriptors for Uniquely Identifying Copies of Data Created on an as-Needed Basis
Patent: 5,345,588 →
Application: 07/947,881 →
Methods for Treating Photoresists
Patent: 5,366,852 →
Application: 07/948,022 →
Multi-Index Multi-Way Set-Associative Cache
Patent: 5,509,135 →
Application: 07/951,623 →
Character Output Control Method and Apparatus for Terminal
Patent: 5,742,746 →
Application: 07/952,863 →
System for Bonding a Heatsink to a Semicondutor Chip Package
Patent: 5,308,429 →
Application: 07/953,448 →
System for Specifying Interactions Among Objects in a Digital Data Processing System
Patent: 5,613,116 →
Application: 07/954,407 →
Coplanar Heatsink and Electronics Assembly
Patent: 5,305,185 →
Application: 07/954,548 →
Apparatus for an Air Impingement Heat Sink Using Secondary Flow Generators
Patent: 5,304,845 →
Application: 07/954,608 →
Synchronous/Asynchronous Partitioning of an Asynchronous Bus Interface
Patent: 5,592,685 →
Application: 07/957,977 →
Imaging System with Multilevel Dithering Using Two Memories
Patent: 5,333,262 →
Application: 07/961,243 →
Void and Cluster Apparatus and Method for Generating Dither Templates
Patent: 5,535,020 →
Application: 07/961,244 →
Image Adjustment System for Translating Raw Input Levels to Adjusted Input Levels
Patent: 5,543,936 →
Application: 07/961,558 →
Imaging System with Two Level Dithering Using Comparator
Patent: 5,495,345 →
Application: 07/961,573 →
Imaging System with Multilevel Dithering Using Bit Shifter
Patent: 5,333,260 →
Application: 07/961,601 →
Object Transferring System and Method in an Object Based Computer Operating System
Patent: 5,297,283 →
Application: 07/962,397 →
Polling of I/O Device Status with Status Comparison Performed in the Polled I/O Device
Patent: 5,319,785 →
Application: 07/962,624 →
Switch Circuit for Setting and Signaling a Voltage Level
Patent: 5,428,640 →
Application: 07/965,123 →
Interference Suppression System
Patent: 5,321,724 →
Application: 07/965,525 →
Computer System Performance Evaluation System and Method
Patent: 5,450,349 →
Application: 07/967,110 →
Test Fixture for Electronic Components
Patent: 5,334,043 →
Application: 07/967,595 →
Combined Write-Operand Queue and Read-After-Write Dependency Scoreboard
Patent: 5,471,591 →
Application: 07/969,126 →
Timing Verification Using Synchronizers and Timing Constraints
Patent: 5,657,239 →
Application: 07/969,933 →
Reduced Tolerance Interconnect System
Patent: 5,313,369 →
Application: 07/970,721 →
Multi Instruction Register Mapper
Patent: 5,519,841 →
Application: 07/974,776 →
Arbiter with Programmable Dynamic Request Prioritization
Patent: 5,303,382 →
Application: 07/975,127 →
Method for Testing a Processor Module in a Computer System
Patent: 5,327,435 →
Application: 07/976,095 →
Method and System for Ensuring Interconnect Integrity in a Micro-Chip- Module
Patent: 5,363,048 →
Application: 07/977,531 →
Method of Handling Errors in Software
Patent: 5,291,494 →
Application: 07/978,053 →
Hollow Chip Package and Method of Manufacture
Patent: 5,885,853 →
Application: 07/979,552 →
Dynamic Assignment of Multicast Network Addresses
Patent: 6,018,771 →
Application: 07/981,274 →
System for Storing Pending Parity Update Log Entries, Calculating New Parity, Updating the Parity Block, and Removing Each Entry from the Log When Update Is Complete
Patent: 5,819,109 →
Application: 07/987,116 →
Automatic Signal Termination System for a Computer Bus
Patent: 5,313,595 →
Application: 07/988,773 →
Integrated Circuit Metal Film Interconnect Having Enhanced Resistance to Electromigration
Patent: 5,382,831 →
Application: 07/990,222 →
Trickle Charge Circuit for an Off-Line Switching Power Supply
Patent: 5,307,256 →
Application: 07/991,766 →
A Current Mode Switching Power Supply Overload Protection Circuit with False Fault Condition Screening
Patent: 5,416,689 →
Application: 07/991,768 →
Method for Providing Minimal Size Test Vector Sets
Patent: 5,444,717 →
Application: 07/993,339 →
Phase Delay Compensator Using Gator Signal Generated by a Synchronizer for Loading and Shifting of Bit Pattern to Produce Clock Phases Corresponding to Frequency Changes
Patent: 5,408,640 →
Application: 07/995,311 →
Method for Synchronization of Arithmetic Exceptions in Central Processing Units Having Pipelined Execution Units Simultaneously Executing Instructions
Patent: 5,341,482 →
Application: 07/995,341 →
Sequential Reference Management for Cache Memories
Patent: 5,432,919 →
Application: 07/997,493 →
Apparatus and Method of Data Transfer Between Systems Using Different Clocks
Patent: 5,347,559 →
Application: 07/998,714 →
Method and Apparatus for Reducing Checking Costs in Fault Tolerant Processors
Patent: 5,339,408 →
Application: 07/998,715 →
Method and Apparatus for Parity Generation
Patent: 5,557,622 →
Application: 08/000,518 →
Method for Comparing Data Structures That Cross Address Space Boundaries
Patent: 5,774,719 →
Application: 08/002,168 →
Method and Apparatus for Allocating Server Access in a Distributed Computing Environment
Patent: 5,452,459 →
Application: 08/002,197 →
Method for Testing, Debugging, and Comparing Computer Programs Using Concurrent Simulation of Program Paths
Patent: 5,291,497 →
Application: 08/006,187 →
Expert System Having a Plurality of Security Inspectors for Detecting Security Flaws in a Computer System
Patent: 5,812,763 →
Application: 08/008,066 →
Data Processing System and Method with Prefetch Buffers
Patent: 5,317,718 →
Application: 08/010,446 →
System for Determining the Rights of Object Access for a Server Process by Combining Them with the Rights of the Client Process
Patent: 5,321,841 →
Application: 08/011,293 →
Adapter for Interconnecting Single-Ended and Differential Scsi Buses to Prevent `Busy' or `Wired-or' Glitches from Being Passed from One Bus to the Other
Patent: 5,608,883 →
Application: 08/012,484 →
Position Independent Code Location System
Patent: 5,504,901 →
Application: 08/012,622 →
Key-Range Locking with Index Trees
Patent: 5,440,732 →
Application: 08/014,181 →
Concurrency-Control Method and Apparatus in a Database Management System Utilizing Key-Valued Locking
Patent: 5,485,607 →
Application: 08/014,188 →
Virtual Memory Management for Source-Code Development System
Patent: 5,301,327 →
Application: 08/015,062 →
Leading One/Zero Bit Detector for Floating Point Operation
Patent: 5,317,527 →
Application: 08/016,054 →
A Method and Apparatus for Controlling a Rounding Operation in a Floating Point Multiplier Circuit
Patent: 5,341,319 →
Application: 08/016,058 →
Fair Arbitration Scheme for Arbitrating Between Multiple Nodes in a Computer System Seeking Control of a Common Bus
Patent: 5,349,690 →
Application: 08/016,419 →
Method and Apparatus for Authenticating a Client to a Server in Computer Systems Which Support Different Security Mechanisms
Patent: 5,586,260 →
Application: 08/017,231 →
Using Pre-Analysis and a 2-State Optimistic Model to Reduce Computation in Transistor Circuit Stimulation
Patent: 5,694,579 →
Application: 08/019,574 →
Data Processing System and Method for Controlling the Latter as Well as a Cpu Board
Patent: 5,307,468 →
Application: 08/020,002 →
Adaptive Fault Identification System
Patent: 5,351,247 →
Application: 08/020,030 →
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Three-Port Josephson Memory Cell for Superconducting Digital Computer
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Semiconductor Device with Reduced Time-Dependent Dielectric Failures
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Remote Monitoring of High-Risk Patients Using Artificial Intelligence
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Object Code Processing System for Forming an Excutable Image by Trans- Forming Lisp-Type Object Files into a Format Compatible for Storage by a Linker
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Programmable Pixel and Scan-Line Offsets for a Hardware Cursor
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Bipolar Transistor Memory Cell and Method
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Object Oriented Computer Architecture Using Directory Objects
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Fault Tolerant Distributed Garbage Collection System and Method for Collecting Network Objects
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Optical Force Sensor for High Density Planar Electrical Interconnects
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Message Encryption Using a Hash Function
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Voltage-Tracking Circuit and Application in a Track-and-Hold Amplifier
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Peak Detector Circuit and Application in a Fiber Optic Receiver
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Planarization Process for Ic Trench Isolation Using Oxidized Polysilicon Filler
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Debugging a Computer Program by Simulating Execution Forwards and Backwards in a Main History Log and Alternative History Logs
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Power Line Transient Suppression Circuit Appliances
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Molded Bumper Rail for a Portable Computer
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Pc Board Cartridge for a Computer Terminal
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Combined Queue for Invalidates and Return Data in Multiprocessor System
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Write-Read/Write-Pass Memory Subsystem Cycle
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Virtual to Physical Address Translation Scheme with Granularity Hint for Identifying Subsequent Pages to Be Accessed
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Cash Pocket for an Automatic Teller Machine
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Document Display System for Organizing and Displaying Documents as Screen Objects Organizined Along Strand Paths
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Documents Having Executable Attributes for Active Mail and Digitized Speech to Text Conversion
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Memory Subsystem for Bitmap Printer Data Controller
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Register Logging in Pipelined Computer Using Register Log Queue of Register Content Changes and Base Queue of Register Log Queue Pointers for Respective Instructions
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Method of Recording, Playback and Re-Execution of Application Program Call Sequences and Import and Export of Data in a Digital Computer System
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System and Method for Communication Between Windowing Environments
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High Performance Substrate, Electronic Package and Integrated Circuit Cooling Process
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Hot Carrier-Hard Gate Oxides by Nitrogen Implantation Before Gate Oxidation
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Byte Aligned Data Compression
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Asynchronous Data Transfers Among a Plurality of Computer Devices
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High Density, High Speed, Semiconductor Interconnect Using-Multilayer Flexible Substrate with Unsupported Central Portion
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Method of Testing Semiconductor Chips with Reusable Test Package
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Network Font Server
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Method of Managing Requests in a Transaction Processing System
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Equipment Cabinet Door Mountable on Either Side and Having a Central Latch
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Equipment Cabinet Stand
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Extensible Entity Management System Including Rule-Based Alarms
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Method and Apparatus for Multiscript Access to Entries in a Directory
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A Shock Absorbing Apparatus for Mounting a Plurality of Storage Devices in a Stacked Configuration
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Message Passing Method
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Remote Display of an Image by Transmitting Compressed Video Frames Representing Background and Overlay Portions Thereof
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Occlusion Detection System for Locator Devices
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System and Method for Generating Glyphs of Unknown Characters
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System and Method for Calculating Raid 6 Check Codes
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Communication Systems
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Enhanced Cache Operation with Remapping of Pages for Optimizing Data Relocation from Cache Misses
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Interlocking Pedestal Assembly for a Computer Enclosure
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Fault Tolerant Computer System with Shadow Virtual Processor
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Bus Event Monitor
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Extensible Entity Management System Including a Dispatching Kernel and Modules Which Independently Interpret and Execute Commands
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Mechanism for Locating Without Search Discrete Application Resources Known by Common Name Only in a Distributed Network Computing Environment
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Embedded Features for Registration Measurement in Electronics Manufacturing
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Embedded Features for Monitoring Electronics Assembly Manufacturing Processes
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Method and Apparatus for Automatic Gap Closing in Computer Aided Drawing
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Method for Increased Performance from a Memory Stream Buffer by Eliminating Read-Modify-Write Streams from History Buffer
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Improved History Buffer Control to Reduce Unnecessary Allocations in a Memory Stream Buffer
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Method for Addressing a Block Addresasble Memory Using a Gray Code
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An Apparatus and Method for an Improved Content Addressable Memory Using a Random Access Memory to Generate Match Information
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Field Effect Transistor with Integrated Schottky Diode Clamp
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Method of Deriving a Per-Message Signature for a Dss or El Gamal Encryption System
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System for Monitoring Computer System Performance
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Optimizer for Program Loops
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System and Method for Adding New Waitable Object Types to Object Oriented Computer Operating System
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Interrupting Node for Providing Interrupt Requests to a Pended Bus
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Elastomeric Key Switch Actuator
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Method of Packaging and Assembling Opto-Electronic Integrated Circuits
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Protection Ring Extension for Computers Having Distinct Virtual Machine Monitor and Virtual Machine Address Spaces
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Interval Width Update Process in the Arithmetic Coding Method
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Affinity Scheduling of Processes on Symmetric Multiprocessing Systems
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High Powered Die with Bus Bars
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Memory Subsystem Command Input Queue Having Status Locations for Resolving Conflicts
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Programmable Data Transfer Timing
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Apparatus and Method for Intelligent Multiple-Probe Cache Allocation
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System for Selectively Storing Stripes of Data in Tracks of Disks So That Sum of Transfer Rates of Stripes Match Communication Bandwidth to Host
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Integration of Result Data from First Program Operations on Dynamic Source Data into Data of a Second Program
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Optimizing Compiler Using Templates Corresponding to Portions of an Intermediate Language Graph to Determine an Order of Evaluation and to Allocate Lifetimes to Temporary Names for Variables
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Noise-Free Analog Islands in Digital Integrated Circuits
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Managing the Fletching and Replacement of Cache Entries Associate with a File System
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Semiconductor Wafer Processing with Across-Wafer Critical Dimension Monitoring Using Optical Endpoint Detection
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Method of Constructing a Constant-Folding Mechanism in a Multilanguage Optimizing Compiler
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Compiler Back End Calling Predetermined Front End Routines That Use Effect and Dependency Indicators to Provide Information to the Compiler to Determine the Validity of an Optimazation
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Method and Apparatus for Cache Miss Reduction by Simulating Cache Associativity
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Trainable Apparatus for Predicting Instruction Outcomes in Pipelined Processors
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Method and Apparatus for Eliminating Branches Using Conditional Move Instructions
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Ring Based Distributed Communication Bus for a Multiprocessor Network
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Method for Providing a Security Facility for a Network of Management Servers Utilizing a Database of Trust Relations to Verify Mutual Trust Relations Between Management Servers
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Power Sequencing Control
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Multiple Reasoning and Result Reconciliation for Enterprise Analysis
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Order Preserving Data Translation
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Method and Apparatus for Producing Audio-Visual Synthetic Speech
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Memory Stream Buffer
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Distributed Configuration Profile for Computing System
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System and Method for Emulating a Window Management Environment Having a Uniform Windowing Interface
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System for Handling Cache Memory Victim Data Which Transfers Data from Cache to the Interface While Cpu Performs a Cache Lookup Using Cache Status Information
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Method and Apparatus for Updating a Duplicate Tag Status in a Snoop Bus Protocal Based Computer System
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Clock Architecture for Synchronous System Bus Which Regulates and Adjusts Clock Skew
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Low Skew Remote Absolute Delay Regulator Chip
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Method and Apparatus for Adaptive Memory Access
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Paddleless Molded Plastic Semiconductor Chip Package
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Buffer Descriptor Prefetch in Network and I/O Design
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Operand Specifier Processing by Grouping Similiar Specifier Types Together and Providing a General Routine for Each
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Method and Apparatus for Checking Validity of Memory Operations
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Software Mechanism for Accurately Handling Exceptions Generated by Speculatively Scheduled Instructions
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Instruction Coding to Support Parallel Execution of Programs
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Method and Apparatus to Provide Pended Transaction on a Non-Pended System Bus
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Method for Increasing the Performance of Lines Drawn into a Framebuffer Memory
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Static Random Access Memory Having Tunable Self-Timed Control Logic Circuits
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Software Mechanism for Accurately Handling Exceptions Generated by Instructions Scheduled Speculatively Due to Branch Elimination
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High Performance Fan Heatsink Assembly
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In-Register Data Manipulation for Unaligned Byte Write Using Data Shift in Reduced Instruction Set Processor
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Shift Register Divided into a Number of Cells and a Number of Stages Within Each Cell to Permit Bit and Multiple Bit Shifting
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Memory Reference Tagging
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System Independent Interface for Performance Counters
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System for Increasing the Difficulty of Password Guessing Attacks in a Distributed Authentication Scheme Employing Authentication Tokens
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License Document Interchange Format for License Management System
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Read-Write Buffer for Gathering Write Requests and Resolving Read Conflicts Based on a Generated Byte Mask Code
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Pattern Recognition Device
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Method and Apparatus for Protecting the Confidentiality of Passwords in a Distributed Data Processing System
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Pipelined Computer with Operand Context Queue to Simplify Context-Dependent Execution Flow
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Remote Display of an Image by Transmitting Compressed Video Frames Respresenting Back-Ground and Overlay Portions Thereof
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Method for Selectively Enabling Subset of Embedded Event-Making Instructions and Selecting Types and Items of Event-Based Data to Be Collected Per Enabled Instruction
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Delayed Acknowledgement in an Asymmetric Timer Based Lan Communications Protocol
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Method of Reducing the Complexity of an I/O Request to a Raid-4 or Raid-5 Array
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Transistor Fabrication Process in Which a Contact Metallization Is Formed with Different Silicide Thickness Over Gate Interconnect Material and Transistor Source/Drain Regions `
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Duplicate Cache Tag Store for Computer Graphics System
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Method Implemented by a Computer Network Adapter for Autonomously Adjusting a Transmit Commencement Threshold Value Upon Occurrence of an Underflow Condition
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Document Display System Using a Scripting Language Having Container Variables Setting Document Attributes
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Void and Cluster Apparatus and Mehtod for Generarting Dither Templates
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Clip-On Non-Snag Grounding Finger Array
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Fast Translation and Execution of a Computer Program on a Non-Native Architecture by Use of Background Translator
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Low Inductance Electrical Resistor Terminator Package
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Video Teleconferencing for Networked Workstations
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Memory System and Method for Selective Multi-Level Caching Using a Cache Level Code
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Alternate Execution and Interpretation of Computer Program Having Code at Unknown Locations Due to Transfer Instructions Having Computed Destination Addresses
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Wagering Solitaire Game
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Probe Card Shipping and Handling System
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Post Processing Timing of Rhythm in Synthetic Speech
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Enabling Mirror, Nonmirror and Partial Mirror Cache Modes in a Dual Cache System
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Option Card Slot Filler Plate
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Hinged Front Panel Assembly for Circuit Cards
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Rotating Battery Hinge for a Notebook Computer
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Integrated Thermal Coupling for Heat Generating Device
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Interleaved-Fin Thermal Connector
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Translation Buffer and Method for Translating Addresses Utilizing Invalid and Don't Care States
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System for Assigning Boot Strap Processor in Symmetric Multiprocessor Computer with Watchdog Reassignment
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System for Controlling a Write Operation Involving Data Held in a Write Cache
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Method of Memory Interleaving, and Memory Systems Interleaved Thereby
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Video Data Scaling for Video Teleconferencing Workstations Communicating by Digital Data Network
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Self-Referencing Modulation Circuit for Cmos Integrated Circuit Electrostatic Discharge Protection Clamps
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Efficient Method and Apparatus for Compiling and Linking Modules of Computer Code in a Large Software System
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Method of Minimizing Area for Fanout Chains in High-Speed Networks
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Entity Management System with Remote Call Feature
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Computer Method and Apparatus for Clustering Documents and Automatic Generation of Cluster Keywords
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Memory Bank Addressing Scheme
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Method and Apparatus for Performing Interrupt Frequency Mitigation in a Network Node
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Method and Apparatus for Performing Raw Cell Status Report Frequency Mitigation on Receive in a Network Node
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Self-Aligned Cobalt Silicide on Mos Integrated Circuits
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T-Shaped Locking Member for Engaging a Passageway in a Heat Sink for Securement to a Mounting Board
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Method and Apparatus for Detecting and Executing Cross-Domain Calls in a Computer System
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Method and Apparatus for Graphical Panning
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Paddleless Molded Plastic Semiconductor Chip Package
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Method of Rule Execution in an Expert System Using Equivalence Classes to Group Database Objects
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Method and Apparatus for Performing Retroactive Backups in a Computer System
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Dynamic Fine-Granted Dependency Analysis for a Functional Language
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Pseudo Network Adapter for Frame Capture, Encapsulation and Encryption
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Item Selection by Prediction and Refinement
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Arbitration Unit Which Requests Control of the System Bus Prior to Determining Whether Such Control Is Required
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Skipping Clock Interrupts During System Inactivity to Reduce Power Consumption
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Performance Optimization and System Bus Duty Cycle Reduction by I/O Bridge Partial Cache Line Writes
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Automatic Disk Drive Shelf Address Assignment and Error Detection Method and Apparatus
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Method and Apparatus for Automatic Gap Closing in Computer Aided Drawing
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Anti-Slamming Latch Apparatus for Modular Component Installations
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Automatic Mapping, Monitoring, and Control of Computer Room Components
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Parallel Distributed Printer Controller Architecture
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Attenuating Vibrations in a Mounting Shelf for Multiple Disk Drives
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High Frequency Emi Shield with Air Flow for Electronic Device Enclosure
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System and Method for Determining Attributes and Coupling Characteristics of Components by Comparatively Observing Provided Reference Signal
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Document Display System for Organizing and Displaying Documents as Screen Objects Organizing Along Strand Paths
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System and Method for Dynamically Analyzing and Improving the Performance of a Network
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Real-Time Data Cache Flushing Threshold Adjustment in a Server Computer
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Real-Time Data Cache Size Adjustment in a Server Computer
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Real-Time Open File Cache Hashing Table Restructuring in a Server Computer
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Semiconductor Structures and Packaging Methods
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Dynamic Sprites for Encoding Video Data
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Multi-Level Round Robin Arbitration System
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System Bus with Separate Address and Data Bus Protocols
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Thread Properties Attribute Vector Based Thread Selection in Multithreading Processor
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Automatic Detection of a Similar Device at the Other End of a Wire in a Computer Network
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Method for Quickly Painting and Copying Shallow Pixels on a Deep Frame Buffer
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Self-Locating Dual Motion Locking Apparatus for Joining Computer Housings
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Arbitration System for a Shared Dma Logic on a Network Adapter with a Large Number of Competing Requests Having Predicted Latency Field
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Reduced Static Raid Enclosure
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Method for Optimizing Items Represented in Permutation Spaces
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Variable-Grained Memory Sharing for Clusters of Symmetric Multi-Processors Using Private and Shared State Tables
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Guided Optical Communication
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Optical Broadcast Communication
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Communication Collision Detection
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Multiple Wavelength Transceiver
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Dynamic Non-Coherent Cache Memory Resizing Mechanism
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Variable Wavelenght Transceiver
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Method for Fabricating a High Performance Vertical Bipolar Npn or Pnp Transistor Having Low Base Resistance in a Standard Cmos Process
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Off-Line Clock Synchronization for Multiprocessor Event Traces
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Method and Apparatus for Secure Remote Programming of Firmware and Configurations of a Computer Over a Network
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Method and Apparatus for Secure Remote Wake-Up of a Computer Over a Network
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Automated Speech Alignment for Image Synthesis
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Extraction of Key Sections from Texts Using Automatic Indexing Techniques
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Method for Analyzing and Presenting Test Execution Flows of Programs
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Cabinet Slide Mounting Bracket
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Wallace-Tree Multipliers Using Half and Full Adders
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Disk Drive Locking Member with Handle
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Document Management System with Delimiters Defined at Run-Time
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A Hands-Free Interface to a Virtual Reality Environment Using Haead Tracking
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High Frequency Sampling of Processor Performance Counters
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Detecting Concurrency Errors in Multi-Threaded Programs
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Facial Image Method and Apparatus for Semi-Automatically Mapping a Face on to a Wireframe Topology
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Processor Performance Counter for Sampling the Execution Frequency of Individual Instructions
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Uninterruptible Power Supply with Fault Tolerance in a High Voltage Environment
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Method for Error Recovery Spinlock in Asymmetrically Accessed Multiprocessor Shared Memory
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Computer Having Internally Mounted Peripheral Devices with Moveable Adapter
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Pruning of Short Paths in Static Timing Verifier
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Fast Determination of Floating Point Sticky Bit from Input Operands
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Void and Cluster Apparatus and Method for Generating Dither Templates
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Division with Limited Carry-Propagation in Quotient Accumulation
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Interface That Permits Data Bus Signals to Pass Between High Frequency Processing Unit and Low Frequency Expansion Devices
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Temporally and Spatially Organized Database
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Method and Apparatus for Automatically Generating Hierarchical Categories from Large Document Collections
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Processor for Sequential Data Retrieval from a Relational Database
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Electro-Static Discharge Protection Device Having a Modulated Control Input Terminal
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Secure Web Tunnel
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Method and Apparatus for Reducing the Apparent Read Latency When Connecting Busses with Fixed Read Reply Timeouts to Cpus with Write-Back Caches
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Speech Data Collection Over the World Wide Web
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Method and Apparatus for Performing Atomic Transactions in a Shared Memory Multi Processor System
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Limited Virtual Address Aliasing and Fast Context Switching with Multi-Set Virtual Cache Without Backmaps
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Two-Way Lock Mechanism with Cam Action
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Adaptive Stream Buffers
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Method and Apparatus for Strengthening Passwords for Protection of Computer Systems
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Task Processing Optimization in a Multiprocessor System
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Distributed Data Bus Sequencing for a System Bus with Separate Address and Data Bus Protocols
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External Signal Attenuator for a Single-Ended Transmission Line
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Controlled Prefetching of Data Requested by a Peripheral
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Apparatus and Method for Providing Non-Blocking Pipelined Cache
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Automated Mapping of Facial Images to Animation Wireframes Topologies
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Graphic System with Read/Write Overlap Detector
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A System for Sampling Network Packets by Only Storing the Network Packet That Its Error Check Code Matches with the Reference Error Check Code
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Loader Conditionally Replacing a Code Sequence with a Functionally-Alike Code Sequence in an Executable Program Intended for Execution in Different Run-Time Environments
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Compiler Generating Functionally-Alike Code Sequence in an Executable Program Intended for Execution in Different Run-Time Environments
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Method and Apparatus for Organizing and Accessing Electronic Mail Messages Using Labels and Full Text and Label Indexing
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Environmently Compensated Speech Processing
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Method for Detecting Human Body Motion in Frames of a Video Sequence
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Web-Based Electronic Mail Server Apparatus and Method Using Full Text and Label Indexing
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Replacing Large Bit Component of Electronic Mail (E-Mail) Message with Hot-Link in Distributed Computer System
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Method for Filtering Mail Messages for a Plurality of Client Computers Connected to a Mail Service System
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Technique for Dynamically Generating an Address Book in a Distributed Electronic Mail System
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Method and Apparatus to Expand an on Chip Fifo into Local Memory
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Auto-Calibrating Digital Delay Circuit
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Method and Apparatus for Accessing Copies of Documents Using a Web Browser Request Interceptor
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Updatings and Method for Updating a Copy of a Remote Document Stored in a Local Computer System
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Method and Apparatus for Modifying Copies of Remotely Stored Documents Using a Web Browser
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Detection of Scsi Devices at Illegal Locations
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Input/ Output Bus System in a Tower Building Block Sysrem
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Tower Building Block System
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Content Addressable Memory Having Memory Cells Storing Don't Care States for Address Translation
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Method for Testing and Verification of a Cpu Using a Reference Model
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Interface with Dual Mode of Operation
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Method and Apparatus for Fault Tolerant Bios Addressing
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Cabinet Security State Detection
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Method and Apparatus for Updating Host Memory in an Adapter to Minimize Host Cpu Overhead in Servicing an Interrupt
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Compact Self-Aligned Body Contact Silicon-on-Insulator Transistor
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Large Memory Allocation Method and Apparatus
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Method for Recovering Radial Distortion Parameters from a Single Camera Image
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Multiprobe Instruction Cache with Instruction-Based Probe Hint Generation and Trainng Whereby the Cache Bank or Way to Be Accessed Next Is Predicted
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Method and Apparatus for Configuring a Computer System
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Performance Counters Controlled by Programmable Logic
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Space-Time Memory
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Fault Notification System and Process Using Local Area Network
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Printed Circuit Board Having a Well Structure Accommodating One or More Capacitor Components
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Method for Aligning Text with Audio Signals
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Method for Ignoring Redundant Constraints in a Graphic Editor
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Dual Pci Bridge Docking
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Energy Absorbing Viscoelastic Spacer for Reducing Vibration to Disk Drives
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Method and Apparatus for Generating an Extended Finite State Machine Architecture for a Software Specification
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Method and Apparatus for Statically Analyzing a Computer Program for Data Dependencies
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Method and Apparatus for Correlating Real-Time Audience Feedback with Segments of Broadcast Programs
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Fast Determination O Carry Inputs from Lower Order Product for Radix-8 Odd/Even Multiplier Array
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Method for Extracting a Three-Dimensional Model Using Appearance-Based Constrained Structure from Motion
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Method and Apparatus for Compositing Colors of Images with Memory Constraints for Storing Pixel Data
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Normalization Shift Prediction Independent of Operand Subtraction
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Method and Apparatus for Employing Commit-Signals and Prefetching to Maintain Inter-Reference Ordering in a High-Performance I/O Processor
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Method and Apparatus for Reducing Latency of Interreference Ordering in a Multiprocessor System
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Distributed Data Dependency Stall Mechanism
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Separate Victim Buffer Read and Release Control
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Order Supporting Mechanisms for Use in a Switch-Based Multi-Processor System
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Real Time Bit Map Capture and Sharing for Collaborative Tools
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System Fpr Compressing Bit Maps to Be Shared and Displayed in Collaborative Tool by Client and Server Systems
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Mechanism for Reducing Latency of Memory Barrier Operations on a Multiprocessor System
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Independent Victim Data Buffer and Probe Buffer Release Control Utilizing Control Flag
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Method and Apparatus for Releasing Victim Data Buffers of Computer Systems Using Victim Release Counters
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Employing Multiple Channels for Deadlock Avoidance in a Cache Coherency Protocol
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Method and Apparatus for Disambiguating Change-to-Dirty Commands in a Switch Based Multi-Processing System with Coarse Directories
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Technique for Reducing Latency of Inter-Reference Ordering Using Commit Signals in a Multiprocessor System Having Shared Caches
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Low Occupancy Protocol for Managing Concurrent Transactions with Dependencies
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Method and Apparatus for Delaying Victim Writes in a Switch-Based Multi-Processor System to Maintain Data Coherency
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Victimization of Clean Data Blocks
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A Multi-Processor Computer System Having a Data Switch with Simultaneous Insertion Buffers for Eliminating Arbitration Interdependencies
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Compression Protocol with Multiple Preset Dictionaries
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Method for Determining Target Address of Computed Jump Instructions in Executable Programs
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Prefetch Management for Dma Read Transactions Depending Upon Past History of Actual Transfer Lengths
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Link Time Optimization with Translation to Intermediate Program and Following Optimization Techniques Including Program Analysis Code Motion Live Variable Set Generation Order Analysis,Dead Code Eliminati on and Load Invariant Analyais
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Link Time Optimization via Dead Code Elimination Code Motion Code Partitioning Code Grouping Loop Analysis with Code Motion Loop Invariant Analysis and Active Variable to Register Analysis
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Inclusion Map for Accelerated Cache Flush
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Method and Apparatus for Resolving Overlapping Selection and Reselection Operations of Scsi Bus Protocols
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Sharing Memory Among Computer Processes
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Integrated Thermal Coupling for a Heat Generating Device
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Interleaved-Fin Thermal Connector
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Integrated Thermal Coupling for Heat Generating Device
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Apparatus and Method for Serialized Set Prediction
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System for Monitoring Computer System Performance
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Apparatus for Performing Fast Multiplication
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Method for Dynamically Remapping a Virtual Address to a Physical Address to Maintain an Even Distritution of Cache Page Addresses in a Virtual Address Space
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Memory Allocation Technique for Maintaining an Even Distribution of Cache Page Addresses Within a Data Structure
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Cross-Referenced Electrostatic Discharge Protection Systems and Methods for Power Supplies
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Method for Reclaiming Physical Pages of Memory While Maintaining an Even Distribution of Cache Page Addresses Within an Address Space
Patent: 5,996,055 →
Application: 08/979,738 →
Apparatus for Sampling Instruction Operand or Result Values in a Processor Pipeline
Patent: 5,923,872 →
Application: 08/979,848 →
Method for Estimating Statistics of Properties of Instructions Processed by a Processor Pipeline
Patent: 5,809,450 →
Application: 08/979,899 →
Method for Measuring Latencies by Randomly Selected Sampling of the Instructions While the Instruction Are Executed
Patent: 6,092,180 →
Application: 08/980,035 →
Method for Inserting Memory Prefetch Operations Based on Measured Latencies in a Program Optimizer
Patent: 5,964,867 →
Application: 08/980,145 →
Method for Estimating Statistics of Properties of Interactions Processed by a Processor Pipeline
Patent: 6,119,075 →
Application: 08/980,164 →
Method for Estimating Execution Rates of Program Execution Paths
Patent: 6,070,009 →
Application: 08/980,166 →
Apparatus for Randomly Sampling Instructions in a Procesor Pipeline
Patent: 6,000,044 →
Application: 08/980,190 →
Method and Apparatus for a Relaxed Bus Protocol Using Heuristics and Higher Level Supervision
Patent: 6,108,734 →
Application: 08/982,080 →
Bit-Depth Increase by Bit Replication
Patent: 6,038,576 →
Application: 08/982,954 →
Method and Apparatus for Controlling Providing of Conditioned Ac Power
Patent: 5,889,666 →
Application: 08/984,324 →
Apparatus and Method for Generating External Interface Signals in a Microprocessor
Patent: 5,943,492 →
Application: 08/985,597 →
Thermal Model for Central Processing Unit
Patent: 6,006,168 →
Application: 08/990,121 →
Distributed Packet Data with Centralized Snooping and Header Processing Router
Patent: 6,160,809 →
Application: 08/992,453 →
Bus Interface Slicing Mechanism Allowing for a Control/Data-Path Slice
Patent: 5,918,029 →
Application: 08/999,899 →
Transmission of an Error Message Over a Network by a Computer Which Fails a Self-Test
Patent: 6,145,102 →
Application: 09/009,084 →
Wake Up of a Sleeping Compute R Using I/O Snooping and Imperfect Packet Filtering
Patent: 6,085,328 →
Application: 09/009,788 →
Computer with Remote Wake Up and Transmission of a Status Packet When the Computer Fails a Self Test
Patent: 6,134,665 →
Application: 09/009,809 →
Method and Apparatus for Performing Error Detection
Patent: 6,098,179 →
Application: 09/010,899 →
Uninterruptible Power Supply with Fault Tolerance in a High Voltage Environment
Patent: 5,901,057 →
Application: 09/013,431 →
Techinque for Ordering Internal Processor Register Accesses
Patent: 6,122,728 →
Application: 09/017,297 →
Method and Apparatus for Optimizing the Performance of Ldxl and Stxc Interlock Instructions in the Context of a Write Invalidate Protocol
Patent: 6,141,734 →
Application: 09/017,752 →
Method and Apparatus for Maximizing Utilization of an Internal Processor Bus in the Context of External Transactions Running at Speeds Fractionally Greater Than Internal Transaction Times
Patent: 5,924,120 →
Application: 09/018,320 →
Technique for Processing Images
Patent: 6,141,434 →
Application: 09/019,548 →
Technique for Updating a Background Image
Patent: 6,184,858 →
Application: 09/019,549 →
Technique for Acknowledging Multiple Objects Using a Computer Generated Face
Patent: 6,043,827 →
Application: 09/020,038 →
Method and Apparatus for Accessing a Cache Memory Utilization Distingushing Bit Rams
Patent: 6,189,083 →
Application: 09/030,797 →
Method and Apparatus for a Fast Variable Precedence Priority Encoder with Optimized Round Robin Precedence Update Scheme
Patent: 6,028,452 →
Application: 09/031,943 →
Scalable Distributed File System
Patent: 6,173,293 →
Application: 09/039,057 →
Cache Memory Exchange Optimized Memeory Organization for a Computer System
Patent: 6,125,429 →
Application: 09/041,513 →
Reduced-Latency Floating-Point Pipeline Using Normalization Shifts of Both Operands
Patent: 6,018,756 →
Application: 09/041,905 →
Encoding of Failing Bit Addresses to Facilitate Multi-Bit Failure Detect Using a Wired-or Scheme
Patent: 6,076,176 →
Application: 09/044,275 →
A Method for Dynamically Adjusting Multimedia Content of a Web Page by a Server in According to Network Path Characteristics Between Client and Server
Patent: 6,243,761 →
Application: 09/048,652 →
Method and Apparatus for Test Data Generation
Patent: 5,878,054 →
Application: 09/054,793 →
Speculative Issue of Instruction Under a Load Miss Shadow
Patent: 6,098,166 →
Application: 09/058,487 →
Access Mechanism for Parallel Status Update for Multiple Servers
Patent: 6,205,474 →
Application: 09/060,066 →
Scanning Force Microscope Thermal Microprobe
Patent: 5,959,241 →
Application: 09/070,640 →
Technique for Controlling and Processing a Section of an Interactive Presentation Simultaneously with Detecting Stimulus Event in Manner That Overrides Process
Patent: 6,163,822 →
Application: 09/070,849 →
Computer Method and Apparatus for Translating Text to Sound
Patent: 6,076,060 →
Application: 09/071,441 →
Esd Protection Clamp for Mixed Voltage I/O Stages Using Nmos Transistors
Patent: 5,932,918 →
Application: 09/072,129 →
Esd Protection Clamp for Mixed Voltage I/O Stages Using Nmos Transistors
Patent: 6,097,071 →
Application: 09/072,130 →
Method and Apparatus for Adding or Removing Devices from a Computer System Without Restarting
Patent: 6,189,050 →
Application: 09/074,767 →
Method and Apparatus Based on Relational Database Design Techniques Supporting Modeling, Analysis and Automatic Hypertext Generation for Structured Document Collections
Patent: 6,212,530 →
Application: 09/076,373 →
Hierarchical Ring Buffers for Buffering Data Between Processor and I/O Device Permitting Data Writes by Processor and Data Reads by I/O Device Simultaneously Directed at Different Buffers at Different Levels
Patent: 6,112,267 →
Application: 09/086,134 →
Register Scoreboard Logic with Register Read Availibility Signal to Reduce Instruction Issue Arbitration Latency
Patent: 6,167,508 →
Application: 09/088,818 →
Method and Apparatus for Failure Recovery in a Multi-Processor Computer System
Patent: 6,199,179 →
Application: 09/095,266 →
Method and Apparatus for a Low Power Self Test of a Memory Subsystem
Patent: 6,067,649 →
Application: 09/095,435 →
Method and Apparatus for Minimizing Pincount Needed by External Memory Control Chip for Multiprocessors with Limited Memory Size Requirements
Patent: 6,199,153 →
Application: 09/099,383 →
Wearable Computing Device Mounted on Superior Dorsal Aspect of a Hand
Patent: 6,151,208 →
Application: 09/103,902 →
Method and Apparatus for Predicting Memory Dependence Using Store Sets
Patent: 6,108,770 →
Application: 09/103,984 →
Reservation and Dynamic Allocation of Resources for Sole Use of Docking Station Peripheral Device
Patent: 6,170,020 →
Application: 09/107,598 →
Enabling Access to a Selected One of Two Detected Same Type Peripheral Devices Connected to Separate Peripheral Slots in a Computer
Patent: 6,178,469 →
Application: 09/107,599 →
Charging System for Computer with Docking Station
Patent: 6,005,368 →
Application: 09/107,647 →
Dynamic Resource Allocation Across Bus Bridges
Patent: 6,216,192 →
Application: 09/107,940 →
.Peripheral Identification Using Bypassable Impedances Connected in Series
Patent: 6,138,182 →
Application: 09/108,933 →
Inter-Program Synchronous Communications Using a Collaboration Software System
Patent: 6,192,394 →
Application: 09/114,373 →
Phantom Resource Memory Address Mapping System
Patent: 6,185,654 →
Application: 09/118,985 →
Electromigration-Resistant via Structure
Patent: 6,096,637 →
Application: 09/124,198 →
User Transparent Mechanism for Profile Feedback Optimization
Patent: 6,158,049 →
Application: 09/132,449 →
High-Speed Cmos Latch
Patent: 6,084,455 →
Application: 09/133,235 →
Semi-Mobile Desktop Personal Computer
Patent: 6,097,593 →
Application: 09/133,874 →
Physical Security System for Portable Computer/Port Replicator
Patent: 6,151,218 →
Application: 09/137,592 →
Port Replicator with Secure Integral Battery Charging Cradle
Patent: 6,046,571 →
Application: 09/138,317 →
Method and Apparatus for Providing Transient Suppression in a Central Processor Unit (Cpu) Phase Locked Loop (Pll) Clock Signal Synthesis Circuit
Patent: 6,104,251 →
Application: 09/143,945 →
Pivoting Door System for a Portable Computer
Patent: 5,918,957 →
Application: 09/148,235 →
Hinge System for a Portable Computer
Patent: 6,202,256 →
Application: 09/148,740 →
Low Profile Surface Mount Transformer
Patent: 6,046,662 →
Application: 09/162,667 →
Methods and Apparatus for Controlling a Power Supply with Improved Techniques for Providing Protection Limits
Patent: 6,011,679 →
Application: 09/163,705 →
Methods and Apparatus for Synchronizing a Plurality of Power Supplies
Patent: 6,133,717 →
Application: 09/164,416 →
Method and Apparatus for Test Data Generation
Patent: 6,148,427 →
Application: 09/193,506 →
Computer Method and Apparatus for Text-to-Speech Synthesizer Dictionary Reduction
Patent: 6,208,968 →
Application: 09/212,874 →
Method and Apparatus for Balancing Load Vs. Store Acess to a Primary Data Cache
Patent: 6,163,821 →
Application: 09/215,354 →
Method and Apparatus for Optimizing Bcache Tag Performance by Inferring Bcache Tag State from Internal Processor State
Patent: 6,401,173 →
Application: 09/237,519 →
High Input Impedance, Strobed Cmos Differential Sense Amplifier with Double Fire Evaluate
Patent: 6,107,839 →
Application: 09/241,003 →
Embedded Input Logic in a High Input Impedance Strobed Cmos Differential Sense Amplifier
Patent: 6,195,377 →
Application: 09/241,212 →
Method and System for Controlling Radio Frequency Radiation in Microelectronic Packages Using Heat Dissipation Structures
Patent: 6,075,700 →
Application: 09/241,351 →
Generalized Push-Pull Cascode Logic Technique
Patent: 6,144,228 →
Application: 09/340,774 →
Apparatus and Method for Controlling Rate of Playback of Audio Data
Patent: 6,490,553 →
Application: 09/781,828 →
Publication: US 2002/0010916
Method for Manufacturing a Glass Sheet Having an Uneven Surface
Patent: 6,708,526 →
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Publication: US 2002/0038559
Related Assignments (2)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Jan 9, 2002
From: DIGITAL EQUIPMENT CORPORATION; COMPAQ COMPUTER CORPORATION
To: COMPAQ INFORMATION TECHNOLOGIES GROUP, L.P.
Reel/Frame 012447/0903 →
Assignment of Assignor's Interest Jul 25, 2002
From: DIGITAL EQUIPMENT CORPORATION; COMPAQ COMPUTER CORPORATION
To: COMPAQ INFORMATION TECHNOLOGIES GROUP, L.P.
Reel/Frame 013118/0226 →