IP Library › Assignment 012447/0903
Patent Assignment
Reel/Frame 012447/0903

Assignment of Assignor's Interest

Recorded: 2002-01-09 Pages: 21
Assignors
DIGITAL EQUIPMENT CORPORATION
Executed: 1999-12-09
COMPAQ COMPUTER CORPORATION
Executed: 2001-06-20
Assignee
COMPAQ INFORMATION TECHNOLOGIES GROUP, L.P.
20555 STATE HIGHWAY 249, HOUSTON, TEXAS, 77070
Covered Properties (1792)
Memory Initialization Circuit
Patent: 4,236,207 →
Application: 05/954,550 →
Cpu with Multi--Stage Mode Register for Defning Cpu Operating Environ- Ment Including Changing Its Communications Protocol
Patent: 4,519,028 →
Application: 06/234,926 →
Distributed Data Processing System
Patent: 4,430,699 →
Application: 06/235,291 →
Cached Multiprocessor System with Pipeline Timing
Patent: 4,392,200 →
Application: 06/239,129 →
Bidirectional Information Transmission via a Long Distance Video Interface (Ldvi) Cable
Patent: 4,390,900 →
Application: 06/256,440 →
Data Processing System with Lock-Unlock Instruction Facility
Patent: 4,488,217 →
Application: 06/265,173 →
Color Printing Apparatus
Patent: 4,407,595 →
Application: 06/298,087 →
Frequency-Independent, Self-Clocking Encoding Technique and Apparatus for Digital Communications
Patent: 4,475,212 →
Application: 06/301,193 →
Disk Format for Secondary Storage System
Patent: 4,434,487 →
Application: 06/308,771 →
Interface Between a Pair of Processors, Such as Host and Peripheral- Controlling Processors in Data Processing Systems
Patent: 4,449,182 →
Application: 06/308,826 →
Arbitration Scheme for a Multiported Shared Functional Device for Use in Multiprocessing Systems
Patent: 4,449,183 →
Application: 06/310,825 →
Bootstrap-Transimpedance Preamplifier for a Fiber Optic Receiver
Patent: 4,535,233 →
Application: 06/342,491 →
Interchangeable Interface Circuitry Arrangements for Use with a Data Processing System
Patent: 4,556,953 →
Application: 06/351,718 →
Electronic Keyboard
Patent: 4,467,150 →
Application: 06/351,719 →
Arrangement to Time Separate Bidirectional Current Flow
Patent: 4,446,382 →
Application: 06/351,720 →
Special Instruction Processing Unit for Data Processing System
Patent: 4,509,116 →
Application: 06/370,390 →
High-Speed Data Transfer Unit for Digital Data Processing System
Patent: 4,490,784 →
Application: 06/370,506 →
Two-Port Memory Controller
Patent: 4,509,115 →
Application: 06/370,520 →
Communications Device for Data Processing System
Patent: 4,527,236 →
Application: 06/372,624 →
Dual-Count, Round-Robin Distributed Arbitration Technique for Serial Buses
Patent: 4,560,985 →
Application: 06/375,983 →
Dual Path Bus Structure for Computer Interconnection
Patent: 4,490,785 →
Application: 06/376,068 →
Interface for Serial Data Communications Link
Patent: 4,450,572 →
Application: 06/376,069 →
Interactive Computer-Based Information Display System
Patent: 4,599,611 →
Application: 06/384,409 →
Apparatus for Combining a Video Signal with Graphics and Text from a Computer
Patent: 4,498,098 →
Application: 06/384,439 →
Central Processor with Means for Suspending Instruction Operations
Patent: 4,504,903 →
Application: 06/385,976 →
Control Arrangement for Data Processing System Employing Multiple Processors
Patent: 4,543,626 →
Application: 06/447,228 →
Address Conversion Unit for Multiprocessor System
Patent: 4,648,035 →
Application: 06/447,229 →
Bus for Data Processing System with Fault Cycle Operation
Patent: 4,543,628 →
Application: 06/461,838 →
Groups of Tag Signals for Data Store in Multi-Plane Set of Buffers
Patent: 4,689,765 →
Application: 06/461,996 →
Diagnostic System for a Digital Computer
Patent: 4,569,049 →
Application: 06/493,109 →
Method and Apparatus for Generating Graphic and Textual Images on a Raster Scan Display
Patent: 4,529,978 →
Application: 06/503,865 →
Planar Interconnect for Integrated Circuits
Patent: 4,617,193 →
Application: 06/505,046 →
System Intercommunication Processor Used in Distributed Data Processing System
Patent: 4,466,063 →
Application: 06/521,021 →
Heat Sink Arrangement with Clip-on Portion
Patent: 4,587,595 →
Application: 06/529,839 →
Alu with Carry Length Detection
Patent: 4,623,981 →
Application: 06/534,018 →
Bus-Control Mechanism
Patent: 4,661,905 →
Application: 06/534,781 →
Cache Invalidation Mechanism for Multiprocessor Systems
Patent: 4,648,030 →
Application: 06/534,782 →
Memory Subsystem
Patent: 4,982,360 →
Application: 06/534,927 →
Segmented Debugger
Patent: 4,589,068 →
Application: 06/538,371 →
Central Processing Unit for a Digital Computer
Patent: 4,586,130 →
Application: 06/538,373 →
Central Processor with Instructions for Processing Sequences of Characters
Patent: 4,556,951 →
Application: 06/540,510 →
Arrangement for Providing Data Signals for a Data Display System
Patent: 4,625,203 →
Application: 06/543,107 →
Buffer System for Input/Output Portion of Digital Data Processing System
Patent: 4,860,244 →
Application: 06/549,608 →
Pipeline Error Correction
Patent: 4,604,750 →
Application: 06/549,610 →
Microcode Control System for Digital Data Processing System
Patent: 5,093,775 →
Application: 06/549,611 →
Method and Apparatus for Self-Testing of Floating Point Accelerator Processors
Patent: 4,583,222 →
Application: 06/549,612 →
Circuit for Selecting and Locking in Operation Function Circuitry
Patent: 4,667,307 →
Application: 06/551,009 →
Bus Transceiver Including Compensation Circuit for Variations in Electrical Characteristics of Components
Patent: 4,614,882 →
Application: 06/554,493 →
A Digital Processor for Use in a Text to Speech System
Patent: 4,754,485 →
Application: 06/560,221 →
Analog Signal Verification Circuit
Patent: 4,552,992 →
Application: 06/560,237 →
Decoder for Self-Clocking Serial Data Communication
Patent: 4,592,072 →
Application: 06/578,883 →
Compression/Decompression System for Transmitting and Receiving Com- Pressed Picture Information Arranged in Rows and Columns of Pixels
Patent: 4,622,585 →
Application: 06/599,039 →
Integrated Circuit Chip Processing Techniques and Integrated Chip Produced Thereby
Patent: 4,584,761 →
Application: 06/610,337 →
Instruction Prefetch System for Conditional Branch Instruction for Central Processor Unit
Patent: 4,742,451 →
Application: 06/612,621 →
Automatic Method and Machine for the Simultaneous Testing of Data Processing Systems
Patent: 4,639,916 →
Application: 06/622,348 →
System for Altering Data Transmission Modes
Patent: 4,701,841 →
Application: 06/633,945 →
Multiple Phase Clock Buffer Module with Non- Saturated Pull- Up Transistor to Avoid Hot Electron Effects
Patent: 4,642,492 →
Application: 06/664,858 →
Scannable Flip-Flop
Patent: 4,669,061 →
Application: 06/684,357 →
Single Rail Cmos Register Array and Sense Amplifier Circuit Therefor
Patent: 4,792,924 →
Application: 06/692,815 →
Self-Timed Random Access Memory Chip
Patent: 4,712,190 →
Application: 06/694,874 →
Data Processing System Having a Control Device for Controlling an Intermediate Memory During a Bulk Data Transport Between a Source Device and a Destination Device
Patent: 4,562,534 →
Application: 06/720,041 →
Electronic Data Input Keyboard Comprising Keys Provided with Conductive Contacts
Patent: 4,709,228 →
Application: 06/720,787 →
Cursor Position Controller
Patent: 4,691,199 →
Application: 06/730,305 →
Computer System with Work Stations at Remote Positions and Reserve Battery Power Supply
Patent: 4,841,474 →
Application: 06/733,272 →
Multiple Chip Interconnection System and Package
Patent: 4,692,839 →
Application: 06/748,087 →
Retry Mechanism for Releasing Control of a Communications Path in a Digital Computer System
Patent: 4,706,190 →
Application: 06/755,952 →
Method of Fabricating Electrical Connector for Surface Mounting
Patent: 4,729,166 →
Application: 06/757,600 →
Interchangeable Interface Circuit Structure
Patent: 4,670,855 →
Application: 06/788,944 →
Memory for a Digital Data Processing System Including Circuit for Controlling Refresh Operations During Power-Up and Power-Down Conditions
Patent: 4,700,330 →
Application: 06/792,756 →
Video Display Control Circuit Arrangement
Patent: 4,769,637 →
Application: 06/802,226 →
Vertical Pwb Supply System
Patent: 4,804,434 →
Application: 06/805,121 →
Data Exchange Apparatus and Methods
Patent: 5,021,995 →
Application: 06/809,985 →
Method and Apparatus for a Constant Frequency Clock Source in Phase with a Variable Frequency System Clock
Patent: 4,748,644 →
Application: 06/823,729 →
Apparatus and Method for Responding to an Aborted Signal Exchange Between Subsystems in a Data Processing System
Patent: 4,858,173 →
Application: 06/823,775 →
Apparatus and Method for Increased System Bus Utilization in a Data Processing System
Patent: 4,809,218 →
Application: 06/823,801 →
Micrpogrammed Data Processing System Using Latch Circuits to Access Different Control Stores with the Same Instruction at Different Times
Patent: 4,794,527 →
Application: 06/823,804 →
Apparatus and Method for Providing a Cache Memory Unit with a Write Operation Utilizing Two System Clock Cycles
Patent: 4,755,936 →
Application: 06/823,805 →
Apparatus and Method for Addressing Semiconductor Arrays in a Main Memory Unit on Consecutive System Clock Cycles
Patent: 4,791,552 →
Application: 06/823,951 →
Digitally Implemented Modulators
Patent: 4,843,613 →
Application: 06/826,700 →
Transformation Circuit to Effect Raster Operations
Patent: 4,799,173 →
Application: 06/834,600 →
Micro-Electronics Devices and Methods of Manufacturing Same
Patent: 4,781,968 →
Application: 06/834,912 →
Electrical Connector for Surface Mounting and Method of Making of Thereof
Patent: 4,754,546 →
Application: 06/841,081 →
Apparatus for Transfering Blocks of Information from One Node to a Second Node in a Computer Network
Patent: 4,777,595 →
Application: 06/843,937 →
Anisotropic Elastomeric Interconnecting System
Patent: 4,778,950 →
Application: 06/853,313 →
Semiconductor Junction Temperature Emulator
Patent: 4,669,025 →
Application: 06/854,137 →
Communication System Including a First-in-First-Out Buffer
Patent: 4,769,769 →
Application: 06/854,259 →
Tilt Apparatus for Cathode Ray Tube Display
Patent: 4,769,634 →
Application: 06/862,095 →
Method and Apparatus for Producing Comparative Data
Patent: 4,936,778 →
Application: 06/863,061 →
Apparatus and Method for Compensation of Thermal Expansion of Cooling Fluid in Enclosed Electronic Packages
Patent: 4,700,272 →
Application: 06/879,199 →
Apparatus and Method for Execution of Floating Point Operations
Patent: 4,849,923 →
Application: 06/879,337 →
High Speed Interconnect Unit for Digital Data Processing System
Patent: 4,827,409 →
Application: 06/889,418 →
Apparatus and Method for Applying Rapid Transient Signals to Components on a Printed Circuit Board
Patent: 4,749,882 →
Application: 06/890,766 →
Horizontal Line Processor of Data to Be Printed Dot Sequentially
Patent: 4,825,386 →
Application: 06/900,028 →
Print Engine Data Interface
Patent: 4,809,216 →
Application: 06/900,057 →
Data Processor Performance Advisor
Patent: 4,849,879 →
Application: 06/904,093 →
Cache Invalidate Protocol for Digital Data Processing System
Patent: 4,814,981 →
Application: 06/908,825 →
Simd Array Processing System with Routing Netwark Having Plurality of Switching Stages to Transfer Massages Among Processors
Patent: 4,985,832 →
Application: 06/909,013 →
Computer System Comprising a Data, Address and Control Signal Bus Which Comprises a Left Bus and a Right Bus
Patent: 4,695,944 →
Application: 06/910,796 →
Method and Apparatus for Requesting Service of Interrupts by Selected Number of Processors
Patent: 4,769,768 →
Application: 06/917,319 →
Paper Feeding Method and Apparatus
Patent: 4,807,790 →
Application: 06/917,776 →
Adjustable Electrobed
Patent: 4,785,487 →
Application: 06/921,590 →
Bus Device for Use in a Computer System Having a Synchronous Bus
Patent: 4,763,249 →
Application: 06/924,578 →
Secondary Storage Facility Employing Serial Communications Between Drive and Controller
Patent: 4,811,278 →
Application: 06/944,955 →
Secondary Storage Facility Employing Serial Communications Between Drive and Controller
Patent: 4,825,406 →
Application: 06/946,891 →
Apparatus and Method for Monitoring Memory Accesses and Detecting Memory Errors
Patent: 4,811,347 →
Application: 07/008,672 →
Fire Resistant Materials
Patent: 4,748,066 →
Application: 07/011,418 →
Apparatus and Method for Testing Contact Interruptions of Circuit Interconnection Devices
Patent: 4,751,721 →
Application: 07/013,323 →
Access Verification Arrangement for Digital Data Processing System Which Has Demand-Paged Memory with Page Crossing Detection
Patent: 4,821,169 →
Application: 07/015,576 →
Central Processor Unit for Digital Data Processing System Including Write Buffer Management Mechanism
Patent: 4,851,991 →
Application: 07/017,518 →
Central Processor Unit for Digital Data Processing System Including Cache Management Mechanism
Patent: 4,831,581 →
Application: 07/017,645 →
Bus Interface Circuit for Digital Data Processor
Patent: 4,831,520 →
Application: 07/017,647 →
Apparatus and Method for Storing and Transmitting Images Represented
Patent: 4,835,599 →
Application: 07/018,491 →
Fast Bitonal to Gray Scale Image Scaling
Patent: 4,829,587 →
Application: 07/020,267 →
Apparatus and Method for Capacitor Coupled Complementary Buffering
Patent: 4,798,972 →
Application: 07/021,251 →
Arrangement for Expanding Memory Capacity
Patent: 4,744,025 →
Application: 07/021,522 →
Braille Encoding Method and Display System
Patent: 4,840,567 →
Application: 07/026,108 →
Edge Connector for Circuit Boards
Patent: 4,780,095 →
Application: 07/026,735 →
Apparatus and Method for Video Signal Image Processing Under Control of a Data Processing System
Patent: 4,918,526 →
Application: 07/028,404 →
Apparatus and Method for Providing a Wireless Link Between Two Local Area Network Systems
Patent: 4,876,742 →
Application: 07/029,214 →
Shock and Vibration Isolation Locking System
Patent: 4,749,164 →
Application: 07/029,331 →
Evaluation System for Determining Analogy and Symmetric Comparison Among Objects in Model-Based Computation Systems
Patent: 4,905,162 →
Application: 07/032,161 →
Key-Embedded Braille Display System
Patent: 4,752,772 →
Application: 07/033,358 →
Heat Exchange Element and Enclosure Incorporating Same
Patent: 4,840,225 →
Application: 07/037,046 →
Virtual Address Table Look Aside Buffer Miss Recovery Method and Apparatus
Patent: 4,920,477 →
Application: 07/040,990 →
Hierarchical Priority Branch Handling for Parallel Execution in a Parallel Processor
Patent: 4,833,599 →
Application: 07/041,081 →
High Performance Low Pin Count Bus Interface
Patent: 4,829,515 →
Application: 07/044,467 →
Node Adapted for Backplane Bus with Default Control
Patent: 5,003,467 →
Application: 07/044,468 →
Lookahead Bus Arbitaration System with Override of Conditional Access Grants by Bus Cycle Extensions for Multicycle Data Transfers
Patent: 4,980,854 →
Application: 07/044,470 →
Method and Apparatus for Initiating Interlock Read Transactions on a Multiprocessor Computer Systim
Patent: 4,941,083 →
Application: 07/044,486 →
Lookahead Bus Arbitration System with Override of Conditional Access Grants by Bus Cycle Extensions for Multicyle Data Transfers
Patent: 4,947,368 →
Application: 07/044,490 →
Node for Servicing Interrupt Request Messages on a Pended Bus
Patent: 4,953,072 →
Application: 07/044,755 →
Method and Apparatus for Assuring Adequate Access to System Resources by Processors in a Multiprocessor Computer System
Patent: 4,937,733 →
Application: 07/044,952 →
Backplane Bus with Default Control
Patent: 4,837,736 →
Application: 07/044,953 →
Method and Apparatus for Managing Multiple Lock Indicators in a Multi- Processor Computer System
Patent: 4,858,116 →
Application: 07/044,954 →
Multilayer Interconnection System for Multichip High Performance Semiconductor Packaging
Patent: 4,770,897 →
Application: 07/046,160 →
Self-Testing Memory
Patent: 4,782,486 →
Application: 07/049,812 →
Automatic Sizing Memory System System with Multiplexed Configuration Signals at Memory Modules
Patent: 4,980,850 →
Application: 07/049,816 →
Apparatus and Method for an Extended Arithmetic Logic Unit for Expediting Selected Floating Point Operations
Patent: 4,811,272 →
Application: 07/050,748 →
Apparatus and Method for Performing a Shift Operation in a Multiplier Array Circuit
Patent: 4,887,232 →
Application: 07/050,749 →
Byte Write Error Code Method and Apparatus
Patent: 4,817,095 →
Application: 07/050,839 →
Extraction-Insertion Card Guide Mechanism
Patent: 4,778,401 →
Application: 07/055,197 →
Method of Forming a Multilevel Interconnection Device
Patent: 4,812,191 →
Application: 07/055,794 →
Chromium Etchant for Positive Photoresist
Patent: 4,940,510 →
Application: 07/055,844 →
Secondary Storage Facility Employing Serial Communications Between Drive and Controller
Patent: 4,811,279 →
Application: 07/058,591 →
Tape Automated Bonding Semiconductor Package
Patent: 4,914,741 →
Application: 07/059,051 →
Needle Printing Head
Patent: 4,744,682 →
Application: 07/062,922 →
Apparatus and Method for Acceleration of Effective Subtraction Procedures by the Approximation of the Absolute Value of the Exponent Argument Difference
Patent: 4,858,165 →
Application: 07/064,835 →
Apparatus and Method for Accelerating Floating Point Addition and Subtraction Operations by Accelerating the Effective Subtraction Procedure
Patent: 4,852,039 →
Application: 07/064,836 →
Apparatus and Method for Expediting Subtraction Procedures in a Carry/Save Adder Mulitplication Unit
Patent: 4,862,405 →
Application: 07/068,262 →
Multiport Memory and Source Arrangement for Pixel Information
Patent: 4,851,834 →
Application: 07/068,728 →
Apparatus and Method for Recovering from Missing Page Faults in Vector Data Processing Operations
Patent: 5,063,497 →
Application: 07/069,372 →
Thermal Package for Electronic Components
Patent: 4,887,147 →
Application: 07/069,406 →
Bcd Adder Circuit
Patent: 4,805,131 →
Application: 07/072,161 →
Method of Assembling Tab Bonded Semiconductor Chip Package
Patent: 4,843,695 →
Application: 07/073,991 →
Apparatus and Method for Storing Performance Parameters of Local Area Network System Members
Patent: 4,799,211 →
Application: 07/076,724 →
Video Circuit Enclosure for Attachment to a Cathode Ray Tube
Patent: 4,873,578 →
Application: 07/078,778 →
Mounting Chassis for a Graphics Function Control Unit
Patent: 4,879,635 →
Application: 07/083,655 →
Tri-State Function Indicator
Patent: 4,837,565 →
Application: 07/084,845 →
Console Emulation for a Graphics Workstation
Patent: 4,903,218 →
Application: 07/084,930 →
High Performance Graphics Workstation
Patent: 5,155,822 →
Application: 07/085,081 →
D.C. Power Monitor
Patent: 4,797,608 →
Application: 07/085,095 →
Communication Protocol
Patent: 4,860,292 →
Application: 07/085,096 →
Peripheral Repeater Box
Patent: 4,905,232 →
Application: 07/085,097 →
System for Accumulating Data into Packet and Transmitting When Equal to Message Length or Predetermined Interval After Last Data Was Received
Patent: 5,123,091 →
Application: 07/085,098 →
Sysem Permitting Peripheral Interchangeability During System Operation
Patent: 4,862,355 →
Application: 07/085,105 →
Apparatus and Method for Using a Single Carry Chain for Leading One Detection and for "Sticky" Bit Calculation
Patent: 4,864,527 →
Application: 07/088,392 →
Drilling Apparatus and Method
Patent: 4,839,497 →
Application: 07/092,558 →
Reconfigurable Bus
Patent: 4,933,845 →
Application: 07/093,200 →
Method and Apparatus for Error Recovery in a Multibus Computer System
Patent: 4,858,234 →
Application: 07/093,476 →
Method and Apparatus for Interconnecting Busses in a Multibus Computer System
Patent: 4,979,097 →
Application: 07/093,479 →
Bus Adapter Module with Improved Error Recovery in a Multibus Computer System
Patent: 4,837,767 →
Application: 07/093,480 →
Bus Adapter Module for Interconnecting Busses in a Multibus Computer System
Patent: 4,864,496 →
Application: 07/093,488 →
Vector Register System for Executing Plural Read/Write Commands Concurrently & Independently Routing Data to Plural Read/Write Ports
Patent: 4,980,817 →
Application: 07/093,499 →
Bus Window Interlock
Patent: 4,897,786 →
Application: 07/093,501 →
Interface of Non-Fault Tolerant Components to Fault Tolerant System
Patent: 4,916,704 →
Application: 07/093,539 →
Dual-Rail Processor with Error Checking at Single Rail Interfaces
Patent: 4,907,228 →
Application: 07/093,584 →
Boot System for Distributed Digital Data Processing System
Patent: 4,885,770 →
Application: 07/093,811 →
Card Cage System
Patent: 5,218,519 →
Application: 07/093,970 →
Arrangemeny with Cooperating Management Server Node and Network Service Node
Patent: 5,005,122 →
Application: 07/094,169 →
Apparatus and Method for Secure Transmission of Data Over an Unsecure Transmission Channel
Patent: 4,881,263 →
Application: 07/101,125 →
Apparatus and Method for a Pipelined Central Processing Unit in a Data Processing System
Patent: 4,991,078 →
Application: 07/101,983 →
Apparatus and Method for Synchronization of a Coprocessor Unit in a Pipelined Central Processing Unit
Patent: 4,943,915 →
Application: 07/101,984 →
Method for Operating a Parallel Processing System and Related Apparatus
Patent: 4,965,882 →
Application: 07/103,364 →
Low Impedance Cable and Connector
Patent: 4,808,773 →
Application: 07/103,832 →
Constant Flow Deionized Water Spray Gun
Patent: 4,875,625 →
Application: 07/107,620 →
Integral Heat Pipe Module
Patent: 4,833,567 →
Application: 07/107,890 →
Method and Apparatus for Adaptive Data Compression
Patent: 4,881,075 →
Application: 07/108,892 →
Computer Interconnect Coupler Employing Crossbar Switching
Patent: 4,845,722 →
Application: 07/109,503 →
System for Specifying and Executing Protocols for Using Iterative Analogy and Comparative Induction in a Model-Based Computation System
Patent: 4,899,290 →
Application: 07/109,555 →
Hierarchical Arbitration System
Patent: 4,897,833 →
Application: 07/110,009 →
Computer Interconnect Coupler for Clusters of Data Processing Devices
Patent: 4,887,076 →
Application: 07/110,513 →
Bus Data Path Control Scheme
Patent: 4,965,723 →
Application: 07/111,642 →
Disk Plating System
Patent: 4,822,467 →
Application: 07/113,872 →
Apparatus and Method for Multi-Threaded Program Execution in a Microcoded Data Processing System
Patent: 4,953,078 →
Application: 07/114,644 →
Massively Parallel Array Processing System with Processors Selectively Accessing Memory Module Locations Using Address in Mocroword or in Address Register
Patent: 5,230,079 →
Application: 07/121,563 →
Distributed Arbitration Apparatus and Method for Shared Bus
Patent: 4,920,486 →
Application: 07/123,382 →
Apparatus and Method for Determining Network Component Locations on a Local Area Network System Cable Segment
Patent: 4,896,315 →
Application: 07/123,890 →
Software Configurable Memory Architecture for Data Processing System Having Graphics Capability
Patent: 4,953,101 →
Application: 07/124,897 →
High Speed Parallel Multiplier Circuit
Patent: 5,159,568 →
Application: 07/124,926 →
Method of and Apparatus for Surface Mounting Electronic Components Onto a Printed Wiring Board
Patent: 4,872,261 →
Application: 07/131,652 →
Current Mode Logic Switching Circuit Having a Schmitt Trigger
Patent: 4,812,676 →
Application: 07/135,457 →
Method of Tiling a Figure in Graphics Rendering System
Patent: 4,935,880 →
Application: 07/137,752 →
Apparatus and Method for Testing Impedances of Interconnect Devices
Patent: 4,859,952 →
Application: 07/137,928 →
Method and Apparatus Using a Cache and Main Memory for Both Vector Processing and Scalar Processing by Prefetching Cache Blocks Including Vector Data Elements
Patent: 4,888,679 →
Application: 07/142,794 →
Apparatus and Method for Removal of Heat from Packaged Element
Patent: 4,800,956 →
Application: 07/145,641 →
Apparatus and Method for Cooling Electronic Component Packages Using an Array of Directed Nozzles Fabricated in the Circuit Board
Patent: 4,839,774 →
Application: 07/147,755 →
Mechanism for Arbitrating Client Access to a Networked Print Server
Patent: 5,014,221 →
Application: 07/149,420 →
Test Fixture for Electronic Components
Patent: 4,842,526 →
Application: 07/151,577 →
Device for Filling the Magazine of a Scalp Clip Applicator with C- Shaped Scalp Clips
Patent: 4,929,239 →
Application: 07/152,762 →
Secondary Storage Facility Employing Serial Communications Between Drive and Controller
Patent: 4,837,675 →
Application: 07/153,518 →
Bipolar Ram Having State Dependent Write Current
Patent: 4,853,898 →
Application: 07/155,021 →
Bipolar Ram Having No Write Recovery Time
Patent: 4,864,540 →
Application: 07/155,022 →
Parallel Associative Memory Having Improved Selection and Decision Mechanisms for Recognizing and Sorting Relevant Patterns
Patent: 5,014,327 →
Application: 07/156,542 →
A Printing Apparatus and Method for Printing a Plurality of Pages Onto a Single Sheet
Patent: 4,928,252 →
Application: 07/159,947 →
Repeater Interlock Scheme
Patent: 4,974,153 →
Application: 07/162,620 →
Aiding the Design of an Operation Having Timing Interactions by Operating a Computer System
Patent: 4,965,758 →
Application: 07/162,624 →
Acoustic Noise Control for Fans
Patent: 4,807,718 →
Application: 07/163,397 →
Loadable Ripple Counter
Patent: 4,891,827 →
Application: 07/164,584 →
Voltage Controlled High-Frequency Attenuator
Patent: 4,839,611 →
Application: 07/164,817 →
Software Licensing Management System
Patent: 4,937,863 →
Application: 07/164,944 →
Self-Timed Programmable Logic Array with Pre-Charge Circuit
Patent: 4,794,570 →
Application: 07/165,456 →
Apparatus and Method for Data Copy Consistency in a Multi-Cache Data Processing Unit
Patent: 4,847,804 →
Application: 07/166,814 →
Single-Stage, Extensible Sorter for Sorting Data and Efficiently Reading Out Sorted Data, Incorporating Single-Bit Devices
Patent: 5,068,822 →
Application: 07/168,974 →
Capacitive Boost Circuit for Extending Hold Up Time
Patent: 4,811,190 →
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Surface Mount Technology Repair Station and Method for Repair of Surface Mount Technology Circuit Boards
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Integrated Circuit Having Laser-Alterable Metallization Layer
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Exception Reporting Mechanism for a Vector Processor
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Context Switching Method and Apparatus for Use in a Vector Processing System
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Micro-Electronics Devices and Methods of Manufacturing Same
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Test Fixture for Tab Circuits and Devices
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Single Rail Cmos Register Array and Sense Amplifier Circuit Therefor
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Multifunctional Enclosure for Wiring Board in Display
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Method and Apparatus for Acclerated Addition of Sliced Addends
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Cache Memory System
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Method and Apparatus for Branching on the Previous State in an Interleaved Computer Program
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Apparatus and Method for Reconstructing a Microstack
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Apparatus and Method for Replaying Decoded Instructions
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Ecl Mux Latch
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Cycle Counter for Timeout Microdiagnostics
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Data Processing System Having a Data Memory Interlock Coherency Scheme
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Method and Apparatus for High Performance Division
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Method of Forming a Salicided Self-Aligned Metal Oxide Semiconductor Device Using a Disposable Silicon Nitride Spacer
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Method and Apparatus for Testing Linear Motion Devices
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Method of Integrating Software Application Programs Using an Attributive Data Model Database
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Data Processing System Having a Data Structure with a Single, Simple Primitive
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A Method and Apparatus for the Continuous and Asynchronous Traversal and Processing of Graphics Data Structures
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On-Line Filtration of Potassium Permanganate
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Ride-Through Energy Boost Circuit
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Lossless Overcurrent Sensing Circuit for Voltage Regulator
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Apparatus for Exchanging Pixel Data Among Pixel Processors
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Method and Apparatus for Providing High Speed Parallel Transfer of Bursts of Data
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Apparatus and Method for Realtime Monitoring of Network Sessions in a Local Area Network
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Rack for Circuit Boards of an Electrical System
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System with a N Stages Timing Silo and P Stages Information Silo for Siloing Information
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System Which Directionally Sums Signals for Identifying and Resolving Timing Inconsistencies
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Method for Specifying and Controlling the Invocation of a Computer Program
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Pixel Lookup in Multiple Variably-Sized Hardware Virtual Colormaps in a Computer Video Graphics System
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Data Path Chip Test Architecture
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Semaphore Controlled Video Chip Loading in a Computer Video Graphics System
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Central Processing Unit for a Digital Computer
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Central Processing Unit for a Digital Computer
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Pixel Data Formatting
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Programmable Ceramic High Performance Custom Package
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High Input Impedance, Strobed Cmos Differential Sense Amplifier
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Method and Apparatus for Filtering Invalidate Requests
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Window-Dependent Buffer Selection
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Extendable-Size Color Look-Up Table for Computer Graphics Systems
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Method for Maintaining a Correct Time in a Distributed Processing System
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Video Imaging Device with Image Altering Controls and Related Method
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System for Processing Data to Facilitate the Creation of Executable Images
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System for Graphically Representing and Manipulating Data Stored in Databases
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Outer Lead Tape Automated Bonding
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Exactly-Once Semantics in a Tp Queuing System
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Efficient Protocol for Communicating Between Asychronous Devices
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Method for Implementing Synchronous Pipeline Exception Recovery
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Application of State Silos for Recovery from Memory Management Exceptions
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Microinstruction Addressing in High-Speed Cpu
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Method and Apparatus for Optimizing Inter-Processor Instruction Transfers
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Pipeline Bubble Compression in a Computer System
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Pipelined Digital Cpu with Deadlock Resolution
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Method and Apparatus for Predicting Valid Performance of Virtual-Address to Physical-Address Translations
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A Pipeline Having an Integral Cache Which Processors Csche Misses and Loads Data in Parallel
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Radix-16 Divider Using Overlapped Quotient Bit Selection an Concurrent Rounding and Correction
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Read Apparatus Having Vertical Turret Magazine for Information Discs
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Method and Apparatus for Transmitting and Receiving Characters Using a Balanced Weight Error Correcting Code
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Method of Fabricating Interconnect Layers on an Integrated Circuit Chip Using Seed-Grown Conductors
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Remote Bootstrapping a Node Over Communication Link by Initially Requesting Remote Storage Access Program Which Emulates Local Disk to Load Other Programs
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Memory Testing System
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Load/Store with Write-Intent for Write-Back Caches
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Bilingual Cmos to Ecl Output Buffer
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Method of Multicast Message Distribution
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System and Method for Garbage Collection with Ambiguous Roots
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Graphics Workststation for Greating Graphics Data Structures Which Are Stored Retrieved and Displayed by a Graphics Subsystem for Competing Programs
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Object Identifier Generator for Distributed Computer System
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Electronic Module Rfi/Emi Shielding
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Circuit Arrangement for a Picture Display Device for the Stabilization of the Size of the Picture Displayed
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Heat Exchange Element
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Method and Apparatus for Plotting Polygon Edges on a Pixelized Grid
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Easily Upgradeable Video Memory System and Method
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Pass-Through and Isolation Switch
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Memory Apparatus for Multiple Processor Systems
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Self-Timed Programmable Logic Array with Pre-Charge Circuit
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Connector Alignment Verification and Monitoring System
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Micro-Beam Tactile Sensor for the Measurement of Vertical Position Displacement,
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Real Time,Concurrent Garbage Collection System and Method
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Conducting Tube
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Method for Updating Data from a Cache Address Location to Main Memory and Maintaining the Cache Address in Registration Memory
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Method and Apparatus for Reducing Memory Read Latency in a Shared Memory System with Multiple Processors
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Integrated Circuit Having Laser-Alterable Metallization Layer
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Bad Data Algorithm
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Read-Modify-Write Operation
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Programmable Data Transfer Timing
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Interface Between a System Control Unit and a Service Processing Unit of a Digital Computer
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Modular Crossbar Interconnection Network for Data Transactions Between System Units in a Multi-Processor System
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Pipelined Floating Point Adder for Digital Computer
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Memory Configuration for Use with Means for Interfacing a System Control Unit for a Multi-Processor System with the System Main Memory
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Synchronizing and Processing of Memory Access Operations in Multiprocessor Systems Using a Directory of Lock Bits
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Branch Prediction
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Method and Apparatus for Resolving a Variable Number of Potential Memory Access Conflicts in a Pipelined Computer System
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System for Queuing Individual Read or Write Mask and Generating Respective Composite Mask for Controlling Access to General Puropose Register
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Method and Apparatus for Increasing the Data Storage Rate of a Computer System Having a Predefined Data Path Width
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Method and Apparatus for Detecting and Correcting Errors in a Pipelined Computer System
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Virtual Instruction Cache System Using Length Responsive Decoded Instruction Shifting and Merging with Prefetch Buffer Outputs to Fill Instruction Buffer
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Control of Multiple Functional Units with Parallel Operation in a Microcoded Execution Unit
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Simultaneously or Sequentially Decoding Multiple Specifiers of a Variable Length Pipeline Instruction Based on Detection of Modified Value of Specifier Registers
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Method and Apparatus Using a Source Operand List and a Source Operand Pointer Queue Between the Execution Unit and the Instruction Decoding and Operand Processing Units of a Pipelined Data Processor
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System for Preprocessing Auto Mode Implied Register Specifiers in a Pipelined Processor
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Method and Apparatus for Interfacing a System Control Unit for a Multi-Processor
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System for Delaying Processing of Memory Access Execution of an Instruction Pipeline of a Virtual Memory System Based Digital Computer
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Method and Apparatus for Ordering and Queueing Multiple Memory Requests
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System for Arbitrating Communication Requests Using Multi-Pass Control Unit Based on Availability of System Resources
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Apparatus and Method for a Quasi-Resonant Dc to Dc Bridge Converter
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Method and Apparatus for Simultaneously Decoding Three Operands in a Variable Length Instruction When One of the Operands Is Also of Variable Length
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Johnson Counter Circuit with Invalid Position Detection and Correction Mechanism
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Division Method and Apparatus Including Use of a Z-Z Plot to Select Acceptable Quotient Bits
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Apparatus and Method for Prohibiting Access in a Multi-Cache Data Processing System to Data Signal Groups Being Processed by a Data Processing Subsystem
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Expert System for Performing Diagnostic and Redesign Operations Incorporatiing Multiple Levels of Simulation Detail
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Methods of Maintaining Cache Coherence and Processor Synchronization in a Multiprocessor System Using Send and Receive Instructions
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Network Transit Prevention
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Multi-Component Test Fixture
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Skewed Xor Data Storage Process
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A Normalizer for Determining the Positions of Bits That Are Set in a Mask
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Node with Coupling Resistor for Limiting Current Flow Through Driver During Overlap Condition
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Memory Device for Storing Vector Registers
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Computer System Comprising a Main Bus and an Additional Communication Means Directly Connected Between Processor and Main Memory
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Dual-Path Computer Interconnect System with Zone Manager for Packet Memory
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Computer Interconnect System with Transmit-Abort Function
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Apparatus and Method for Secure Transmission of Data Over an Unsecure Transmission Channel
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Deposition of a Conductive and Protective Coating on a Metallic Substrate
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Rotating Priority Encoder Operating by Selectively Masking Input Signals to a Fixed Priority Encoder
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Method of Making Semiconductor Chip Having Field Effect Transistors Which Have Differing Threshold Voltages Determined in a Masking Step
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Integrated Module Handle and Chassis Bulkhead for Reducing Electromagnetic Interference Emissions from Circuit Modules
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System for Displaying Video from a Plurality of Sources on a Display
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System Including Inductive Learning Arrangement for Adaptive Management of Behavior of Complex Entity
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Battery Charger for Charging a Plurality of Batteries
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Dual Rail Processors with Error Checking on I/O Reads
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Fault Tolerant Computer Systems with Fault Isolation and Repair
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An Apparatus and Method for Providing Fast Data Transfer Between Multiple Devices Through Dynamic Reconfiguration of the Memory Spaces of the Devices
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Corrugated Strip Gasket for an Electronic Enclosure Joint to Reduce Both Electromagnetic and Radio Frequency Radiation
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Vsli Latch System and Sliver Pulse Generator with High Correlation Factor
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Expert System for Performing Beta-Token Partitioning in a Rete Network
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Multiple Bit Error Detection and Correction System Employing a Modified Reed-Solomon Code Incorporating Address Parity and Catastrophic Failure Detection
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Reliable Broadcast of Information in a Wide Area Network
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System for Updating Program Stored in Eeprom by Storing New Version into New Location and Updating Second Transfer Vector to Contain Starting Address of New Version
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Linear Address Conversion
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Method for Quickly Acquiring and Using Very Long Traces of Mixed System and User Memory References
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Electronically Controlled Wave Solder Mask Shield
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Laser Relow Soldering Process and Bonded Assembly Formed Thereby
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Information Object Transport System
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Tabular Data Format
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Digital Computer Using Data Structure Including External Reference Arrangement
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System for Selectively Converting Plurality of Source Data Structures Through Corresponding Source Intermdiate Structures, and Target Intermdiate Structures into Selected Target Structure
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Localized Cooling Apparatus for Cooling Integrated Circuit Devices
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Neural Network for Performing Beta-Token Partitioning in a Rete Network
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Signal Transmission and Receiving System with Looped Transmission Line
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Dynamic Heat Sink
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Backplane Bus System Including a Plurality of Nodes
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Apparatus and Method for Calibrated Monitoring of Output Voltage Levels of Local Area Network Communication Devices
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Minimizing the Interconnection Cost of Electronically Linked Objects
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Method of Transmitting Data at Full Bandwidth Within a Synchronous System When Clock Skew Plus Delay Exceeds the Cycle Time
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Reconfiguration System and Method for High-Speed Mesh Connected Local Area Network
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High-Speed Mesh Connected Local Area Network
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Apparatus and Method for Interconnecting a Plurality of Devices to a Single Node in a Node-Limited Serial Data Bus Computer Network
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Defect Tolerant Set Associative Cache
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Rendering Shaded Areas with Boundary-Localized Pseduorandom Noise
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Series Terminated Ecl Buffer Circuit and Method with an Optimized Temperaure Compensated Output Voltage Swing
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Apparatus and Method for Forming Die Sites in a High Density Electrical Interconnecting Structure
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Method and Apparatus for Non-Contact Opens/Shorts Testing of Electrical Circuits
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Test Cell for Non-Contact Opens/Shorts Testing of Electrical Circuits
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Method of Manufacturing Thick-Film Devices
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Cathode Ray Tube Deflection Circuit with Solid State Switch
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Numeric Encoding Method and Apparatus for Neural Networks
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Method and Apparatus for Managing Multiple Lock Indicators in a Multiprocessor Computer System
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Method for Utilizing an Encrypted Key as a Key Identifier in a Data Packet in a Computer Network
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Reactant Exhaust System for a Thermal Processing Furnace
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Inert Gas Curtain for a Thermal Processing Furnace
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Low-Voltage Cmos Output Buffer
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Surface Interference Detector
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Integrating the Logical and Physical Design of Electronically Linked Objects
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Double-Sided Hybrid High Density Circuit Board and Method of Making Same
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High Speed Parallel Multiplier Circuit
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Method and Apparatus for Enhancing the Enable Response of a Laser Diode Used in an Optical Communication System
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Rule Inference and Localization During Synthesis of Logic Circuit Designs
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Method of Minimizing Sum-of-Product Cases in a Heterogeneous Data Base Environment for Circuit Synthesis
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Method and Apparatus for Duplex Printing
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Method and Apparatus for Controlling the Bias Current of a Laser Diode
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A Parameter and Rule Creation and Modification Mechanism for Use by a Procedure for Synthesis of Logic Circuit Designs
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Object Container Transfer System and Method in an Object Based Computer Operating System
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Virtual Memory Page Table Paging Apparatus and Method
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Virtual Memory Paging Apparatus with Variable Size in-Page Clusters
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Waitable Object Creation System and Method in an Object Based Computer Operating System
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Method of Packaging and Powering Integrated Circuit Chips and the Chip Assembly Formed Thereby
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Bidirectional Transceiver for High Speed Data System
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Floating Point Arithmetic System and Method
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Temporary Object Handling System and Method in an Object Based Computer Operating System
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Conditional Object Creating System Having Different Object Pointers for Accessing a Set of Data Structure Objects
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Data Integrity Features for a Sort Accelerator
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Sort Accelerator with Rebound Sorter Repeatedly Morging Sorted Strings
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Digital Data Management System for Maintaininmg Consistency of Data in a Shadow Set
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Stable Sorting for a Sort Accelerator
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Latch Circuit and Method Wth Complementary Clocking and Level Sensitive Scan Capability
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Incremental-Scanning Compiler for Source-Code Development System
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Re-Execution of Edit-Compile-Link -Run Cycles for Changed Lines of Source Code with Storage of Associated Data in Buffers
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Incremental Compiler for Source-Code Development System
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Incremental Linking in Source-Code Development System
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Line-Skip Compiler for Source-Code Development System
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Emi/Rfi Shielding Method and Apparatus
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Method and Means for Displaying Smooth-Shaded Objects
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A Fault Tolerant, Synchronized Twin Computer System with Error Checking of I/O Communication
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Selection Between Alternate Control Word and Current Instruction Generated Control Word for Alu in Response to Alu Output and Current Instruction
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Process for Read/Write Transfers Includes Transmitting an Address to Configure Switching Logic Then Retransmitting the Address for Accessing a Resource
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Method of Handling Errors in Software
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Method of Converting Unique Data to System Data
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Extensible Entity Management System Including a Dispatching Kernel and Modules Which Independently Interpret and Execute Commands
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Bus Transmitter Having Controlled Trapezoidal Slew Rate
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Method of Inhibiting Electrochemical Reduction of Polyimide During Electroplating and Articles Formed Thereby
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Diffusion Barrier for Solvents and Inorganic Cations on Polyimide Surfaces by Ammonia Treatment
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Computer Workstation Including Video Update Arrangement
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Electro-Emissive Laser Stimulated Test
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Identifying Likely Failure Points in a Digital Data Processing System
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Subroutine Return Prediction Mechanism Using Ring Buffer and Comparing Predicated Address with Actual Address to Validate or Flush the Pipeline
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Composite Graphite Heat Pipe Apparatus and Method
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Evaporator Having Etched Fiber Nucleation Sites and Method of Fabricating Same
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Push-Pull Cascode Logic
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Local Area Printer Server for Requesting and Storing Required Resource Data and Forwarding Printer Status Message to Selected Destination
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Direct Manipulation Interface for Boolean Information Retrieval
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Instruction Storage Method with a Compressed Format Using a Mask Word
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Method of Operating a Computer Graphics System Including Asynchronously Traversing Its Nodes
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Lookahead Bus Arbitration System with Override of Condional Access Grants by Bus Cycle Extensions for Multicycle Data Transfer
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Fast Determination of Subtype Relationship in a Single Inheritance Type Hierarchy
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Reticular Discrimination Network for Specifying Real-Time Conditions
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Transmitting High-Bandwidth Signals on Coaxial Cable
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Bus Control Circuit for Latching and Maintaining Data Independently of Timing Event on the Bus Until New Data Is Driven Onto
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Planar Connector System with Zero Insertion Force and Distributed Clamping
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Improved Buffer for Gathering Write Requests and Resolving Read Conflicts by Matching Read and Write Requests
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Method and Apparatus for Circuit Simulation Using Parallel Processors Including Memory Arrangements and Matrix Decomposition Synchronization
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Process and System for Making Computer-Aided Drawings Using a Contour Inclusion Tree Associated Planar Map Data Structure
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High Performance Bit-Sliced Multiplier Circuit
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Precision Resistor in Self-Aligned Silicided Mos Process
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Lattice Scheduler Method for Reducing the Impact of Covert-Channel Countermeasures
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Token Ring Network Having Token Request Mechanism
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Finding Faults in Circuit Boards
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Configurable Set Associative Cache with Decoded Data Element Enable Lines
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System and Method for Consistent Timestamping in Distributed Computer Databases
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System for Flushing Instruction-Cache Only When Instruction-Cache Address and Data-Cache Address Are Matched and the Execution of a Return-from-Exception-or-Interrupt Command
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Semiconductor Package Having Wraparound Metallization
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Digital Processor with Bit Mask for Counting Registers for Fast Register Saves
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Computer Network Operating with Multilevel Hierarchical Security with Selectable Common Trust Realms and Corresponding Security Protocols
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Method and Apparatus for Mounting a Cathode Ray Tube to Minimize Tube Shift with Respect to a Bezel
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Circuit Chip Package Employing Low Melting Point Solder for Heat Transfer
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Rule Invocation Mechanism for Inductive Learning Engine
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Method of Dynamically Allocating Processors in a Massively Parallel Processing System
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High Speed Optoisolator Switching Apparatus
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Air Cooled Heat Exchanger for Multi-Chip Assemblies
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Next Line Prediction Apparatus for a Pipelined Computer System
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Register Mapping System Having a Log Containing Sequential Listing of Registers That Were Changed in Preceding Cycles for Precise Post- Branch Recovery
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An Apparatus and Method for an Improved Content Addressable Memory
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Frequency Independent Encoding Technique and Apparatus for Digital Communications
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Configurable Data Path Arrangement for Resolving Data Type Incom- Patibility
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Method and Apparatus for Sharring Data Between Processors in a Computer System
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Integrated Circuit Test Fixture and Method
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A Method and Apparatus for Efficiently Implementing Read-Type Procedural Attachments in a Rete-Like Pattern Matching Environment
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High-Power, High-Performance Integrated Circuit Chip Package
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Method and Apparatus for Exchanging Blocks of Information Between a Cache Memory and a Main Memory
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Probabilistic Cryptographic Processing Method
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Generic Encryption Technique for Communication Networks
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Frame Status Encoding for Communication Networks
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Pipelined Cryptography Processor and Method for Its Use in Communication Networks
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Arbitration Apparatus for Shared Bus
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Shared Bus Arbitration Apparatus Having a Deaf Node
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Error Transition Mode for Multi-Processor System
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Ensuring Data Integrity by Locked-Load and Conditional-Store Operations in a Multiprocessor System
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Prefetch Instruction for Improving Performance in Reduced Instruction Set Processor
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Method and Apparatus for Performing Diagnosis Scanning of a Memory Unit Regardless of the State of the System Clock and Without Affecting the Store Data
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Single Load, Multiple Issue Queue with Error Recovery Capability
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Crossbar Interface for Data Communication Network
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Method and Apparatus for Determining the Total Harmonic Distortion and Power Factor of a Non-Linear Load Circuit
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Method of Cooling and Powering an Integrated Circuit Chip Using a Complaint Interposing Pad
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Providing a Data Processor with a User -Mode Accessible Mode of Operation in Which the Processor Performs Processing Operations Without Interruption
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Name Pronunciation by Snythesizer
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System for Processor Pipeline Control with Selective Signal Deassertion for Handling Plurality of Exceptions Simultaneously Withou Without Priority Arbitration
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Method of Displaying Descriptive Data Representing a Candidate as a Plurality of Lines on an Output Device
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Language for Economically Building Complex, Large-Scale Efficient, Rule -Based Systems and Sub-Systems
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Method and Apparatus for Transferring Information Over a Common Parallel Bus Using a Fixed Sequence of Bus Phase Transitions
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Conical Gas Inlet for Thermal Processing Furnace
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Communications Arranagement for Digital Data Processing System Employing Heterogeneous Multiple Processing Nodes
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Normalization of Vectors Associated with Display Pixels of Computer Generated Images
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Single-Keyed Indexed File for Tp Queue Repository
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Vehicular Display System
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Apparatus and Method for Distributed Dynamic Priority Arbitration for Access to a Shared Resource
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Method and Apparatus for Organizing and Analyzing Timing Information
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Apparatus and Method for Single Operand Register Array for Vector and Scalar Data Processing Operations
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Product Defect Detection Using Thermal Ratio Analysis
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Mode Switching for a Memory System with Diagnostic Scan
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Method for Controlling the Variable Baud Rate of Peripheral Devices
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Compound Principals in Access Control Lists
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A Method for Performing Group Exclusion in Hierarchical Group Structures
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A Method for Delegating Authorization from One Entity to Another Through the Use of Session Encryption Keys
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Device and Method for Distributing Information in a Computer System
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Apparatus for Suppressing an Error Report from an Address for Which an Error Has Already Been Reported
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Two-Level Protocol for Multi-Component Bus Ownership, and Implementation in a Multi-Processor Cache Write Back Protocol
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Write-Back Cache with Ecc Protection
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System and Method for Producing Discrimination Nets for Expert Systems
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Integrated Power Conversion
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System for Distributed Computation Processing Including Dynamic Assignment of Predicates to Define Interdependencies
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Radix-16 Divider Using Overlapped Quotient Bit Selection and Concurrent Quotient Rounding and Correction
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Cmos Shift Register with Complementary Refresh Pass Gates and Buffer
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Multiple-Disk Storage System
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Modular Blackboard Based Expert System
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Cache with at Least Two Fill Rates
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Data Storage System Including Redundant Storage Devices
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Fault Tolerant Bus
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Automatic Sizing Memory System with Multiplexed Configuation Signals at Memory Modules
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Method and Apparatus for Providing High Performance Interconnection Between Interface Circuits Coupled to Information Buses
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Compact, High-Density Packaging Apparatus for High Performance Semiconductor Devices
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Method and Apparatus for a Backup Power Controller for Volatile Random Access MEM0RY
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Die Attach Structure and Method
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Sprite Cursor with Edge Extension and Clipping
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Electrical Circuit Interconnection
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Method and Apparatus for Handling Faults of Vector Instructions Causing Memory Management Exceptions
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Reduced Broadcast Algorithm for Address Resolution Protocol
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Single-Probe Charge Measurement Testing Method
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Package for Emi, Esd, Thermal, and Mechanical Shock Protection of Circuit Chips
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Apparatus for Recording and/or Reading Information
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Apparatus for Recording and/or Reading Information
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Augmented Doubly-Linked List Search and Management Method for a System Having Data Stored in a List of Data Elements in Memory
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Text Searching System
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Apparatus for Recording and/or Reading Information
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Reducing the Effect Processor Blocking
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N-Channel Clamp for Esd Protection in Self-Aligned Silicided Cmos Process
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Electronically Variable Delay Line
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System and Method for Jacketing Cross-Domain Calls in a Multi-Code Execution and Debugging System Within a Multi-Architecture Environment
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System for Linking Program Units by Binding Symbol Vector Index in the Symbol Table into Calling Image to Obtain Current Value of the Target Image
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System and Method for Preserving Instruction Granularity When Translating Program Code from a Computer Having a First Architecture to a Computer Having a Second Reduced Architecture During the Occurrence of Interrupts Due to Asynchronous Events
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Branch Resolution via Backward Symbolic Execution
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Tracking Condition Codes in Translating Code for Different Machine Architectures
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Use of Stack Depth to Identify Architecture and Calling Standard Dependencies in Machine Code
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Register Usage Tracking in Translating Code for Different Machine Architectures by Forward and Reverse Tracing Through the Program Flow Graph
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Mapping Assembly Language Argument List References in Translating Code for Different Machine Architectures
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Successive Translation, Execution and Interpretation of Computer Program Having Code at Unknown Locations Due to Execution Transfer Instructions Having Computed Destination Addresses
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Use of Stack Depth to Identify Machine Code Mistakes
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Identifying Pausible Variable Length Machine Code by Selecting Add- Dresses in Numerical Sequence,Decoding Code Strings,and Following Exe- Cution Transfer Paths
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Analysis of Computer Programs for Locating Translatable Code by Resolving Callbacks and Other Conflicting Mutual Dependencies
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Computer Systems and Method for Executing Command Scripts Using Multiple Synchronized Threads
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Structure for Controlling Impedance and Cross-Talk in a Printed Circuit Substrate
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Rete Network with Provisional Satisfaction of Node Conditions
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Memory Management Method for Coupled Memory Multiprocessor Systems
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A Coupled Memory Multiprocessor Computer System Including Cache Coherency Management Protocols
Patent: 5,303,362 →
Application: 07/673,766 →
Adaptive Memory Management Method for Coupled Memory Multiprocessor Systems
Patent: 5,269,013 →
Application: 07/674,077 →
Method and Apparatus for Testing Electrical Connectors
Patent: 5,177,555 →
Application: 07/676,794 →
Computer Apparatus and Method for Finite Element Identification in Interactive Modeling
Patent: 5,289,567 →
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System for Automatically and Transparently Mapping Rules and Objects from a Stable Storage Database Management System Within a Forward Chaining or Backward Chaining Inference Cycle
Patent: 5,136,523 →
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Computer Peripheral Device Network with Peripheral Address Resetting Capabilities
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Application: 07/680,313 →
Procedure for Incorporating Timing Parameters in the Synthesis of Logic Circuit Designs
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Application: 07/680,624 →
Memory Configuration System
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Shielded Printed Circuit Board Housing for High Density Storage
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Integral Heatsink Semiconductor Package
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Self Aligning Vacuum Nozzle
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Master Ecl Bias Voltage Regulator
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Expert System for Identifying Likely Failure Points in a Digital Data Processing System
Patent: 5,469,463 →
Application: 07/700,112 →
System for Reporting Errors of a Translated Program and Using a Boundry Instruction Bitmap to Determine the Corresponding Instruction Address in a Source Program
Patent: 5,432,795 →
Application: 07/700,770 →
System for Managing Hierarchical Information in a Digital Data Processing System
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Rule Structure in a Procedure for Synthesis of Logic Circuits
Patent: 5,175,696 →
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Rule Structure for Insertion of New Elements in a Circuit Design Synthesis Procedure
Patent: 5,452,226 →
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Apparatus and Method for Control of Asynchronous Program Interrupt Events in a Data Processing System
Patent: 5,148,544 →
Application: 07/704,710 →
Method for Providing a Thermal Transfer Device for the Removal of Heat from Packaged Elements
Patent: 5,083,373 →
Application: 07/704,898 →
Instruction Storage and Cache Miss Recovery in a High Speed Multiprocessing Parallel Processing Apparatus
Patent: 5,179,680 →
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Modulation Circuit for Grayscale Laser Printing
Patent: 5,170,403 →
Application: 07/708,163 →
Antialiasing Apparatus and Method for Computer Printers
Patent: 5,185,852 →
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System for Allocating Storage Spaces Based Upon Required and Optional Service Attributes Having Assigned Priorities
Patent: 5,287,500 →
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A System Monitoring Method and Device Including a Graphical User Interface to View and Manipulate System Information
Patent: 5,375,199 →
Application: 07/710,135 →
Micro-Beam Tactile Sensor for the Measurement of Vertical Position Displacement, and Method of Fabricating the Same
Patent: 5,138,216 →
Application: 07/713,280 →
Mode Scrambler as an Optical Isolator for Higher-Coherence Lasers in Multi-Mode Fiber Plants
Patent: 5,138,675 →
Application: 07/713,900 →
Hand Brake Mechanism for a Central Processing Unit Cabinet
Patent: 5,183,321 →
Application: 07/718,497 →
Flexible Circuit Connector
Patent: 5,133,667 →
Application: 07/718,498 →
Triaxially-Equalized Action Shock Mount
Patent: 5,156,371 →
Application: 07/718,502 →
Magnetic Head Testing Apparatus for Detecting Occurrences of Popcorn Noise Amid Externally Generated Noise
Patent: 5,134,366 →
Application: 07/719,042 →
Photo-Definable Template for Semiconductor Chip Alignment
Patent: 5,413,964 →
Application: 07/720,262 →
Concurrency and Recovery for Index Trees with Nodal Updates Using Multiple Atomic Actions by Which the Tree's Integrity Is Preserved During Undesired System Interruptions
Patent: 5,276,872 →
Application: 07/720,405 →
Computer System and Method for Displaying Images with Superimposed Partially Transparent Menus
Patent: 5,283,560 →
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Method and Apparatus for Forming Coplanar Contact Projections on Flexible Circuits
Patent: 5,161,403 →
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Management Issue Recognition and Resolution Knowledge Processor
Patent: 5,241,621 →
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Intermittent Component Failure Manager and Method for Minimizing Disruption of Distributed Computer System
Patent: 5,260,945 →
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Uniform Spatial Action Shock Mount
Patent: 5,217,198 →
Application: 07/721,745 →
Computer System Operation with Corrected Read Data Function
Patent: 5,263,032 →
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System and Method for Efficiently Indexing and Storing a Large Database with High Data Insertion Frequency
Patent: 5,204,958 →
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System of Device Independent File Directories Using a Tag Between the Directories and File Descriptors That Migrate with the Files
Patent: 5,333,315 →
Application: 07/722,008 →
Real-Time Recognition of Pointing Information from Video
Patent: 5,168,531 →
Application: 07/722,082 →
System and Method with a Procedure Oriented Input/Output Mechanism
Patent: 5,237,662 →
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Thermode Struture Having an Elongated Thermal Stable Blade
Patent: 5,229,575 →
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Gentle Package Extraction Tool and Method
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Integrated Circuit Protection by Liquid Encapsulation
Patent: 5,130,889 →
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Workflow Management and Control System
Patent: 5,301,320 →
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System for Reconstructing Prior Versions of Indexes Using Records Indicating Changes Between Successive Versions of the Indexes
Patent: 5,347,653 →
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Mounting Silicon Chips
Patent: 5,206,713 →
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System for Constructing and Loading a Table Data Structure Based on an Associated Configuration Data Structure
Patent: 5,446,575 →
Application: 07/722,750 →
System for Constructing a Table Data Sturcture Based on an Associated Configuration Data Structure and Loading It with Checmial Sample Physical Data
Patent: 5,434,971 →
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Method and Apparatus for Testing Inner Lead Bonds
Patent: 5,214,963 →
Application: 07/722,845 →
High Throughput Interlevel Dielectric Gap Filling Process
Patent: 5,279,865 →
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Translation Buffer for Virtual Machines with Address Space Match
Patent: 5,319,760 →
Application: 07/722,869 →
Computer Cable Management System
Patent: 5,286,919 →
Application: 07/722,870 →
Micro-Channel Wafer Cooling Chuck
Patent: 5,115,858 →
Application: 07/722,891 →
Electronic Component Cleaning Apparatus
Patent: 5,224,235 →
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Fixture and Method for Attaching Components
Patent: 5,240,549 →
Application: 07/722,972 →
Method and Apparatus for Efficient Morphological Text Analysis Using a High-Level Language for Compact Specification of Inflectional Paradigms
Patent: 5,559,693 →
Application: 07/723,145 →
Method and Apparatus for a Pcb and I/O Integrated Electromagnetic Containment
Patent: 5,165,055 →
Application: 07/723,151 →
Semiconductor Probe and Alignment System
Patent: 5,239,260 →
Application: 07/723,168 →
Structure and Method for Direct Calibration of Registration Measurement Systems to Actual Semiconductor Wafer Process Topography
Patent: 5,280,437 →
Application: 07/723,170 →
Atmospheric Pressure Gaseous-Flux-Assisted Laser Reflow Soldering
Patent: 5,227,604 →
Application: 07/723,203 →
Planarization Process for Trench Isolation in Integrated Circuit Manufacture
Patent: 5,175,122 →
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Computer System Console
Patent: 5,276,863 →
Application: 07/723,228 →
Method and Apparatus for Integrating a Dynamic Lexicon into a Full- Text Information Retrieval System
Patent: 5,251,316 →
Application: 07/723,229 →
Method and Apparatus for Coupling Light Between an Optoelectronic Device and a Waveguide
Patent: 5,168,537 →
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Apparatus for Connecting and Shielding Enclosures Housing Electronic Equipment
Patent: 5,164,543 →
Application: 07/723,395 →
Frame Assembly for Rack-Mountable Equipment
Patent: 5,372,262 →
Application: 07/723,396 →
Programmable Stall Cycles
Patent: 5,280,608 →
Application: 07/724,379 →
Method and Apparatus for Learning in a Neural Network
Patent: 5,226,092 →
Application: 07/724,381 →
Five-Volt Tolerant Differential Receiver
Patent: 5,172,016 →
Application: 07/724,407 →
Ic Package Hold-Down Fixture
Patent: 5,175,410 →
Application: 07/724,412 →
Integrated Circuit Device Carrier
Patent: 5,163,551 →
Application: 07/724,413 →
High-Speed Pseudo-Random Number Generator and Method for Generating Same
Patent: 5,187,676 →
Application: 07/724,531 →
Method for Fast Rule Execution of Expert Systems
Patent: 5,263,127 →
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System and Method for Construction of Language Independent Print Format Statements Through Use of Data Structures for Arbitrary Ordering of Print Parameters
Patent: 5,339,240 →
Application: 07/724,573 →
Scheme for Insuring Data Consistency Between a Plurality of Cache Memories and the Main Memory in a Multi-Processor System
Patent: 5,222,224 →
Application: 07/727,296 →
Multilevel Transaction Recovery in a Database System Which Loss Parent Transaction Undo Operation Upon Commit of Child Transaction
Patent: 5,287,501 →
Application: 07/728,661 →
Method and Apparatus for Efficient Morphological Text Analysis Using a High-Level Language for Compact Specification of Inflectional Paradigms
Patent: 5,475,587 →
Application: 07/729,445 →
Fault Diagnostic System
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Interface Between Processor and Special Instruction Processor in Digital Data Processing System
Patent: 5,226,170 →
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Expert System Including Arrangement for Acquiring Redesign Knowledge
Patent: 5,208,768 →
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Method and Apparatus for Synchronizing Signals
Patent: 5,164,677 →
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Method and Apparatus for Suspending and Restarting a Bus Cycle
Patent: 5,150,467 →
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Blocking Message Transmission or Signaling Error in Response to Message Addresses in a Computer Interconnect Coupler for Clusters of Data Processing Devices
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System for Translation of Virtual to Physical Addresses by Opearting Memory Management Processor for Calculating Location of Physical Address in Memory Concurrently with Cache Comparing Virtual Addresses for Translation
Patent: 5,349,651 →
Application: 07/746,007 →
Routing Apparatus and Method for High-Speed Mesh Connected Local Area Network
Patent: 5,179,558 →
Application: 07/746,796 →
Graphics Command Processing Method in a Computer Graphics System
Patent: 5,315,696 →
Application: 07/748,352 →
Address Method for Computer Graphics System
Patent: 5,321,810 →
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Method and Apparatus for Varying Command Length in a Computer Graphics System
Patent: 5,315,698 →
Application: 07/748,354 →
Translation of Virtual Addresses in a Computer Graphics System
Patent: 5,313,577 →
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Method and Apparatus for Transmitting Graphics Command in a Computer Graphics System
Patent: 5,321,806 →
Application: 07/748,360 →
Method and Apparatus for Reducing Electromagnetic Interference and Emission Associated with Computer Network Interfaces
Patent: 5,223,806 →
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Method and Apparatus for Shared Use of a Multiplexed Address/Data Signal Bus by Multiple Bus Masters
Patent: 5,191,656 →
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Predictive Cache System
Patent: 5,305,389 →
Application: 07/753,096 →
Compiler Allocating a Register to a Data Item Used Between a Use and Store of Another Data Item Previously Allocated to the Register
Patent: 5,339,428 →
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High Current, Low Voltage Drop, Separable Connector
Patent: 5,224,884 →
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Update Synchronizer
Patent: 5,294,842 →
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Method and Apparatus for Complete Functional Testing of a Complex Signal Path of a Semiconductor Chip
Patent: 5,198,758 →
Application: 07/764,314 →
Method and Apparatus for Clock Skew Reduction Through Absolute Delay Regulation
Patent: 5,272,390 →
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Multiple Record Group Rebound Sorter
Patent: 5,185,886 →
Application: 07/765,464 →
Gasket for Sealing a Flat Cable
Patent: 5,194,696 →
Application: 07/766,941 →
High Density Memory Array Packaging
Patent: 5,191,404 →
Application: 07/767,571 →
Automatic Program Code Generation in a Compiler System for an Instantiation of a Generic Program Structure and Based on Formal Parameters and Characteristics of Actual Parameters
Patent: 5,280,617 →
Application: 07/770,768 →
Distributed Interlock Apparatus and Distributed Interlock Management Method
Patent: 5,129,089 →
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Method for Providing a Lubricant Coating on the Surface of a Magneto- Optical Disk and Resulting Optical Disk
Patent: 5,112,662 →
Application: 07/772,476 →
Pocket-Sized Computer Access Security Device
Patent: 5,177,789 →
Application: 07/774,705 →
Dual-Path Computer Interconnect System with Four-Ported Packet Memory Control
Patent: 5,193,149 →
Application: 07/774,725 →
Correcting Crossover Distortion Produced When Analog Signal Thresholds Are Used to Remove Noise from Signal
Patent: 5,287,534 →
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Expert System for Assisting in the Design of a Complex System
Patent: 5,218,557 →
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System and Method for Analyzing Complex Sequences in Trace Arrays Using Multiple Finite Automata
Patent: 5,299,206 →
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Access Control Subsystem and Method for Distributed Computer System Using Compound Principals
Patent: 5,173,939 →
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Substrate to Heatsink Interface Apparatus and Method
Patent: 5,146,981 →
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Attribute Inductive Data Analysis
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Fast Tag Compare and Bank Select in Set Associative Cache
Patent: 5,353,424 →
Application: 07/794,865 →
Closed-Cycle Expansion-Valve Impingement Cooling System
Patent: 5,183,104 →
Application: 07/798,821 →
Apparatus and Method for Servicing Interrupts Utilizing a Pended Bus
Patent: 5,146,597 →
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Component Reclamation Apparatus and Method
Patent: 5,148,969 →
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Computer Method and Apparatus for Converting Compressed Characters for Display in Full Size
Patent: 5,404,436 →
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Apparatus and Method for Specifying Windows with Priority Ordered Rectangles in a Computer Video Graphics System
Patent: 5,216,413 →
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Method for Analyzing the Flow of Data Through a Complex Information Exchange System
Patent: 5,487,131 →
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Generic Remote Boot for Networked Workstations by Creating Local Bootable Code Image
Patent: 5,452,454 →
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Virtual Address to Physical Address Translation Using Page Tables in Virtual Memory
Patent: 5,239,635 →
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Attribute Based Multiple Data Structures in Host for Network Received Traffic
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Multiprocessor Buffer System
Patent: 5,315,707 →
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Secure User Authentication from Personal Computer
Patent: 5,210,795 →
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Compiler Using Clean Lines Table with Entries Indicating Unchanged Text Lines for Incrementally Compiling Only Changed Source Text Lines
Patent: 5,325,531 →
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Image Rendering Clip Registers
Patent: 5,414,524 →
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System and Method for Reducing Timign Channels in Digital Data Processing Systems
Patent: 5,220,661 →
Application: 07/823,066 →
System and Method for Exclusive Two-Level Caching
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Thermal Processing Furnace with Improved Plug Flow
Patent: 5,248,253 →
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Reducing Gas Recirculation in Thermal Processing Furnace
Patent: 5,256,060 →
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System for Reducing the Emission of High Frequency Electromagnetic Waves from Computer Systems
Patent: 5,285,007 →
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Rpc Based Computer System Using Transparent Callback and Associated Method
Patent: 5,247,676 →
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Memory Selection /Deselection Circuitry Having a Wordline Discharge Circuit
Patent: 5,301,163 →
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Hybrid Cooling System for Electronic Components
Patent: 5,285,347 →
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Molded Video Display Screen Bezel
Patent: 5,565,934 →
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Bellows Heat Pipe Apparatus for Cooling Systems
Patent: 5,206,791 →
Application: 07/832,524 →
Two-Stage Cmos Latch with Single-Wire Clock
Patent: 5,155,382 →
Application: 07/832,742 →
Disk Carrier
Patent: 5,199,743 →
Application: 07/834,013 →
Planar Interconnect with Electrical Alignment Indicator
Patent: 5,192,214 →
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Apparatus for Cell Format Control in a Spread Sheet
Patent: 5,280,575 →
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High Speed Transfer of Instructions from a Master to a Slave Processor
Patent: 5,210,834 →
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Method of Forming Trench Isolated Regions with Sidewall Doping
Patent: 5,296,392 →
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Solder Pump Bushing Seal
Patent: 5,209,389 →
Application: 07/841,671 →
Laser-Activated Plasma Chamber for Non-Contact Testing
Patent: 5,202,623 →
Application: 07/842,043 →
Memory Apparatus for Multiple Processor Systems
Patent: 5,193,071 →
Application: 07/844,883 →
Apparatus and Method for Synchronization of Access to Main Memory Signal Groups in a Multiprocessor Data Processing System
Patent: 5,291,581 →
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Heat Dissipation Apparatus
Patent: 5,184,281 →
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Window Dependent Pixel Datatypes in a Computer Video Graphics System
Patent: 5,396,263 →
Application: 07/849,784 →
System for Achieving Atomic Non-Sequential Multi-Word Operations in Shared Memory
Patent: 5,428,761 →
Application: 07/849,887 →
Floating-Well Cmos Output Driver
Patent: 5,160,855 →
Application: 07/850,248 →
Method of Issuance and Revocation of Certificates of Authenticity Used in Public Key Networks and Other Systems
Patent: 5,261,002 →
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Targeted Resets in a Data Processor Including a Trace Memory to Store Transactions
Patent: 5,251,227 →
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Cross Regulator for a Multiple Output Power Supply
Patent: 5,220,271 →
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Clocking System for Asynchronous Operations
Patent: 5,319,678 →
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Method and Apparatus for Text Classification
Patent: 5,371,807 →
Application: 07/855,378 →
High Density Electrical Interconnection Device and Method Therefor
Patent: 5,278,727 →
Application: 07/859,288 →
High-Density Double-Sided Multi-String Memory Module with Resistor for Insertion Detection
Patent: 5,164,916 →
Application: 07/861,276 →
Sharing of Bus Access Among Multiple State Machines with Minimal Wait Time and Prioritization of Like Cycle Types
Patent: 5,265,212 →
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Arcuate Profiled Heatsink Apparatus and Method
Patent: 5,172,755 →
Application: 07/861,724 →
Data Bus Using Open Drain Drivers and Differential Receivers Together with Distributed Termination Impedances
Patent: 5,311,081 →
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Power Supply Interlock for a Distributed Power System
Patent: 5,229,926 →
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Emi Shielding Gasket
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Integrated Circuit Protection by Liquid Encapsulation
Patent: 5,243,756 →
Application: 07/862,192 →
Intelligent and Compact Bucketing Method for Region Queries in Two-Dimensional Space
Patent: 5,319,743 →
Application: 07/862,467 →
System for Performing Rule Partitioning in a Rete Network
Patent: 5,241,652 →
Application: 07/863,351 →
Combined Differential-Mode and Common-Mode Noise Filter
Patent: 5,243,308 →
Application: 07/863,578 →
Integrated Computer Assembly
Patent: 5,294,994 →
Application: 07/863,612 →
Electromagnetic Radiation Shield for a Video Amplifier
Patent: 5,192,893 →
Application: 07/863,615 →
Video Amplifier Assembly Mount
Patent: 5,227,582 →
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Locating Mobile Objects in a Distributed Computer System
Patent: 5,325,524 →
Application: 07/864,371 →
Sequential Multilayer Process for Using Fluorinated Hydrocarbons as a Dielectric
Patent: 5,387,495 →
Application: 07/864,375 →
Cross-Domain Call System in a Capability Based Digital Data Processing System
Patent: 5,210,874 →
Application: 07/865,699 →
System and Method for Retrieving Justifiably Relevant Cases from a Case Library
Patent: 5,224,206 →
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Queue Apparatus and Mechanics for a Communications Interface Architecture
Patent: 5,386,514 →
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System for Accessing Information in a Data Processing System
Patent: 5,386,524 →
Application: 07/869,668 →
Dynamic Arbitration for System Bus Control in Multiprocessor Data Processing System
Patent: 5,301,283 →
Application: 07/870,134 →
Self-Retaining Mounting Block
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Application: 07/870,438 →
Memory Bank Management and Arbitration in Multiprocessor Computer System
Patent: 5,412,788 →
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Dual Addressing Arrangement for a Communications Interface Architecture
Patent: 5,657,471 →
Application: 07/870,491 →
System and Method for Measuring Computer System Time Intervals
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Robotics Workstation
Patent: 5,268,837 →
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Parallel Diagnostic Mode for Testing Computer Memory
Patent: 5,216,672 →
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Error Detecting and Correcting Apparatus and Method with Transparent Test Mode
Patent: 5,357,529 →
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Identification Panel for Electronic Equipment Cabinet
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Application: 07/873,319 →
Server Impersonation of Client Processes in an Object Based Computer Operating System
Patent: 5,187,790 →
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Interconnect Arrangement for Electronic Components Disposed on a Circuit Board
Patent: 5,297,107 →
Application: 07/873,922 →
System for Radial Clock Distribution and Skew Regulation for Synchronous Clocking of Components of a Computing System
Patent: 5,428,764 →
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Processor Identification Mechanism for a Multiprocessor System
Patent: 5,388,224 →
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Method of Using Stream Buffer to Perform Operation Under Normal Operation Mode and Selectively Switching to Test Mode to Check Data Integrity During System Operation
Patent: 5,452,418 →
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System for Sequential Read of Memory Stream Buffer Detecting Page Mode Cycles Availability, Fetching Data into a Selected Fifo, and Sending Data Without Accessing Memory
Patent: 5,461,718 →
Application: 07/874,076 →
Stream Buffer Memory Having a Multiple-Entry Address History Buffer for Detecting Sequential Reads to Intiate Prefetching
Patent: 5,371,870 →
Application: 07/874,080 →
Aborting Synchronizer
Patent: 5,305,354 →
Application: 07/874,237 →
Multisignal Synchronizer with Shared Last Stage
Patent: 5,274,628 →
Application: 07/874,243 →
Self-Configuring Bus Termination Component
Patent: 5,309,569 →
Application: 07/874,288 →
Duplicate Tag Store for a Processor Having Primary and Backup Cache Memories in a Multiprocessor Computer System
Patent: 5,319,766 →
Application: 07/874,289 →
Scheme for Error Handling in a Computer System
Patent: 5,361,267 →
Application: 07/874,321 →
Self-Compensating Voltage Level Shifting Circuit
Patent: 5,287,517 →
Application: 07/874,322 →
Application Design Interface Enhancement
Patent: 5,557,729 →
Application: 07/874,750 →
Method and Apparatus for Protecting the Confidentiality of Passwords in a Distributed Data Processing System
Patent: 5,418,854 →
Application: 07/875,050 →
Transferring Data in a Digital Data Processing System
Patent: 5,247,618 →
Application: 07/882,765 →
Remote Bootstrapping a Node Over Communication Link by Initially Requesting Remote Storage Access Program Which Emulates Local Disk to Load Other Programs
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Method and Apparatus for Resource Arbitration
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Application: 07/887,176 →
Cooling Device That Creates Longitudinal Vortices
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Application: 07/887,447 →
Wet Micro-Channel Wafer Chuck and Cooling Method
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Application: 07/888,040 →
Voltage-Controlled Ring Oscillator Using Complementary Differential Buffers for Generating Multiple Phase Signals
Patent: 5,239,274 →
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Method of Mounting a Tape Automated Bonded Semiconductor in a Housing Using a Compressor
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Application: 07/890,984 →
Manually-Operated Continuity/Shorts Test Probe for Bare Interconnection Packages
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Application: 07/891,632 →
Quadrant-Based Binding of Pointer Device Buttons
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Application: 07/892,189 →
Inter-Application Interface System
Patent: 5,175,854 →
Application: 07/892,609 →
Video Teleconferencing for Networked Workstations
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Application: 07/893,074 →
Method of Making an Electrical Interconnect Device
Patent: 5,428,891 →
Application: 07/893,220 →
Power Converter with Controller for Switching Between Primary and Battery Power Sources
Patent: 5,289,046 →
Application: 07/896,250 →
Modular Housing for Batteries and Battery Charger
Patent: 5,366,827 →
Application: 07/896,251 →
Feedback Isolation Amplifier
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Application: 07/896,282 →
Configurable Inverter for 120 Vac or 240 Vac Output
Patent: 5,260,864 →
Application: 07/896,712 →
Fault Detector for a Plurality of Batteries in Battery Backup Systems
Patent: 5,254,930 →
Application: 07/896,713 →
Dry Contact Electroplating Apparatus
Patent: 5,227,041 →
Application: 07/898,038 →
Non-Contact Electrical Pathway
Patent: 5,179,279 →
Application: 07/898,228 →
Static Timing Verification
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Application: 07/898,920 →
Semiconductor Heat Removal Apparatus with Non-Uniform Conductance
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Application: 07/898,930 →
Post Fabrication Processing of Semiconductor Chips
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Semiconductor Chip Test Jig
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Network Packet Receiver with Buffer Logic for Reassembling Interleaved Data Packets
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Hybrid Lock Escalation and De-Escalation Protocols
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Method and Apparatus for Ordering Read and Write Operations Using Conflict Bits in a Write Queve
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Processor and Method for Preventing Access to a Locked Memory Block by Recording a Lock in a Content Addressable Memory with Outstanding Cache Fills
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Digital Computer System with Cache Controller Coordinating Both Vector and Scalar Operations
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Processing and Method for Delaying the Processing of Cache Coherency Transactions During Outstanding Cache Fills
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Methods of Forming a Local Interconnect and a High Resistor Polysilicon Load by Reacting Cobalt with Polysilicon
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Method and Apparatus for Testing Processor-Based Computer Modules
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Smart Recompilation of Performing Matchup/Difference After Code Generation
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Method and System for Decreasing Recovery Time for Failed Atomic Transactions by Keeping Copies of Altered Control Structures in Main Memory
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Durable Atomic Storage Update Manager
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Hint Generation in Smart Recompilation
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Method and Apparatus for Coordinating Access to and Modifying Multiple Element Data Objects in a Shared Memory
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Resistance Tester Utilizing Regulator Circuits
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Inrush Current Control Circuit
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Reduced-Voltage Nmos Output Driver
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Method and Apparatus for Drawing Lines in a Graphics System
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High-Speed, Low-Noise, Cmos Output Driver
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Distributed Transaction Processing Using Two-Phase Commit Protocol with Presumed-Commit Without Log Force
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Fifo Based Parity Generator
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Color Information Storage and Processing System
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Fault-Tolerant System and Method for Implementing a Distributed State Machine
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Management Interface for License Management System
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Ensuring Write Ordering Under Writeback Cache Error Conditions
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Video Data Scaling for Video Teleconferencing Workstations Communicating by Digital Data Network
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Audio/Video Storage and Retrieval for Multimedia Workstations by Interleaving Audio and Video Data in Data File
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Asynchronous Bus Interface for Generating Individual Handshake Signal for Each Data Transfer Based on Associated Propagation Delay Within a Transaction
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Access Control Subsystem and Method for Distributed Computer System Using Locally Cached Authentication Credentials
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Computer Network with Modified Host-to-Host Encryption Keys
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Sort and Merge System Using Tags Associated with the Current Records Being Sorted to Lookahead and Determine the Next Record to Be Sorted
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Long-Term Storage of Controller Performance
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Procedure State Descriptor System for Digital Data Processors
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Plenum for Air-Impingement Cooling of Electronic Components
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Transferring Data Between Storage Media While Maintaining Host Processor Access for I/O Operations
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Method Apparatus for Scheduling Tasks in Repeated Iterations in a Digital Data Processing System Having Multiple Processors
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Optimized Stripe Detection for Redundant Arrays of Disk Drives
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Data and Parity Prefetching for Redundant Arrays of Disk Drives
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Method for Merging Memory Blocks, Fetching Associated Disk Chunk, Merging Memory Blocks with the Disk Chunk, and Writing the Merged Data
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System and Method for Drawing Antialiased Polygons
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Register Conflict Scoreboard in Pipelined Computer Using Pipelined Reference Counts
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Method for Creating a Directory Tree in Main Memory Using an Index File in Secondary Memory
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Document Generation Using Information Engineering
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Microprocessor System for Selectively Accessing a Processor Internal Register When the Processor Has Control of the Bus and Partial Address Identifying the Register
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System for Predicting Memory Fault in Vector Processor by Sending Indication Signal to Scalar Processor to Continue a Next Vector Instruction Issuance
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Package for Multiple Removable Integrated Circuits
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High Bandwidth Multiple Computer Bus Apparatus
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Destination Control Logic for Arithmetic and Logic Unit for Digital Data Processor
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Thread Private Memory Storage of Multi-Thread Digital Data Processors Using Access Descriptors for Uniquely Identifying Copies of Data Created on an as-Needed Basis
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Methods for Treating Photoresists
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Multi-Index Multi-Way Set-Associative Cache
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Character Output Control Method and Apparatus for Terminal
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System for Bonding a Heatsink to a Semicondutor Chip Package
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System for Specifying Interactions Among Objects in a Digital Data Processing System
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Coplanar Heatsink and Electronics Assembly
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Apparatus for an Air Impingement Heat Sink Using Secondary Flow Generators
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Set Prediction Cache Memory System Using Bits of the Main Memory Address
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Synchronous/Asynchronous Partitioning of an Asynchronous Bus Interface
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Cryptographic Processing in a Communication Network, Using a Single Cryptographic Engine
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Imaging System with Multilevel Dithering Using Two Memories
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Void and Cluster Apparatus and Method for Generating Dither Templates
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Image Adjustment System for Translating Raw Input Levels to Adjusted Input Levels
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Imaging System with Two Level Dithering Using Comparator
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Imaging System with Multilevel Dithering Using Bit Shifter
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Object Transferring System and Method in an Object Based Computer Operating System
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Polling of I/O Device Status with Status Comparison Performed in the Polled I/O Device
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Switch Circuit for Setting and Signaling a Voltage Level
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Interference Suppression System
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Computer System Performance Evaluation System and Method
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Test Fixture for Electronic Components
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Fast Area-Efficient Multi-Bit Binary Adder with Low Fan-Out Signals
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Timing Verification Using Synchronizers and Timing Constraints
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Reduced Tolerance Interconnect System
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Automatic Writeback and Storage Limit in a High-Performance Frame Buffer and Cache Memory System
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Multi Instruction Register Mapper
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Arbiter with Programmable Dynamic Request Prioritization
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Method for Testing a Processor Module in a Computer System
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Method and System for Ensuring Interconnect Integrity in a Micro-Chip- Module
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Method of Handling Errors in Software
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Hollow Chip Package and Method of Manufacture
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Dynamic Assignment of Multicast Network Addresses
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Computer Network Providing Transparent Operation on a Compute Server and Associated Method
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Bitwise Implementation Mechanism for a Circuit Design Synthesis Procedure
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Automatic Signal Termination System for a Computer Bus
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Integrated Circuit Metal Film Interconnect Having Enhanced Resistance to Electromigration
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Trickle Charge Circuit for an Off-Line Switching Power Supply
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A Current Mode Switching Power Supply Overload Protection Circuit with False Fault Condition Screening
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Method for Providing Minimal Size Test Vector Sets
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Phase Delay Compensator Using Gator Signal Generated by a Synchronizer for Loading and Shifting of Bit Pattern to Produce Clock Phases Corresponding to Frequency Changes
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Method for Synchronization of Arithmetic Exceptions in Central Processing Units Having Pipelined Execution Units Simultaneously Executing Instructions
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Sequential Reference Management for Cache Memories
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Method and Apparatus for Parity Generation
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Expert System Including Arrangement for Acquiring Redesign Knowledge
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Method for Comparing Data Structures That Cross Address Space Boundaries
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Method and Apparatus for Allocating Server Access in a Distributed Computing Environment
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Subarray Architecture with Partial Address Translation
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Apparatus and Method for Data Induced Condition Signalling
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Method for Testing, Debugging, and Comparing Computer Programs Using Concurrent Simulation of Program Paths
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Expert System Having a Plurality of Security Inspectors for Detecting Security Flaws in a Computer System
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Torsion Bar Connector
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Data Processing System and Method with Prefetch Buffers
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System for Determining the Rights of Object Access for a Server Process by Combining Them with the Rights of the Client Process
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Adapter for Interconnecting Single-Ended and Differential Scsi Buses to Prevent `Busy' or `Wired-or' Glitches from Being Passed from One Bus to the Other
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Position Independent Code Location System
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Key-Range Locking with Index Trees
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Concurrency-Control Method and Apparatus in a Database Management System Utilizing Key-Valued Locking
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Virtual Memory Management for Source-Code Development System
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Leading One/Zero Bit Detector for Floating Point Operation
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A Method and Apparatus for Controlling a Rounding Operation in a Floating Point Multiplier Circuit
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Fair Arbitration Scheme for Arbitrating Between Multiple Nodes in a Computer System Seeking Control of a Common Bus
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Method and Apparatus for Authenticating a Client to a Server in Computer Systems Which Support Different Security Mechanisms
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Using Pre-Analysis and a 2-State Optimistic Model to Reduce Computation in Transistor Circuit Stimulation
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Data Processing System and Method for Controlling the Latter as Well as a Cpu Board
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Adaptive Fault Identification System
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Content Addressable Memory Having a Pair of Memory Cells Storing Don't Care States for Address Translation
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Three-Port Josephson Memory Cell for Superconducting Digital Computer
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All-Optical Network Architecture
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Data Integrity Features for a Sort Accelerator
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Nmethod for Multi-Domain and Multi-Dimensional Concurrent Simulation Using a Digital Computer
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Laser Bonding Highly Reflective Surfaces
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System for Checking the Acceptance of I/O Request to an Interface Using Software Visible Instruction Which Provides a Status Signal and Performs Operations in Response Thereto
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Topology Independent System for State Element Conversion
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Routing Objects on Action Paths in a Distributed Computing System
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Semiconductor Device with Reduced Time-Dependent Dielectric Failures
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Lossless Active Snubber for Half-Bridge Output Rectifiers
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Low-Loss Active Voltage-Clamp Circuit for Single-Ended Forward Pwm Converter
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System for Forming Serial M-Bit Information into Blocks Whose Location Correspond to Bitmap Locations
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Remote Monitoring of High-Risk Patients Using Artificial Intelligence
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Method and Apparatus for Controlling a Processor Bus Used by Multiple Processor Components During Writeback Cache Transactions
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Competitive Snoopy Caching for Large-Scale Multiprocessors
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Processor System with Writeback Cache Using Writeback and Non Writeback Transactions Stored in Separate Queues
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Clip-On Heat Sink
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Object Code Processing System for Forming an Excutable Image by Trans- Forming Lisp-Type Object Files into a Format Compatible for Storage by a Linker
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System and Method for Automatically Relocating and Configuring Firmware Stored in Subsystem Modules
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Digital Processing System Including Plural Memory Devices and Data Transfer Circuitry
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Data Base Access Mechanism for Rules Utilized by a Synthesis Procedure for Logic Circuit Design
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Card Cage System
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Distributed Mult-Version Commitment Ordering Protocols for Guaranteeing Serializability During Transaction Processing
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Method and Apparatus for Clock Skew Reduction Through Remote Delay Regulation
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System to Facilitate Efficient Utilization of Network Resources in a Computer Network
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Distributed Computation Recovery Management System and Method
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Journalling Optimization System and Method for Distributed Computations
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Oscillation Device for Plating System
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Conformal Heat Sink for Electronic Module
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Programmable Pixel and Scan-Line Offsets for a Hardware Cursor
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Method and Apparatus for Clock Skew Reduction Through Absolute Delay Regulation
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I/O Expansion Box
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Method and Apparatus for Liquid Spill Containment
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Integrated Circuit Chip Having Primary and Secondary Random Access Memories for a Hierarchical Cache
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Transaction Control
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Input Modification System for Multilevel Dithering
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Cache Coherency Protocol for Multi Processor Computer System
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Method and Apparatus for Processing Input/Output Commands in a Storage System Having a Command Queue
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Method and Apparatus for Synchronizing Upgrades in Distributed Network Data Processing Systems
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Process for Filling an Isolation Trench
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Mechanism for Broadcasting Data in a Massively Parallel Array Processing System
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Method and Apparatus for Employing a Cycle Bit to Indicate Completion of Parallel Executing Instructions
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Bipolar Transistor Memory Cell and Method
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Method and System for Sorting and Prioritizing Electronic Mail Messages
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Method of Controlling Gate Oxide Thickness in the Fabrication of Semiconductor Devices
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An Apparatus and Method for Speculatively Executing Instructions in a Computer System
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Propagation Speedup by Use of Complementary Resolver Outputs in a System Bus Receiver
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Mechanism for Enforcing the Correct Order of Instruction Execution
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A Method and Apparatus for Propagating Exception Conditions of a Computer System
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Bus Termination Resistance Linearity Circuit
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Naming Service Database Updating Technique
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Compensated Offset Voltage, Low Gain, High Bandwidth, Full Swing, Wide Common Mode Range, Cmos Differential Voltage Amplifier
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Bus Settle Time by Using Previous Bus State to Condition Bus at All Receiving Locations
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Integrated I/O Bus Circuit Protection for Multiple-Driven System Bus Signals
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Remote Procedure Callback System and Method
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Object Oriented Computer Architecture Using Directory Objects
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Chunky Binary Multiplier and Method of Operation
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A Memory Analysis System for Dynamically Displaying Memory Allocation and De-Allocation Events Associated with an Application Program
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Threshold Optimization for Soi Transistors Through Use of Negative Charge in the Gate Oxide
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Method and Apparatus for the on-Line Restoration of a Disk in a Raid- 4 or Raid-5 Array with Concurrent Access by Applications
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Method for on-Line Reorganization of the Data on a Raid-4 or Raid-5 Array in the Absence of One Disk and the on-Line Restoration of a Replacement Disk
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Process for Increasing Sacrificial Oxide Etch Rate to Reduce Field Oxide Loss
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Soi Transistor Threshold Optimization by Use of Gate Oxide Having Positive Charge
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Fault Tolerant Distributed Garbage Collection System and Method for Collecting Network Objects
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Run-Length Compression of Index Keys
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Fixture and Method for Attaching Components
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High Capacity Netlist Comparison
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Disk Cache Management Techniques Using Non-Volatile Storage
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Multiprocessor Cache Examiner and Coherency Checker
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Branch Prediction in High-Performance Processor
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Branch Prediction Unit for High-Performance Processor
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Method and System for Data Retrieval in a Distributed System Using Linked Location References on a Plurality of Nodes
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System for Controlling a Write Cache and Merging Adjacent Data Blocks for Write Operations
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Optical Force Sensor for High Density Planar Electrical Interconnects
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Secure Method of Neighbor Discovery Over a Multiaccess Medium
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Method of Forming Micro-Trench Isolation Regions in the Fabrication of Semiconductor Devices
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Message Encryption Using a Hash Function
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Signature Data Object
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Combined Differential-Mode Common-Mode Noise Filter
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Voltage-Tracking Circuit and Application in a Track-and-Hold Amplifier
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Determination of Interconnect Stress Test Current
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Peak Detector Circuit and Application in a Fiber Optic Receiver
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Segmented Video on Demand System
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Video on Demand with Memory Accessing and Vcr Like Functions
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Staged Cmos Output Buffer
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Language Scoping for Modular, Flexible, Concise, Configuration Descriptions
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Zero Impact Module Ejection System
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Method for Addressing Page Tables in Virtual Memory
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Voltage Level Converting Buffer Circuit
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Planarization Process for Ic Trench Isolation Using Oxidized Polysilicon Filler
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Debugging a Computer Program by Simulating Execution Forwards and Backwards in a Main History Log and Alternative History Logs
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Computer Simulation Technique for Predicting Program Performance
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Method of Decreasing the Field Oxide Etch Rate in Isolation Technology
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Method and Apparatus for Schematic Routing
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Method and Apparatus for Generating Tests for Structures Expressed as Extended Finite State Machines
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Power Line Transient Suppression Circuit Appliances
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Molded Bumper Rail for a Portable Computer
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Virtual to Physical Address Translation Scheme with Granularity Hint for Identifying Subsequent Pages to Be Accessed
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Cash Pocket for an Automatic Teller Machine
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Documents Having Executable Attributes for Active Mail and Digitized Speech to Text Conversion
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Memory Subsystem for Bitmap Printer Data Controller
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System and Method for Communication Between Windowing Environments
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Hot Carrier-Hard Gate Oxides by Nitrogen Implantation Before Gate Oxidation
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Equipment Cabinet Door Mountable on Either Side and Having a Central Latch
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Extensible Entity Management System Including Rule-Based Alarms
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Interlocking Pedestal Assembly for a Computer Enclosure
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Fault Tolerant Computer System with Shadow Virtual Processor
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Embedded Features for Registration Measurement in Electronics Manufacturing
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Field Effect Transistor with Integrated Schottky Diode Clamp
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Elastomeric Key Switch Actuator
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Protection Ring Extension for Computers Having Distinct Virtual Machine Monitor and Virtual Machine Address Spaces
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Interval Width Update Process in the Arithmetic Coding Method
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Optimizing Compiler Using Templates Corresponding to Portions of an Intermediate Language Graph to Determine an Order of Evaluation and to Allocate Lifetimes to Temporary Names for Variables
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Noise-Free Analog Islands in Digital Integrated Circuits
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Semiconductor Wafer Processing with Across-Wafer Critical Dimension Monitoring Using Optical Endpoint Detection
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Online Background Predictors and Prefetchers for Locality Management
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Method and Apparatus for Cache Miss Reduction by Simulating Cache Associativity
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Trainable Apparatus for Predicting Instruction Outcomes in Pipelined Processors
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Ring Based Distributed Communication Bus for a Multiprocessor Network
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Common-Mode Filtering Attachment for Power Line Connectors
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Method for Providing a Security Facility for a Network of Management Servers Utilizing a Database of Trust Relations to Verify Mutual Trust Relations Between Management Servers
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Power Sequencing Control
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Multiple Reasoning and Result Reconciliation for Enterprise Analysis
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Method and Apparatus for Producing Audio-Visual Synthetic Speech
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Memory Stream Buffer
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Distributed Configuration Profile for Computing System
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System and Method for Emulating a Window Management Environment Having a Uniform Windowing Interface
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System for Handling Cache Memory Victim Data Which Transfers Data from Cache to the Interface While Cpu Performs a Cache Lookup Using Cache Status Information
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Method and Apparatus for Updating a Duplicate Tag Status in a Snoop Bus Protocal Based Computer System
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Clock Architecture for Synchronous System Bus Which Regulates and Adjusts Clock Skew
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Low Skew Remote Absolute Delay Regulator Chip
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Paddleless Molded Plastic Semiconductor Chip Package
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Buffer Descriptor Prefetch in Network and I/O Design
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Operand Specifier Processing by Grouping Similiar Specifier Types Together and Providing a General Routine for Each
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Instruction Coding to Support Parallel Execution of Programs
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Method for Increasing the Performance of Lines Drawn into a Framebuffer Memory
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Static Random Access Memory Having Tunable Self-Timed Control Logic Circuits
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Software Mechanism for Accurately Handling Exceptions Generated by Instructions Scheduled Speculatively Due to Branch Elimination
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High Performance Fan Heatsink Assembly
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In-Register Data Manipulation for Unaligned Byte Write Using Data Shift in Reduced Instruction Set Processor
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Shift Register Divided into a Number of Cells and a Number of Stages Within Each Cell to Permit Bit and Multiple Bit Shifting
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Memory Reference Tagging
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System for Increasing the Difficulty of Password Guessing Attacks in a Distributed Authentication Scheme Employing Authentication Tokens
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License Document Interchange Format for License Management System
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Read-Write Buffer for Gathering Write Requests and Resolving Read Conflicts Based on a Generated Byte Mask Code
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Pattern Recognition Device
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Method and Apparatus for Protecting the Confidentiality of Passwords in a Distributed Data Processing System
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Pipelined Computer with Operand Context Queue to Simplify Context-Dependent Execution Flow
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Using Sorting to Do Matchup in Smart Recompilation
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Remote Display of an Image by Transmitting Compressed Video Frames Respresenting Back-Ground and Overlay Portions Thereof
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Method and Apparatus for Synchronizing Data Queues in Asymmetric Reflective Memories
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Method for Selectively Enabling Subset of Embedded Event-Making Instructions and Selecting Types and Items of Event-Based Data to Be Collected Per Enabled Instruction
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Delayed Acknowledgement in an Asymmetric Timer Based Lan Communications Protocol
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Method of Reducing the Complexity of an I/O Request to a Raid-4 or Raid-5 Array
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Generic Fault Management of a Computer System
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Low Delay Means of Communicating Between Systems on Different Clocks
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Method for Detection of Configuration Types and Addressing Modes of a Dynamic Ram
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Arbitration System Based on Requester Class and Relative Priority Including Transmit Descriptor Valid Bit for a Shared Resource Having Multiple Requesters
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Delay Compensated Signal Propagation
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Model Based Reasoning System for Network Fault Diagnosis
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Computer Memory Device Holding a Data Structure for Implementation of Function Objects
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Methods and Apparatus for Implementing Server Functions in a Distributed Heterogeneous Environment
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Method and Apparatus for Forming and Exchange Address for a System with Different Size Caches
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Memory Testing with Preservation of in-Use Data
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Update Vs. Invalidate Policy for Snoopy Bus Protocol
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Simulator System for Code Execution and Debugging Within a Multi-Architecture Environment
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Video Teleconferencing for Networked Workstations
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Low Dielectric Constant Microsphere Filled Layers for Multilayer Electrical Structures
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Method for Control of Random Test Vector Generation
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Method and Apparatus for Remotely Booting a Computer System
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Method and Apparatus for Testing Software on a Computer Network
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Guaranteeing Global Serializability by Applying Commitment Ordering Selectively to Global Transactions
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Commitment Ordering for Guaranteeing Serializability Across Distributed Transactions
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Apparatus for Caching Smram in an Intel Processor Based Computer System Employing System Management Mode
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Apparatus and Method for Accessing Smram in a Computer Based Upon a Processor Employing System Management Mode
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Rotating Battery Hinge for a Notebook Computer
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Heat Dissipating Arrangement in a Portable Computer
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Past-History Filtered Branch Prediction
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Method and Apparatus for Providing High-Speed Column Redundancy
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Apparatus and Method for Adapting a Computer System to Different Architectures
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Programmable Interrupt Signal Router
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Method and System for Certificate Based Alias Detection
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Apparatus and Method for Tracing Data Flows in High-Speed Computer Systems
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Method and Apparatus for Tracing Unpredictable Execution Flows in a Trace Buffer of a High-Speed Computer System
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Intelligent Snoopy Bus Arbiter
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Method and Device for Monitoring, Manipulating, and Viewing System Information
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Interface for Symbol Table Construction in a Multilanguage Optimizing Compiler
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System for Executing and Bebugging Multiple Codes in a Multi- Architecture Environment Using Jacketing Means for Jacketing the Cross-Domain Calls
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Tenon and Mortice Jig for a Router
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Method and Apparatus for Network Computer Systems Management Group Administration
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Multiplexed Gapped Constant Bit Rate Data Transmission
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Interconnect Structures Using Group Viii Metals
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Emi Shielding for Components
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Temporary State Preservation for a Distributed File Service Which Purges Virtual Circuit Control Information After Expiration of Time Limit of Inactivity
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High Speed Method for Maintaining Cache Coherency in a Multi-Level, Set Associative Cache Hierarchy
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Method for Improving the Processing and Storage Performance of Digital Signature Schemes
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Mis-Synchronization Detection System Using a Combined Error Correcting and Cycle Identifier Code
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Method and Apparatus for Preserving Data Integrity in a Multiple Disk Raid Organized Storage System
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Method and Apparatus for Simplified and Compact Component Addition to a Printed Circuit Board
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Phase-Space Surface Representation of Server Computer Performance in a Computer Network
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Method and Apparatus for Displaying Module Diagnostic Results
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Common Agent Computer Management System and Method
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Software Debugging System and Method Especially Adapted for Code Debugging Within a Multi-Architecture Environment
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Graphical User Interface for Video Teleconferencing
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System and Method for Controlling Execution of Nested Loops in Parallel in a Computer Including Multiple Processors, and Compiler for Generating Code Therefore
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Testing Tool for Diagnosing Defective Computer System Devices
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Analyzing Inductive Expressions in a Multilanguage Optimizing Compiler
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Multiple Block Line Prediction
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Testing and Debugging New Y Architecture Code on Existing X Architecture System by Using an Environment Manager to Switch Between Direct X Code Execution and Simulated Y Code Execution
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Using Hint Generation to Cause Portions of Object Files to Remain the Same
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Document Management System Using Multiple Threaded Processes and Having Asynchronous Repository Responses and No Busy Cursor
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Concurrency and Recovery for Index Trees with Nodal Updates Using Multiple Atomic Actions
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Multi-Processor Computer Systems Having Shared Memory and Private Cache Memories,and Invalidate Queues Having Valid Bits and Flush Bits for Serializing Transactions
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Durable Atomic Storage Update Manager
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Log for Selective Management of Specific Addresses in a Shadow Storage System
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Attribute Component Name Portion Based Document Retrieval System with System Query Language Interface
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High-Performance Multi-Processor Having Floating Point Unit
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Extensible Entity Management System Including an Information Manager for Obtaining, Storing and Retrieving Information from Entities
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Method and Apparatus for Conditioning Timed Program Independent of Transport Timing
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Programmable Memory Controller for Power and Noise Reduction
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Photo-Definable Template for Semiconductor Chip Alignment
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System for Selectively Browsing a Large, Distributed Directory Tree Using Authentication Links
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Dynamic Computer Performance Monitor
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Dynamic Microbranching with Programmable Hold on Condition, to Programmable Dynamic Microbranching Delay Minimization
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Method for Predictive Prefetching of Information Over a Communications Network
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Computer Network Providing Transparent Operation on a Compute Server and Associated Method
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An Apparatuss and Method for an Improved Content Addressable Memory Using a Random Access Memory to Generate Match Information
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Method and Apparatus for End-to-End Encryption of a Data Packet in a Computer Network
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Package for High Powered Die
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Configurable Digital Signal Interface Using Field Programmable Gate Array to Reformat Data
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Video Data Scaling for Video Teleconferencing Workstations Communicating by Digital Data Network
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Modular Coupler Arrangement for Use in a Building Wiring Distribution System
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Socket Including Centrally Distributed Test Tips for Testing Unpackaged Singulated Die
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Memory Resource Allocation Look Ahead System and Method
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Object Oriented Computer Architecture Using Directory Objects
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Method of Using Additives with Silica-Based Slurries to Enhance Selectivity in Metal Cmp
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N-[(4-Heteroaryl)-1-Piperidinyl)Alkyl] -1,2,3,4-Tetrahydroquinolines and Related Compounds and Their Therapeutic Utility
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Temporary State Preservation for a Distributed File Service
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Self-Aligned Cobalt Silicide on Mos Integrated Circuits
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Semiconductor Process, Power Supply and Temperature Compensated System Bus Integrated Interface Architecture with Precision Receiver
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Static Timing Verification in the Presence of Logically False Paths
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Method and Apparatus for Rendering of Fractional Pixel Lists for Anti- Aliasing and Transparency
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Neural Network Recognizer for Pdls
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Floating Point Unit Data Path Alignment
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Method and Apparatus of Improving Network Performance and Network Availability in a Client-Server Network by Transparently Replicating a Network Service
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Precision Broadcast of Composite Programs Including Secondary Program Content Such as Advertisements
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Method and Apparatus for Preventing the Use of Corrupt Data in a Multiple Disk Raid Organized Storage System
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Method and Apparatus for Conducting Computerized Commerce
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Method and Apparatus for Cryptographic Authentication
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Cache Memory System and Method for Selectively Removing Stale Aliased Entries
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Atomic Update of Edc Protected Data
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Generic Remote Boot for Networked Workstations by Creating Local Bootable Code Image
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Semiconductor Process Power Supply Voltage and Temperature Compensated Integrated System Bus Driver Rise and Fall Time
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Media Recovery with Time-Split B-Trees
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Stacked Skip List Data Structures
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Bidirectional Transreceiver for High Speed Data System
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Skip List Data Structure Enhancements
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Uninterruptible Power Supply with Fault Tolerance in a Hihg Voltage Environment
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Calibration and Merging Unit for Video Adapters
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Enhanced Raid Write Hole Protection and Recovery
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Reconstructing Data Blocks in a Raid Array Data Storage System Having Storage Device Metadata and Raid Set Metadata
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Promoting Device Level Error to Raidset Level Error to Restore Redundacy in a Raid Array Data Storage System
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Variable-Level Backup Scheduling Method and Apparatus
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Host Transparent Storage Controller Failover/Failback of Scsi Targets and Associated Units
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Software Mechanism for Accuratley Handling Exceptions Generated by Instructions Scheduled Speculatively Due to Branch Elimination
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Method for Performing Private Lock Management
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Code Point Update Device in the Arithmetic Coding Method
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A Sorting System for Serially Processing Records
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Emi Chassis Seam
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Implicit Tree-Mapping Technique
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Methodology for in Situ Etch Stop Detection and Control of Plasma Etching Process and Device Design to Minimize Process Chamber Contamination
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Register and Instruction Controller for Superscalar Processor
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State Machine Phase Lock Loop
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Dynamically Programmable Reduced Instruction Set Computer with Programmable Processor Loading Based on Program Number Field and Program Number Register Contents
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Hardware Extraction Technique for Programmable Reduced Instruction Set Computers
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Esd Protection Clamp for Mixed Voltage I/O Stages Using Nmos Transistors
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Semiconductor Device Fabrication with Planar Gate Interconnect Surface
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High-Efficiency Apparatus for Measuring Operational Parameters and Times of Vehicles Running Around a Racetrack
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Document Display System Using Documents Having Ephemeral Attributes for Sharing Information Regarding the Location of the Display of Each Document on Multiple Display Devices
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Method for Altering Memory Configuration and Sizing Memory Modules While Maintaining Software Code Stream Coherence
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Memory Stream Buffer with Variable-Size Prefetch Depending on Memory Interleaving Configuration
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Multi-Processor Resource Locking Mechanism with a Lock Register Corresponding to Each Resource Stored in Common Memory
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Multiple-Bit Error Correction in Computer Main Memory
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Transistor Fabrication Process in Which a Contact Metallization Is Formed with Different Silicide Thickness Over Gate Interconnect Material and Transistor Source/Drain Regions `
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Duplicate Cache Tag Store for Computer Graphics System
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Method Implemented by a Computer Network Adapter for Autonomously Adjusting a Transmit Commencement Threshold Value Upon Occurrence of an Underflow Condition
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Method and Apparatus for Hierarchical Relative Error Scheduling
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Continuous Motion Electrical Circuit Interconnect Test Method and Apparatus
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Method and Apparatus for Rate-Based Scheduling Using a Relative Error Approach
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Parallel Processing System for Virtual Processor Implementation of Machine-Language Instructions
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Document Display System Using a Scripting Language Having Container Variables Setting Document Attributes
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Translating, Executing, and Re-Translating a Computer Program for Finding and Translating Program Code at Unknown Program Addresses
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Display Apparatus for the Display of Documents in a Three-Dimensional Workspace
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Interactive Visualization Environment with Improved Visual Programming Interface
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Spline-Based Image Registration
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Method and Apparatus for Producing a Software Test System Using Complementary Code to Resolve External Dependencies
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Method for Performing Integrated Section-Level and Full-Chip Timing Verification for Custom Microprocessor Designs
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System for Downloading Computer Software Programs
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Temporary Storage Having Entries Smaller Than Memory Bus
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Distributed Data Bus Sequencing for a System Bus with Separate Address and Data Bus Protocols
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Reduced System Bus Receiver Setup Time by Latching Unamplified Bus Voltage
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Method and Apparatus for Viedo Compression and Decompression Using High Speed Discrete Cosine Transform
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Void and Cluster Apparatus and Mehtod for Generarting Dither Templates
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Method for Providing a Pipeline Interpreter for a Variable Length Instruction Set
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Clip-On Non-Snag Grounding Finger Array
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Means and Apparatus for Maintaining Condition Codes in an Unevaluated State
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Fast Translation and Execution of a Computer Program on a Non-Native Architecture by Use of Background Translator
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Method and Apparatus for Performing Binary Translation
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Method and Apparatus for Forming a Translation Unit
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Transparent and Secure Network Gateway
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Apparatus and Method for Interleaving Timed Program Data with Secondary Data
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Application User Interface
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Low Inductance Electrical Resistor Terminator Package
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Video Teleconferencing for Networked Workstations
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Dma Controller for Memory Scrubbing
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Memory System and Method for Selective Multi-Level Caching Using a Cache Level Code
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Hardware Instruction Scheduler for Short Execution Unit Latencies
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Testable Chip Carrier
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System for Generating Error Signal to Indicate Mismatch in Commands and Preventing Processing Data Associated with the Received Commands When Mismatch Command Has Been Determined
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Software Mechanism for Reducing Exceptions Generated by Speculatively Scheduled Instructions
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Alternate Execution and Interpretation of Computer Program Having Code at Unknown Locations Due to Transfer Instructions Having Computed Destination Addresses
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Crosspoint Switched Multimedia System
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Symmetrically Switched Multimedia System
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Probe Card Shipping and Handling System
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Page Mode and Nibble Mode Dram
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Past-History Filtered Branch Prediction
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Test Methodology for Exceeding Tester Pin Count for an Asic Device
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Two Part Closely Coupled Cross Polarized Emi Shield
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Method and Apparatus for Handling and Detecting an Invalid Use of a Data Structure
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Method and Apparatus for Interconnection of Multiple Modules
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Portable Computer with Integrated Alarm System
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Method for Providing Improved Graphics Performance Through Atypical Pixel Storage in Video Memory
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Variable Split Virtual Address Space Allocation with Multi-System Compatibility
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Virtual Memory System with Page Table Space Separating a Private Space and Shared Space in a Virtual Memory
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Virtual Memory Allocation in a Virtual Address Space Having an Inaccessible Gap
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System for Non-Current Page Table Structure Access
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Universal Pte Backlinks for Page Table Accesses
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Method and Apparatus for Providing 32-Bit Yuv to Rgb Color Conversion
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Compact Self-Aligned Body Contact Silicon-on-Insulator Transistor
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Color Adjustment Table System for Yuv to Rgb Color Conversion
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Architecture for System-Wide Standardized Intra-Module and Inter-Module Fault Testing
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Byte-Compare Operation for High-Performance Processor
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System and Method for Generation of One-Time Encryption Keys for Data Communications and a Computer Program Product for Implementing the Same
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Entity Management System
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Method of Data in a Computer System by Encoding Data Using a Data Dictionary
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Method and Apparatus for Performing Switched Supply Drive in Cmos Pad Drivers
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Method and Apparatus for Interleaving and De-Interleaving Yuv Pixel Data
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Mechanism for High Bandwidth Dma Transfers in a Pci Environmment
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Apparatus and Method for Serialized Set Prediction
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Method and Apparatus for Eliminating the Transpose Buffer During a Decomposed Forward or Inverse 2-Dimensional Discrete Cosine Transform Through Operand Decomposition Storage and Retrieval
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Method and Apparaus for Performing Fast Division
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Circuit Board Retainer
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Method and Apparatus for Performing Two Pass Quality Video Compression Through Pipelining and Buffer Management
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Computer Animation Method and Apparatus
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Post Processing Timing of Rhythm in Synthetic Speech
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Enabling Mirror, Nonmirror and Partial Mirror Cache Modes in a Dual Cache System
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Simultaneous, Mirror Write Cache
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Option Card Slot Filler Plate
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Low Profile Desk Top Computer
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Reusable Slotted Suspension Bulk Package
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Hinged Front Panel Assembly for Circuit Cards
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Rotating Battery Hinge for a Notebook Computer
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Validation Checking of Shared Memory Accesses
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Integrated Thermal Coupling for Heat Generating Device
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Interleaved-Fin Thermal Connector
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Translation Buffer and Method for Translating Addresses Utilizing Invalid and Don't Care States
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Fault Management Scheme for a Cache Memory
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Method and Apparatus for Testing Implementations of Software Specifications
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System for Assigning Boot Strap Processor in Symmetric Multiprocessor Computer with Watchdog Reassignment
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System for Controlling a Write Operation Involving Data Held in a Write Cache
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Method of Reducing the Number of Overhead Instructions by Modifying the Program to Locate Instructions That Access Shared Data Stored at Target Addresses Before Program Execution
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Database Generator
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Batched Checking of Shared Memory Accesses
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A Method for Sharing Variable-Grained Memory of Worksations by Sending Particular Block Including Line and Size of the Block to Exchange Shared Data Structures
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Lock-Up Free Data Sharing
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Method and Apparatus for Software Testing Using a Differential Testing Technique to to Test Compilers
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Apparatus to Minimize Integrated Circuit Heatsink E.M.I Radiation
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Grounding for Enclosures
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Method of Memory Interleaving, and Memory Systems Interleaved Thereby
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Video Data Scaling for Video Teleconferencing Workstations Communicating by Digital Data Network
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Scaled Memory Allocation System
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Self-Referencing Modulation Circuit for Cmos Integrated Circuit Electrostatic Discharge Protection Clamps
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Direct Memory Access (Dma) Data Transfer Requiring No Processor Dma Support
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Dynamic Component Trimming Method and Apparatus
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Destination Indexed Miss Status Holding Registers
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Symmetric Multi-Processing Control Arrangement
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Efficient Method and Apparatus for Compiling and Linking Modules of Computer Code in a Large Software System
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Method of Minimizing Area for Fanout Chains in High-Speed Networks
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Entity Management System with Remote Call Feature
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Computer Method and Apparatus for Clustering Documents and Automatic Generation of Cluster Keywords
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Adjustable Filter for Error Detecting and Correcting System
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Flexible Snmp Trap Mechanism
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Browser-Based Electronic Messaging
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Method and Apparatus for Cpu Failure Recovery in Symmetric Multi- Processing Systems
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Memory Bank Addressing Scheme
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Method and Apparatus for Performing Interrupt Frequency Mitigation in a Network Node
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Transmit Data Fifo for Flow Controlled Data
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Method and Apparatus for Performing Raw Cell Status Report Frequency Mitigation on Receive in a Network Node
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Image-Based Touchscreen
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Self-Aligned Cobalt Silicide on Mos Integrated Circuits
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T-Shaped Locking Member for Engaging a Passageway in a Heat Sink for Securement to a Mounting Board
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Method and Apparatus for Detecting and Executing Cross-Domain Calls in a Computer System
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Method and Apparatus for Graphical Panning
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Paddleless Molded Plastic Semiconductor Chip Package
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Method of Rule Execution in an Expert System Using Equivalence Classes to Group Database Objects
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Method and Apparatus for Performing Retroactive Backups in a Computer System
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Dynamic Fine-Granted Dependency Analysis for a Functional Language
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Pseudo Network Adapter for Frame Capture, Encapsulation and Encryption
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Item Selection by Prediction and Refinement
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Arbitration Unit Which Requests Control of the System Bus Prior to Determining Whether Such Control Is Required
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Skipping Clock Interrupts During System Inactivity to Reduce Power Consumption
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Performance Optimization and System Bus Duty Cycle Reduction by I/O Bridge Partial Cache Line Writes
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Automatic Disk Drive Shelf Address Assignment and Error Detection Method and Apparatus
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Method and Apparatus for Automatic Gap Closing in Computer Aided Drawing
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Method for Communicating Interrupt Data Sturcture in Multi-Processor Computer System
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Method and Apparatus Providing Dma Transfers Between Devices Coupled to Different Host Bus Bridges
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Anti-Slamming Latch Apparatus for Modular Component Installations
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Automatic Mapping, Monitoring, and Control of Computer Room Components
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Parallel Distributed Printer Controller Architecture
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Attenuating Vibrations in a Mounting Shelf for Multiple Disk Drives
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High Frequency Emi Shield with Air Flow for Electronic Device Enclosure
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Array Index Chaining for Tree Structure Save and Restore in a Process Swapping System
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Document Display System for Organizing and Displaying Documents as Screen Objects Organizing Along Strand Paths
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System and Method for Dynamically Analyzing and Improving the Performance of a Network
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Real-Time Data Cache Flushing Threshold Adjustment in a Server Computer
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Real-Time Data Cache Size Adjustment in a Server Computer
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Real-Time Open File Cache Hashing Table Restructuring in a Server Computer
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Semiconductor Structures and Packaging Methods
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Thread Properties Attribute Vector Based Thread Selection in Multithreading Processor
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Method for Quickly Painting and Copying Shallow Pixels on a Deep Frame Buffer
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Self-Locating Dual Motion Locking Apparatus for Joining Computer Housings
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Arbitration System for a Shared Dma Logic on a Network Adapter with a Large Number of Competing Requests Having Predicted Latency Field
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Reduced Static Raid Enclosure
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Variable-Grained Memory Sharing for Clusters of Symmetric Multi-Processors Using Private and Shared State Tables
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Multiple Wavelength Transceiver
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Dynamic Non-Coherent Cache Memory Resizing Mechanism
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Method for Fabricating a High Performance Vertical Bipolar Npn or Pnp Transistor Having Low Base Resistance in a Standard Cmos Process
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Off-Line Clock Synchronization for Multiprocessor Event Traces
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Method and Apparatus for Secure Remote Programming of Firmware and Configurations of a Computer Over a Network
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Automated Speech Alignment for Image Synthesis
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Memory Architecture Dependent Program Mapping
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Cabinet Slide Mounting Bracket
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Wallace-Tree Multipliers Using Half and Full Adders
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Disk Drive Locking Member with Handle
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A Hands-Free Interface to a Virtual Reality Environment Using Haead Tracking
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High Frequency Sampling of Processor Performance Counters
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Detecting Concurrency Errors in Multi-Threaded Programs
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Facial Image Method and Apparatus for Semi-Automatically Mapping a Face on to a Wireframe Topology
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Processor Performance Counter for Sampling the Execution Frequency of Individual Instructions
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Uninterruptible Power Supply with Fault Tolerance in a High Voltage Environment
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Computer Having Internally Mounted Peripheral Devices with Moveable Adapter
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Pruning of Short Paths in Static Timing Verifier
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Integrated Circuit Output Power Supply Transient Voltage Protection Circuit
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Input and Output Noise Reduction Circuit
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Fast Determination of Floating Point Sticky Bit from Input Operands
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Void and Cluster Apparatus and Method for Generating Dither Templates
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Division with Limited Carry-Propagation in Quotient Accumulation
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Interface That Permits Data Bus Signals to Pass Between High Frequency Processing Unit and Low Frequency Expansion Devices
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Temporally and Spatially Organized Database
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Electro-Static Discharge Protection Device Having a Modulated Control Input Terminal
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Secure Web Tunnel
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Method and Apparatus for Reducing the Apparent Read Latency When Connecting Busses with Fixed Read Reply Timeouts to Cpus with Write-Back Caches
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Speech Data Collection Over the World Wide Web
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Method and Apparatus for Performing Atomic Transactions in a Shared Memory Multi Processor System
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Limited Virtual Address Aliasing and Fast Context Switching with Multi-Set Virtual Cache Without Backmaps
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Two-Way Lock Mechanism with Cam Action
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Adaptive Stream Buffers
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Method and Apparatus for Strengthening Passwords for Protection of Computer Systems
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Task Processing Optimization in a Multiprocessor System
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Controlled Prefetching of Data Requested by a Peripheral
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A System for Sampling Network Packets by Only Storing the Network Packet That Its Error Check Code Matches with the Reference Error Check Code
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Loader Conditionally Replacing a Code Sequence with a Functionally-Alike Code Sequence in an Executable Program Intended for Execution in Different Run-Time Environments
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Compiler Generating Functionally-Alike Code Sequence in an Executable Program Intended for Execution in Different Run-Time Environments
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Method and Apparatus for Organizing and Accessing Electronic Mail Messages Using Labels and Full Text and Label Indexing
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Environmently Compensated Speech Processing
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Method for Detecting Human Body Motion in Frames of a Video Sequence
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Web-Based Electronic Mail Server Apparatus and Method Using Full Text and Label Indexing
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Replacing Large Bit Component of Electronic Mail (E-Mail) Message with Hot-Link in Distributed Computer System
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Method for Filtering Mail Messages for a Plurality of Client Computers Connected to a Mail Service System
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Technique for Dynamically Generating an Address Book in a Distributed Electronic Mail System
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Method and Apparatus to Expand an on Chip Fifo into Local Memory
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Auto-Calibrating Digital Delay Circuit
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Method and Apparatus for Accessing Copies of Documents Using a Web Browser Request Interceptor
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Updatings and Method for Updating a Copy of a Remote Document Stored in a Local Computer System
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Method and Apparatus for Modifying Copies of Remotely Stored Documents Using a Web Browser
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Detection of Scsi Devices at Illegal Locations
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Input/ Output Bus System in a Tower Building Block Sysrem
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Power Bus System in a Tower Building Block System
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Tower Building Block System
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Content Addressable Memory Having Memory Cells Storing Don't Care States for Address Translation
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Method for Testing and Verification of a Cpu Using a Reference Model
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Interface with Dual Mode of Operation
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Method and Apparatus for Fault Tolerant Bios Addressing
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Cabinet Security State Detection
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Method and Apparatus for Updating Host Memory in an Adapter to Minimize Host Cpu Overhead in Servicing an Interrupt
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Compact Self-Aligned Body Contact Silicon-on-Insulator Transistor
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Large Memory Allocation Method and Apparatus
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Method for Recovering Radial Distortion Parameters from a Single Camera Image
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Multiprobe Instruction Cache with Instruction-Based Probe Hint Generation and Trainng Whereby the Cache Bank or Way to Be Accessed Next Is Predicted
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Method and Apparatus for Configuring a Computer System
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Performance Counters Controlled by Programmable Logic
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Space-Time Memory
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Fault Notification System and Process Using Local Area Network
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Printed Circuit Board Having a Well Structure Accommodating One or More Capacitor Components
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Method for Aligning Text with Audio Signals
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Method for Ignoring Redundant Constraints in a Graphic Editor
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Dual Pci Bridge Docking
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Energy Absorbing Viscoelastic Spacer for Reducing Vibration to Disk Drives
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Using Global Memory Information to Manage Memory in a Computer Network
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Method and Apparatus for Generating an Extended Finite State Machine Architecture for a Software Specification
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Method and Apparatus for Statically Analyzing a Computer Program for Data Dependencies
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Method and Apparatus for Correlating Real-Time Audience Feedback with Segments of Broadcast Programs
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Fast Determination O Carry Inputs from Lower Order Product for Radix-8 Odd/Even Multiplier Array
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Method for Extracting a Three-Dimensional Model Using Appearance-Based Constrained Structure from Motion
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Method and Apparatus for Compositing Colors of Images with Memory Constraints for Storing Pixel Data
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Normalization Shift Prediction Independent of Operand Subtraction
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Method and Apparatus for Employing Commit-Signals and Prefetching to Maintain Inter-Reference Ordering in a High-Performance I/O Processor
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Method and Apparatus for Reducing Latency of Interreference Ordering in a Multiprocessor System
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Distributed Data Dependency Stall Mechanism
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Separate Victim Buffer Read and Release Control
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Order Supporting Mechanisms for Use in a Switch-Based Multi-Processor System
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Real Time Bit Map Capture and Sharing for Collaborative Tools
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System Fpr Compressing Bit Maps to Be Shared and Displayed in Collaborative Tool by Client and Server Systems
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Mechanism for Reducing Latency of Memory Barrier Operations on a Multiprocessor System
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Independent Victim Data Buffer and Probe Buffer Release Control Utilizing Control Flag
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Method and Apparatus for Releasing Victim Data Buffers of Computer Systems Using Victim Release Counters
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Employing Multiple Channels for Deadlock Avoidance in a Cache Coherency Protocol
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Method and Apparatus for Disambiguating Change-to-Dirty Commands in a Switch Based Multi-Processing System with Coarse Directories
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Technique for Reducing Latency of Inter-Reference Ordering Using Commit Signals in a Multiprocessor System Having Shared Caches
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Low Occupancy Protocol for Managing Concurrent Transactions with Dependencies
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Method and Apparatus for Delaying Victim Writes in a Switch-Based Multi-Processor System to Maintain Data Coherency
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Victimization of Clean Data Blocks
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A Multi-Processor Computer System Having a Data Switch with Simultaneous Insertion Buffers for Eliminating Arbitration Interdependencies
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Compression Protocol with Multiple Preset Dictionaries
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Method for Determining Target Address of Computed Jump Instructions in Executable Programs
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Prefetch Management for Dma Read Transactions Depending Upon Past History of Actual Transfer Lengths
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Link Time Optimization with Translation to Intermediate Program and Following Optimization Techniques Including Program Analysis Code Motion Live Variable Set Generation Order Analysis,Dead Code Eliminati on and Load Invariant Analyais
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Link Time Optimization via Dead Code Elimination Code Motion Code Partitioning Code Grouping Loop Analysis with Code Motion Loop Invariant Analysis and Active Variable to Register Analysis
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Inclusion Map for Accelerated Cache Flush
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Method and Apparatus for Resolving Overlapping Selection and Reselection Operations of Scsi Bus Protocols
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Sharing Memory Among Computer Processes
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Integrated Thermal Coupling for a Heat Generating Device
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Interleaved-Fin Thermal Connector
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Integrated Thermal Coupling for Heat Generating Device
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Apparatus and Method for Serialized Set Prediction
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System for Monitoring Computer System Performance
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Apparatus for Performing Fast Multiplication
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Method for Dynamically Remapping a Virtual Address to a Physical Address to Maintain an Even Distritution of Cache Page Addresses in a Virtual Address Space
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Memory Allocation Technique for Maintaining an Even Distribution of Cache Page Addresses Within a Data Structure
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Cross-Referenced Electrostatic Discharge Protection Systems and Methods for Power Supplies
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Method for Reclaiming Physical Pages of Memory While Maintaining an Even Distribution of Cache Page Addresses Within an Address Space
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Apparatus for Sampling Instruction Operand or Result Values in a Processor Pipeline
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Method for Estimating Statistics of Properties of Instructions Processed by a Processor Pipeline
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Method for Measuring Latencies by Randomly Selected Sampling of the Instructions While the Instruction Are Executed
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Method for Inserting Memory Prefetch Operations Based on Measured Latencies in a Program Optimizer
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Method for Estimating Statistics of Properties of Interactions Processed by a Processor Pipeline
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Method for Estimating Execution Rates of Program Execution Paths
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Apparatus for Randomly Sampling Instructions in a Procesor Pipeline
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Method and Apparatus for a Relaxed Bus Protocol Using Heuristics and Higher Level Supervision
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Bit-Depth Increase by Bit Replication
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Method and Apparatus for Controlling Providing of Conditioned Ac Power
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Apparatus and Method for Generating External Interface Signals in a Microprocessor
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Thermal Model for Central Processing Unit
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Distributed Packet Data with Centralized Snooping and Header Processing Router
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Bus Interface Slicing Mechanism Allowing for a Control/Data-Path Slice
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High Performance Recoverable Communication Method and Apparatus for Write-Only Networks
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Transmission of an Error Message Over a Network by a Computer Which Fails a Self-Test
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Wake Up of a Sleeping Compute R Using I/O Snooping and Imperfect Packet Filtering
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Computer with Remote Wake Up and Transmission of a Status Packet When the Computer Fails a Self Test
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Method and Apparatus for Performing Error Detection
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Uninterruptible Power Supply with Fault Tolerance in a High Voltage Environment
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Techinque for Ordering Internal Processor Register Accesses
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Method and Apparatus for Optimizing the Performance of Ldxl and Stxc Interlock Instructions in the Context of a Write Invalidate Protocol
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Method and Apparatus for Maximizing Utilization of an Internal Processor Bus in the Context of External Transactions Running at Speeds Fractionally Greater Than Internal Transaction Times
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Technique for Processing Images
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Technique for Updating a Background Image
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Technique for Acknowledging Multiple Objects Using a Computer Generated Face
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Method and Apparatus for Accessing a Cache Memory Utilization Distingushing Bit Rams
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Method and Apparatus for a Fast Variable Precedence Priority Encoder with Optimized Round Robin Precedence Update Scheme
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Scalable Distributed File System
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Cache Memory Exchange Optimized Memeory Organization for a Computer System
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Reduced-Latency Floating-Point Pipeline Using Normalization Shifts of Both Operands
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Encoding of Failing Bit Addresses to Facilitate Multi-Bit Failure Detect Using a Wired-or Scheme
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A Method for Dynamically Adjusting Multimedia Content of a Web Page by a Server in According to Network Path Characteristics Between Client and Server
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Method and Apparatus for Test Data Generation
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Speculative Issue of Instruction Under a Load Miss Shadow
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Access Mechanism for Parallel Status Update for Multiple Servers
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Scanning Force Microscope Thermal Microprobe
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Technique for Controlling and Processing a Section of an Interactive Presentation Simultaneously with Detecting Stimulus Event in Manner That Overrides Process
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Computer Method and Apparatus for Translating Text to Sound
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Esd Protection Clamp for Mixed Voltage I/O Stages Using Nmos Transistors
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Esd Protection Clamp for Mixed Voltage I/O Stages Using Nmos Transistors
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Method and Apparatus for Adding or Removing Devices from a Computer System Without Restarting
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Method and Apparatus Based on Relational Database Design Techniques Supporting Modeling, Analysis and Automatic Hypertext Generation for Structured Document Collections
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Hierarchical Ring Buffers for Buffering Data Between Processor and I/O Device Permitting Data Writes by Processor and Data Reads by I/O Device Simultaneously Directed at Different Buffers at Different Levels
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Register Scoreboard Logic with Register Read Availibility Signal to Reduce Instruction Issue Arbitration Latency
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Method for Cost-Effective Production Testing of Input Voltage Levels of the Forwarded Clock Interface of High Performance Integrated Circuits
Patent: 6,163,864 →
Application: 09/095,149 →
Method and Apparatus for Failure Recovery in a Multi-Processor Computer System
Patent: 6,199,179 →
Application: 09/095,266 →
Method and Apparatus for a Low Power Self Test of a Memory Subsystem
Patent: 6,067,649 →
Application: 09/095,435 →
Method and Apparatus for Minimizing Pincount Needed by External Memory Control Chip for Multiprocessors with Limited Memory Size Requirements
Patent: 6,199,153 →
Application: 09/099,383 →
Method and Apparatus for Resolving Probes in Multi-Processor Systems Which Do Not Use External Duplicate Tags for Probe Filtering
Patent: 6,295,583 →
Application: 09/099,400 →
Wearable Computing Device Mounted on Superior Dorsal Aspect of a Hand
Patent: 6,151,208 →
Application: 09/103,902 →
Method and Apparatus for Predicting Memory Dependence Using Store Sets
Patent: 6,108,770 →
Application: 09/103,984 →
Reservation and Dynamic Allocation of Resources for Sole Use of Docking Station Peripheral Device
Patent: 6,170,020 →
Application: 09/107,598 →
Enabling Access to a Selected One of Two Detected Same Type Peripheral Devices Connected to Separate Peripheral Slots in a Computer
Patent: 6,178,469 →
Application: 09/107,599 →
Charging System for Computer with Docking Station
Patent: 6,005,368 →
Application: 09/107,647 →
Dynamic Resource Allocation Across Bus Bridges
Patent: 6,216,192 →
Application: 09/107,940 →
.Peripheral Identification Using Bypassable Impedances Connected in Series
Patent: 6,138,182 →
Application: 09/108,933 →
Inter-Program Synchronous Communications Using a Collaboration Software System
Patent: 6,192,394 →
Application: 09/114,373 →
Phantom Resource Memory Address Mapping System
Patent: 6,185,654 →
Application: 09/118,985 →
Electromigration-Resistant via Structure
Patent: 6,096,637 →
Application: 09/124,198 →
User Transparent Mechanism for Profile Feedback Optimization
Patent: 6,158,049 →
Application: 09/132,449 →
Differential Sense Amplifier with Reduced Hold Time
Patent: 6,201,418 →
Application: 09/132,797 →
High-Speed Cmos Latch
Patent: 6,084,455 →
Application: 09/133,235 →
Semi-Mobile Desktop Personal Computer
Patent: 6,097,593 →
Application: 09/133,874 →
Physical Security System for Portable Computer/Port Replicator
Patent: 6,151,218 →
Application: 09/137,592 →
Port Replicator with Secure Integral Battery Charging Cradle
Patent: 6,046,571 →
Application: 09/138,317 →
Method and Apparatus for Providing Transient Suppression in a Central Processor Unit (Cpu) Phase Locked Loop (Pll) Clock Signal Synthesis Circuit
Patent: 6,104,251 →
Application: 09/143,945 →
Pivoting Door System for a Portable Computer
Patent: 5,918,957 →
Application: 09/148,235 →
Hinge System for a Portable Computer
Patent: 6,202,256 →
Application: 09/148,740 →
Low Profile Surface Mount Transformer
Patent: 6,046,662 →
Application: 09/162,667 →
Methods and Apparatus for Controlling a Power Supply with Improved Techniques for Providing Protection Limits
Patent: 6,011,679 →
Application: 09/163,705 →
Methods and Apparatus for Synchronizing a Plurality of Power Supplies
Patent: 6,133,717 →
Application: 09/164,416 →
Mechanism for High Bandwidth Dma Transfers in a Pci Environment
Patent: 5,968,153 →
Application: 09/170,812 →
System for Assigning Boot Strap Processor in Symmetric Multiprocessor Computer with Watchdog Reassignment
Patent: 6,009,521 →
Application: 09/178,184 →
Virtual Memory Allocation in a Virtual Address Space Having an Inaccessible Gap
Patent: 6,125,430 →
Application: 09/183,677 →
Computer Method and Apparatus for Analyzing Program Instructions Executing in a Computer System
Patent: 6,009,514 →
Application: 09/183,734 →
Normalization Shift Prediction Independent of Operand Subtraction
Patent: 6,101,516 →
Application: 09/191,143 →
System for Passing an Index Value with Each Prediction in Forward Direction to Enable Truth Predictor to Associate Truth Value with Particular Branch Instruction
Patent: 6,081,887 →
Application: 09/191,869 →
Autonomous Relational Database Coprocessor
Patent: 6,108,663 →
Application: 09/192,989 →
Method and Apparatus for Test Data Generation
Patent: 6,148,427 →
Application: 09/193,506 →
Method and Apparatus for Relative Error Scheduling in a Communications Network Using Discrete Rates and Proportional Rate Scaling
Patent: 6,108,305 →
Application: 09/197,137 →
Cross-Referenced Electrostatic Discharge Protection Systems and Methods for Power Supplies
Patent: 5,999,386 →
Application: 09/203,417 →
Input and Output Noise Reduction Circuit
Patent: 5,986,868 →
Application: 09/206,019 →
Arbitration System Based on Requester Class and Relative Priority Including Transmit Descriptor Valid Bit for a Shared Resource Having Multiple Requesters
Patent: 6,199,124 →
Application: 09/206,200 →
Fast Determination of Carry Inputs from Lower Order Product for Radix-8 Odd/Even Multiplier Array
Patent: 6,131,107 →
Application: 09/208,169 →
Computer Method and Apparatus for Text-to-Speech Synthesizer Dictionary Reduction
Patent: 6,208,968 →
Application: 09/212,874 →
Method and Apparatus for Balancing Load Vs. Store Acess to a Primary Data Cache
Patent: 6,163,821 →
Application: 09/215,354 →
A Multi-Processor System for Transferring Data Without Incurring Deadlock Using Hierarchical Virtual Channels
Patent: 6,094,686 →
Application: 09/220,161 →
Skipping Clock Interrupts During System Inactivity to Reduce Power Consumption
Patent: 6,161,187 →
Application: 09/232,009 →
Bus Interface Slicing Mechanism Allowing for a Control/Data Path Slice
Patent: 6,077,306 →
Application: 09/233,839 →
High Input Impedance, Strobed Cmos Differential Sense Amplifier with Double Fire Evaluate
Patent: 6,107,839 →
Application: 09/241,003 →
Embedded Input Logic in a High Input Impedance Strobed Cmos Differential Sense Amplifier
Patent: 6,195,377 →
Application: 09/241,212 →
Method and System for Controlling Radio Frequency Radiation in Microelectronic Packages Using Heat Dissipation Structures
Patent: 6,075,700 →
Application: 09/241,351 →
Method and Apparatus for Providing Dma Transfers Between Devices Coupled to Different Host Bus Bridges
Patent: 6,012,120 →
Application: 09/271,558 →
Method and Apparatus for Controlling Providing of Conditioned Ac Power
Patent: 6,147,885 →
Application: 09/276,989 →
Void and Cluster Apparatus and Method for Generating Dither Templates
Patent: 6,172,773 →
Application: 09/309,472 →
Sinusoidal Radio-Frequency Clock Distribution System for Synchronization of a Computer System
Patent: 6,184,736 →
Application: 09/315,588 →
Generalized Push-Pull Cascode Logic Technique
Patent: 6,144,228 →
Application: 09/340,774 →
Method and Apparatus for a Fast Variable Precedence Priority Encoder with Optimized Round Robin Precedence Update Scheme
Patent: 6,133,760 →
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Related Assignments (3)
Other recorded transfers of the patents in this record — the chain of ownership.
Change of Name Jan 21, 2004
From: COMPAQ INFORMATION TECHNOLOGIES GROUP, LP
To: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Reel/Frame 015000/0305 →
Corrective Assignment Deleting U.S. Patent No. 5,112,662, Previously Recorded on Reel 012447 Frame 0903. Sep 15, 2006
From: DIGITAL EQUIPMENT CORPORATION; COMPAQ COMPUTER CORPORATION
To: COMPAQ INFORMATION TECHNOLOGIES GROUP, L.P.
Reel/Frame 018279/0421 →
Change of Name Feb 13, 2008
From: COMPAQ INFORMATION TECHNOLOGIES GROUP, L.P.
To: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Reel/Frame 020497/0863 →