Patent Assignment
Reel/Frame 036353/0134
Assignment of Assignor's Interest
Recorded: 2015-08-14
Pages: 10
Assignor
INFINEON TECHNOLOGIES AG
Executed: 2015-07-08
Assignee
POLARIS INNOVATIONS LIMITED
29 EARLSFORT TERRACE, DUBLIN 2, DUBLIN, IRELAND
Covered Properties
(115)
Feedback Pulse Generators
Patent:
5,929,684 →
Application:
09/036,486 →
Self Aligned Buried Plate
Patent:
6,699,794 →
Application:
09/037,287 →
Semiconductor Device with Vertical Transistor and Buried Word Line
Patent:
6,172,390 →
Application:
09/047,581 →
Dynamic Random Access Memory Circuit and Methods Therefor
Patent:
5,909,388 →
Application:
09/052,799 →
Trench Capacitor with Epi Buried Layer
Patent:
6,265,741 →
Application:
09/056,119 →
Method of Forming Stack Capacitor with Improved Plug Conductivity
Patent:
6,046,059 →
Application:
09/074,882 →
Semiconductors Having Defect Denuded Zones
Patent:
6,040,211 →
Application:
09/093,796 →
Integrated Circuit with Improved Off Chip Drivers
Patent:
6,137,316 →
Application:
09/093,797 →
Method of Forming Deep Trench Capacitors
Patent:
6,103,585 →
Application:
09/093,801 →
Vertical Device Formed Adjacent to a Worldline Sidewall and Method for Semiconductor Chips
Patent:
6,091,094 →
Application:
09/095,793 →
Memory with Reduced Wire Connections
Patent:
5,933,374 →
Application:
09/097,545 →
Trench Capacitor with Isolation Collar and Corresponding Manufacturing Method
Patent:
6,310,375 →
Application:
09/097,783 →
High Density Plasma Cvd Process for Making Dielectric Anti-Reflective Coatings
Patent:
6,060,132 →
Application:
09/097,872 →
Phase Shift Mask Having Multiple Alignment Indications and Method of Manufacture
Patent:
6,042,972 →
Application:
09/098,785 →
Semiconductor Metalization System and Method Background of the Invention
Patent:
6,137,178 →
Application:
09/099,093 →
Lock Arrangement for a Calabrated Ddl in Ddr Sdram Applications
Patent:
6,043,694 →
Application:
09/103,871 →
Method for Forming a Seminconductor Fuse
Patent:
6,261,937 →
Application:
09/105,107 →
System and Method for Optically Measuring Dielectric Thickness in Semiconductor Devices
Patent:
6,166,819 →
Application:
09/105,632 →
Low Leakage, Low Capacitance Isolation Material
Patent:
6,465,370 →
Application:
09/105,633 →
Interleaved Sense Amplifier with a Single-Sided Precharge Device
Patent:
6,049,492 →
Application:
09/107,191 →
Semiconductor Manufacturing Method
Patent:
6,121,098 →
Application:
09/107,672 →
Amorphously Deposited Metal Oxide Ceramic Films
Patent:
6,133,051 →
Application:
09/107,861 →
Prevention of Photoresist Poisoning from Dielectric Antireflective Coating in Semiconductor Fabrication
Patent:
6,103,456 →
Application:
09/120,629 →
Silicon Oxynitride Cap for Fluorinated Silicate Glass Film in Intermetal Dielectric Semiconductor Fabrication
Patent:
6,300,672 →
Application:
09/120,630 →
Apparatus and Method for Forming Controlled Deep Trench Top Isolation Layers
Patent:
6,074,909 →
Application:
09/127,262 →
Vertical Device Formed Adjacent to a Wordline Sidewall and Method for Semiconductor Chips
Patent:
6,699,750 →
Application:
09/145,623 →
Combined Preanneal/Oxidation Step Using Rapid Thermal Processing
Patent:
6,436,846 →
Application:
09/146,870 →
Metallization Etching Techniques for Reducing Post-Etch Corrosion of Metal Lines
Patent:
6,177,353 →
Application:
09/153,390 →
Method of Enhancing Semiconductor Wafer Release
Patent:
6,132,294 →
Application:
09/161,793 →
Stacked Capacitator Memory Cell and Method of Fabrication
Patent:
6,136,660 →
Application:
09/161,861 →
Memory Cell with a Stacked Capacitor
Patent:
6,207,524 →
Application:
09/162,867 →
6 1/4 F2 Dram Cell Structure with Four Nodes Per Bitline-Stud and Two Topological Wordline Levels
Patent:
6,188,095 →
Application:
09/163,670 →
Method for Fabricating Transistors
Patent:
6,323,103 →
Application:
09/175,267 →
Fuse Layout for Improved Fuse Blow Process Window
Patent:
6,121,074 →
Application:
09/186,515 →
Delay Lock Loop
Patent:
6,137,327 →
Application:
09/200,338 →
Silicon Oxynitride Cap for Fluorinated Silicate Glass Film in Intermetal Dielectric Semiconductor Fabrication
Patent:
6,008,120 →
Application:
09/204,031 →
Measurement System and Method for Measuring Critical Dimensions Using Ellipsometry
Patent:
6,031,614 →
Application:
09/204,402 →
Extended Trench for Preventing Interaction Between Components of Stacked Capacitors
Patent:
6,222,220 →
Application:
09/209,198 →
Methods for Enhancing the Metal Removal Rate During the Chemical-Mechanical Polishing Process of a Semiconductor
Patent:
6,136,714 →
Application:
09/213,469 →
Adjustable Strength Driver Circuit and Method of Adjustment
Patent:
6,177,810 →
Application:
09/215,607 →
Method of Making a Microelectronic Structure
Patent:
6,221,757 →
Application:
09/234,341 →
Arrangement for Controlling Voltage Generators in Multi Voltage Generator Chips Such as Drams
Patent:
6,094,395 →
Application:
09/253,996 →
Method for Nondestructive Measurement of Dopant Concentrations and Profiles in the Drift Region of Certain Semiconductor Devices
Patent:
6,294,919 →
Application:
09/266,038 →
Method for Nondestructive Measurement of Minority Carrier Diffusion Length and Minority Carrier Lifetime in Semiconductor Devices
Patent:
6,346,821 →
Application:
09/266,039 →
Radiation-Sensitive Mixture and Its Use
Patent:
6,063,543 →
Application:
09/299,364 →
Film-Forming Polymers
Patent:
6,306,990 →
Application:
09/299,365 →
Soi Semiconductor Configuration and Method of Fabricating the Same
Patent:
6,958,282 →
Application:
09/313,424 →
Improved Process for Dram Cell Production
Patent:
6,297,087 →
Application:
09/393,700 →
Integrated Circuit Having Adjustable Delay Units for Clock Signals
Patent:
6,191,627 →
Application:
09/408,685 →
Integrated Circuit with Adjustable Delay Unit
Patent:
6,194,928 →
Application:
09/408,687 →
Method for Manufacturing an Integrated Circuit with Low Threshold Voltage Differences of the Tranistors Therein
Patent:
6,387,766 →
Application:
09/429,834 →
Read/Write Memory with Self-Test Device and Associated Test Method
Patent:
6,539,506 →
Application:
09/431,529 →
Semiconductor Chip Configuration and Method of Controlling a Semiconductor Chip
Patent:
6,615,289 →
Application:
09/437,956 →
Circuit Configuration with a Temperature-Dependent Semiconductor Component Test and Repair Logic Circuit
Patent:
6,297,995 →
Application:
09/440,721 →
Ferroelectric Memory Configuration
Patent:
6,137,712 →
Application:
09/440,818 →
Magnetic Memory
Patent:
6,359,829 →
Application:
09/443,751 →
Method of Forming a Buried Plate
Patent:
6,316,310 →
Application:
09/449,362 →
Semiconductor Component Having at Least One Capacitor and Methods for Fabricating It
Patent:
6,323,513 →
Application:
09/449,716 →
Integrated Circuit Having a Decoder
Patent:
6,255,855 →
Application:
09/470,310 →
Stack Capacitor with Improved Plug Cunductivity
Patent:
6,313,495 →
Application:
09/478,312 →
Process for Producing Ultra-Pure Water, and Configuration for Carrying Out a Process of This Nature
Patent:
6,461,519 →
Application:
09/481,637 →
Conveying System
Patent:
6,336,546 →
Application:
09/481,639 →
Mehtod for repairing defective memory cells of an integrated semiconductor memory
Patent:
6,292,414 →
Application:
09/483,738 →
Integrated Semiconductor Circuit and Method for Functional Testing of Pad Cells
Patent:
6,949,946 →
Application:
09/484,781 →
Method for improving the quality of metal conductor tracks on semiconductor structures
Patent:
6,337,263 →
Application:
09/492,654 →
Method for Producing Structures on the Surface of a Semiconductor Wafer
Patent:
6,457,168 →
Application:
09/492,655 →
Method for improving the readability of alignment marks
Patent:
6,153,492 →
Application:
09/492,656 →
Method for fabricating an isolation trench using an auxiliary layer
Patent:
6,255,193 →
Application:
09/494,774 →
Apparatus and method for forming controlled deep trench top isolation layers
Patent:
6,359,299 →
Application:
09/503,992 →
Exhaust Apparatus
Patent:
6,443,171 →
Application:
09/504,274 →
Electrical test structure on a semiconductor substrate and test method
Patent:
6,310,361 →
Application:
09/504,275 →
Semiconductor Memory Having Memory Bank Decoders Disposed Symmetrically on a Chip
Patent:
6,188,634 →
Application:
09/505,379 →
Semiconductor Memory Configuration with Dummy Components on Continuous Diffusion Regions
Patent:
6,441,469 →
Application:
09/511,812 →
Integrated memory
Patent:
6,157,561 →
Application:
09/513,587 →
Method for Mounting a Semiconductor Chip on a Carrier Layer and Device for Carrying Out the Method
Patent:
6,534,345 →
Application:
09/514,265 →
Semiconductor memory configuration with a bit-line twist
Patent:
6,310,399 →
Application:
09/514,268 →
Integrated circuit for producing two output clock signals at levels which do not overlap in time
Patent:
6,307,416 →
Application:
09/519,541 →
Integrated semiconductor memory configuration with self-buffering of supply voltages
Patent:
6,236,612 →
Application:
09/523,146 →
Circuit Configuration for the Interference- Free Initialization of Delayed Locked Loop Circuits with Fast Lock
Patent:
6,639,958 →
Application:
09/524,240 →
Configuration Having a Field-Effect Transistor Having a Short Channel Length and an Adjustable Threshold Voltage
Patent:
6,417,722 →
Application:
09/525,820 →
Integrated Circuit with Improved Off Chip Drivers
Patent:
6,373,286 →
Application:
09/603,631 →
Test circuit for testing a digital semiconductor circuit configuration
Patent:
6,256,243 →
Application:
09/642,734 →
Lead Frame, Circuit Board with Lead Frame, and Method for Producing the Lead Frame
Memory Cell with a Stacked Capacitor
Memory System
Dram Cell Arrangement
Patent:
6,492,221 →
Application:
09/806,427 →
Dram Cell System and Method for Producing Same
Patent:
6,566,187 →
Application:
09/806,614 →
Circuit configuration for generating a reference voltage for reading a ferroelectric memory
Substrate Assembly Having a Depression Suitable for an Integrated Circuit Configuration and Method for Its Fabrication
Patent:
6,608,340 →
Application:
09/821,853 →
Ferroelectric Transistor and Method for Fabricating It
A Method for Preventing Etching-Induced Damage to a Metal Oxide Film by Patterning the Film After a Nucleation Anneal but While Still Amorphous and Then Thermally Annealing to Crystallize
Femfet Device and Method for Producing Same
Patent:
6,737,689 →
Application:
09/857,262 →
Field-Effect-Controlled Transistor and Method for Fabricating the Transistor
New Complex of an Element of Transition Group Iv or V for Forming an Improved Precursor Combination
Method of Structuring a Metal-Containing Layer
Integrated Circuit Configuration and Method for Manufacturing It
Circuit Configuration Having at Least One Nanoelectronic Component and Method for Fabricating the Component
Integrated Memory with Redundancy
Capacitor Electrode Arrangement with Oxygen Iridium Between Silicon and Oxygen Barrier Layer
Integrated Memory
Method and Configuration for Verifying a Layout of an Integrated Circuit and Application Thereof for Fabricating the Integrated Circuit
Process for Fabrication of a Semiconductor Component Having a Tungsten Oxide Layer
Integrated Memory and Corresponding Operating Method
Semiconductor Structure Having an Interconnect and Method of Producing the Semiconductor Structure
Method for Operating a Memory Cell Configuration Having Dynamic Gain Memory Cells
Miniaturized Capacitor with Solid-State Dielectric, in Particular for Integrated Semiconductor Memories, E.G. Drams, and Method for Fabricating Such a Capacitor
Magnetoresistive Memory Cell Configuration and Method for Its Production
Memory Cell Configuration and Production Method
Integrated Circuit Configuration and Method of Fabricating a Dram Structure with Buried Bit Lines or Trench Capacitors
Dram Cell Configuration and Fabrication Method
Method for Fabricating a Trench Isolation for Electrically Active Components
Method of Filling Gaps on a Semiconductor Wafer
Memory Cell Configuration and Method for Fabricating It
Integrated Memory Having Memory Cells and Reference Cells, and Operating Method for Such a Memory
Method for Fabricating a Semiconductor Component
Related Assignments
(4)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Jan 12, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023768/0001 →
Assignment of Assignor's Interest
Jan 13, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023773/0001 →
Assignment of Assignor's Interest
Jan 13, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023828/0001 →
Assignment of Assignor's Interest
May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →