IP Library › Assignment 008059/0846
Patent Assignment
Reel/Frame 008059/0846

Assignment of Assignor's Interest

Recorded: 1996-08-05 Pages: 19
Assignor
Assignee
NATIONAL SEMICONDUCTOR CORPORATION
M/S D3-579, 2900 SEMICONDUCTOR DRIVE, SANTA CLARA, CALIFORNIA, 95051
Covered Properties (312)
Electronic Control System
Patent: 4,209,833 →
Application: 05/530,319 →
Data Storage Apparatus
Patent: 4,352,492 →
Application: 05/745,025 →
Low Cost Watch Case
Patent: 4,229,936 →
Application: 05/788,866 →
Input Stage Using Field Effect Transistors for Biasing
Patent: 4,194,136 →
Application: 05/807,602 →
Analog Multiplexer
Patent: 4,196,358 →
Application: 05/825,020 →
Insulated Gate Field-Effect Transistor Read-Only Memory Cell
Patent: 4,173,766 →
Application: 05/834,017 →
Fixturing System
Patent: 4,230,985 →
Application: 05/868,822 →
Insulated-Gate Field-Effect Transistor with Self-Aligned Contact Hole to Source or Drain
Patent: 4,169,270 →
Application: 05/893,918 →
Optically Coupled Isolator Device and Method of Making Same
Patent: 4,160,308 →
Application: 05/900,685 →
Headless Resistor
Patent: 4,191,964 →
Application: 05/914,637 →
Integrated Circuit Structures Utilizing Conductive Buried Regions
Patent: 4,198,649 →
Application: 05/921,375 →
High-Performance Address Buffer for Random-Access Memory
Patent: 4,214,175 →
Application: 05/944,687 →
Method of Producing a Metal- Semiconductor Field-Effect Transistor
Patent: 4,277,882 →
Application: 05/966,182 →
Inverse Transistor Coupled Memory Cell
Patent: 4,257,059 →
Application: 05/971,623 →
Compensation of Vbe Non-Linearities Over Temperature by Using High Base Sheet Resistivity Devices
Patent: 4,242,693 →
Application: 05/972,742 →
Signal Cancelling Device
Patent: 4,236,048 →
Application: 06/001,139 →
Process for Forming Field Dielectric Regions in Semiconductor Structures Without Encroaching on Device Regions
Patent: 4,170,500 →
Application: 06/003,674 →
Transistor Logic Tristate Output with Feedback
Patent: 4,255,670 →
Application: 06/005,928 →
Transistor Logic Tristate Output with Reduced Power Dissipation
Patent: 4,287,433 →
Application: 06/005,929 →
Memory Array with Sequential Row and Column Addressing
Patent: 4,231,110 →
Application: 06/007,103 →
Charge-Coupled Device Serial Analog-to-Digital Converter and Associated Conversion Method
Patent: 4,275,387 →
Application: 06/029,604 →
Merged Bipolar/Field-Effect Bistable Memory Cell
Patent: 4,276,616 →
Application: 06/032,045 →
Ignition Control System
Patent: 4,275,701 →
Application: 06/033,667 →
Transistor Logic Output for Reduced Power Consumption and Increased Speed During Low to High Transition
Patent: 4,321,490 →
Application: 06/034,380 →
Process for Patterning Metal Connections on a Semiconductor Structure by Using a Tungsten-Titanium Etch Resistant Layer
Patent: 4,267,012 →
Application: 06/034,781 →
Method of Preventing Etch Masking During Wafer Etching
Patent: 4,251,317 →
Application: 06/034,824 →
Method for Forming Shaped Buried Layers in Semiconductor Devices and the Resulting Structure
Patent: 4,251,300 →
Application: 06/039,070 →
Eprom Reliability Test Circuit
Patent: 4,253,059 →
Application: 06/039,096 →
Universal Test Fixture Employing Interchangeable Wired Personalizers
Patent: 4,352,061 →
Application: 06/042,116 →
Rom Program Security Circuits
Patent: 4,268,911 →
Application: 06/050,909 →
Preset Circuit for Information Storage Devices
Patent: 4,326,270 →
Application: 06/058,638 →
Transistor Logic Tristate Device with Reduced Output Capacitance
Patent: 4,311,927 →
Application: 06/058,674 →
Transistor Logic Output Device for Diversion of Miller Current
Patent: 4,330,723 →
Application: 06/065,991 →
Input Stage Using Junction Field Effect Transistors for Biasing
Patent: 4,316,102 →
Application: 06/075,435 →
Electronic Testing System
Patent: 4,280,220 →
Application: 06/075,916 →
Electrical Validator for a Printed Circuit Board Test Fixture and a Method of Validation Thereof
Patent: 4,290,015 →
Application: 06/086,220 →
Voltage Protection Circuit for Binary Data-Storage Device
Patent: 4,311,930 →
Application: 06/104,639 →
Ignition Control System with Electronic Advance
Patent: 4,324,216 →
Application: 06/110,736 →
Power Supply with Increased Dynamic Range
Patent: 4,302,717 →
Application: 06/118,168 →
Method for Making an Integrated Injection Logic Structure Including a Self-Aligned Base Contact
Patent: 4,322,882 →
Application: 06/118,178 →
Method of Fabricating Self-Aligned Lateral Bipolar Transistor Utilizing Special Masking Techniques
Patent: 4,298,402 →
Application: 06/118,291 →
Sense Amplifier and Sensing Methods
Patent: 4,370,737 →
Application: 06/120,426 →
Data Latch with Enable Signal Gating
Patent: 4,334,157 →
Application: 06/123,717 →
Solid State Alarm Clock
Patent: 4,301,524 →
Application: 06/129,520 →
Digital-To-Analog Switching Interface Circuit
Patent: 4,308,470 →
Application: 06/133,691 →
Phase Locked Loop Motor Speed Control
Patent: 4,307,324 →
Application: 06/133,692 →
Process for Suppressing Electromigration in Conducting Lines Formed on Integrated Circuits by Control of Crystalline Boundary Orientation
Patent: 4,352,239 →
Application: 06/141,040 →
Interruptible Microprogram Sequencing Unit and Microprogrammed Apparatus Utilizing Same
Patent: 4,398,244 →
Application: 06/147,100 →
Sense Amplifier for Ccd Memory
Patent: 4,354,257 →
Application: 06/152,638 →
Computer-Controlled High-Speed Circuit for Testing Electronic Devices
Patent: 31,056 →
Application: 06/154,151 →
Arithmetic Logic Unit with Improved Bi-Directional Data Path
Patent: 4,396,979 →
Application: 06/155,153 →
High Performance Microprocessor System
Patent: 4,412,283 →
Application: 06/155,832 →
Process for Patterning Metal Connections on a Semiconductor Structure by Using an Aluminum Oxide Etch Resistant Layer
Patent: 4,289,574 →
Application: 06/157,996 →
Combined Integrated Injection Logic and Transistor-Transistor Logic Microprocessor Integrated Circuit Design
Patent: 4,396,980 →
Application: 06/167,614 →
Mos Comparator Circuit
Patent: 4,463,270 →
Application: 06/171,762 →
Plasma Passivation Technique for the Prevention of Post-Etch Corrosion of Plasma-Etched Aluminum Films
Patent: 4,325,984 →
Application: 06/172,745 →
Apparatus for Crystl Shaping
Patent: 4,331,452 →
Application: 06/175,174 →
Method for Semiconductor Memory Testing
Patent: 4,335,457 →
Application: 06/176,353 →
Multiple Preamplifiers with Intervening Overflow Cell for Charge Coupled Imaging Devices
Patent: 4,398,301 →
Application: 06/186,108 →
Mos Battery Backup Controller for Microcomputer Random Access Memory
Patent: 4,384,350 →
Application: 06/203,182 →
Regulated Mos Substrate Bias Voltage Generator for a Static Random Access Memory
Patent: 4,322,675 →
Application: 06/203,183 →
Method and Circuitry for Correcting Errors in Recirculating Memories
Patent: 4,365,332 →
Application: 06/203,774 →
Method and Apparatus for Digital Converter Testing
Patent: 4,419,656 →
Application: 06/204,979 →
Electrically Erasable Programmable Read-Only Memory
Patent: 4,377,857 →
Application: 06/207,859 →
Printed Circuit Board Test Fixture Having Interchangeable Card Personalizers
Patent: 4,321,533 →
Application: 06/213,708 →
Multilayer Metal Silicide Interconnections for Integrated Circuits
Patent: 4,398,335 →
Application: 06/214,615 →
A Method for Forming a Headless Resistor Utilizing Selective Diffusion and Special Contact Formation
Patent: 4,332,070 →
Application: 06/216,401 →
Address Gate for Memories to Protect Stored Data, and to Simplify Memory Testing, and Method of Use Thereof
Patent: 4,409,675 →
Application: 06/219,294 →
High Speed, Nonvolatile, Electrically Erasable Memory Cell and System
Patent: 4,398,338 →
Application: 06/219,784 →
Precision Optical Spacers for Image Sensor Filters
Patent: 4,388,525 →
Application: 06/233,347 →
Polycrystalline Silicon Schottky Diode Array
Patent: 4,425,379 →
Application: 06/233,348 →
Method for Manufacturing a Semiconductor Structure Having Reduced Lateral Spacing Between Buried Regions
Patent: 4,373,252 →
Application: 06/234,289 →
Method and Means for Internal Error Check in a Digital Memory
Patent: 4,384,353 →
Application: 06/235,803 →
Method and Means for Diagnostic Testing of Ccd Memories
Patent: 4,409,676 →
Application: 06/235,804 →
Binary Germanium-Silicon Interconnect and Electrode Structure for Integrated Circuits
Patent: 4,442,449 →
Application: 06/243,986 →
Laser Scanning Method for Annealing, Glass Flow and Related Processes
Patent: 4,415,794 →
Application: 06/244,395 →
Integrated Circuit Power Transistor Array
Patent: 4,475,119 →
Application: 06/254,334 →
Supply Voltage Sense Amplifier
Patent: 4,368,420 →
Application: 06/254,338 →
Serpentine Charge Transfer Device
Patent: 4,446,473 →
Application: 06/258,866 →
Alignment Target for Electron-Beam Write System
Patent: 4,351,892 →
Application: 06/260,514 →
Logic Structure Utilizing Polycrystaline Silicon Schottky Diodes
Patent: 4,418,468 →
Application: 06/261,842 →
Process for Fabricating Non-Encroaching Planar Insulating Regions in Integrated Circuit Structures
Patent: 4,374,011 →
Application: 06/261,843 →
Method of Forming Self-Aligned Lateral Bipolar Transistor
Patent: 4,435,225 →
Application: 06/262,568 →
Bonding Wire Ball Forming Method and Apparatus
Patent: 4,390,771 →
Application: 06/262,595 →
Method for Analyzing a Digital to-Analog Converter with a Nonideal Analog-to-Digital Converter
Patent: 4,335,373 →
Application: 06/264,928 →
Radiation Protection for Integrated Circuits Utilizing Tape Automated Bonding
Patent: 4,380,566 →
Application: 06/282,569 →
Random Access Memory Dual Word Line Recovery Circuitry
Patent: 4,393,476 →
Application: 06/282,767 →
Method for Lpcvd Co-Deposition of Metal and Silicon to Form Metal Silicide
Patent: 4,359,490 →
Application: 06/282,768 →
Random Access Memory Preset Circuitry
Patent: 4,393,473 →
Application: 06/282,893 →
Lead Frame Wire Bonding by Preheating
Patent: 4,434,347 →
Application: 06/294,411 →
Method of Detecting and Repairing Latent Defects in a Semiconductor Dielectric Layer
Patent: 4,420,497 →
Application: 06/295,417 →
Laser Induced Flow of Glass Bond Materials
Patent: 4,542,037 →
Application: 06/300,706 →
Lift-Off Shadow Mask
Patent: 4,387,145 →
Application: 06/306,116 →
Digital Tester Local Memory Data Storage System
Patent: 4,433,414 →
Application: 06/307,322 →
Tri-Level Input Buffer
Patent: 4,449,065 →
Application: 06/308,070 →
Dynamic Ttl Input Comparator for Cmos Devices
Patent: 4,485,317 →
Application: 06/308,073 →
Test Vector Indexing Method and Apparatus
Patent: 4,493,045 →
Application: 06/312,839 →
Dynamic Read Reference Voltage Generator
Patent: 4,386,420 →
Application: 06/313,001 →
Method for Forming Submicron Bipolar Transistors Without Epitaxial Growth and the Resulting Structure
Patent: 4,472,873 →
Application: 06/313,875 →
A Method of Fabricating Electrically Connected Regions of Opposite Conductivity Type in a Semiconductor Structure
Patent: 4,617,071 →
Application: 06/315,553 →
Method of Making an Integrated Circuit Bipolar Memory Cell
Patent: 4,488,350 →
Application: 06/315,678 →
Bit Line Powered Translinear Memory Cell
Patent: 4,442,509 →
Application: 06/315,679 →
Corrosion Inhibition of Aluminum or Aluminum Alloy Film Utilizing Bromine-Containing Plasma
Patent: 4,351,696 →
Application: 06/315,693 →
Self-Refreshing Memory Cell
Patent: 4,423,491 →
Application: 06/324,343 →
Self-Refreshing Memory Cell
Patent: 4,435,786 →
Application: 06/324,344 →
Laser Induced Flow Ge-O Based Materials
Patent: 4,443,493 →
Application: 06/339,600 →
Laser Induced Flow Ge-0 Based Materials
Patent: 4,431,900 →
Application: 06/339,601 →
Current Dump Circuit for Bipolar Random Access Memories
Patent: 4,477,885 →
Application: 06/340,145 →
A Method for the Formation of High Density Memory Cells Using Ion Implantation Techniques
Patent: 4,433,471 →
Application: 06/340,395 →
Method of Programming of Junction-Programmable Read-Only Memories
Patent: 4,480,318 →
Application: 06/349,790 →
Sense/Restore Circuit for Dynamic Random Access Memory
Patent: 4,477,886 →
Application: 06/352,967 →
Identification of Repaired Integrated Circuits
Patent: 4,480,199 →
Application: 06/360,028 →
Programmable Address Buffer for Partial Products
Patent: 4,476,546 →
Application: 06/360,029 →
Smooth Glass Insulating Film Over Interconnects on an Integrated Circuit
Patent: 4,490,737 →
Application: 06/362,322 →
Method for Forming a Low Temperature Binary Glass
Patent: 4,417,914 →
Application: 06/362,333 →
Bypass Circuit for Word Line Cell Discharge Current
Patent: 4,488,263 →
Application: 06/363,198 →
Method and Apparatus for Analyzing an Analog-to-Digital Converter with a Nonideal Digital-to-Analog Converter
Patent: 4,465,995 →
Application: 06/364,374 →
Lead Format for Tape Automated Bonding
Patent: 4,390,598 →
Application: 06/365,686 →
Programmable Deskewing of Automatic Test Equipment
Patent: 4,488,297 →
Application: 06/365,829 →
Telephone Regulator Circuitry
Patent: 4,495,382 →
Application: 06/371,328 →
Method of Removing Bulk Impurities from Semiconductor Wafers
Patent: 4,410,395 →
Application: 06/376,890 →
Mask Programmable Charge Coupled Device Transversal Filter
Patent: 4,612,522 →
Application: 06/376,894 →
Test System Memory Architecture for Passing Parameters and Testing Dynamic Components
Patent: 4,502,127 →
Application: 06/378,937 →
Method of Fabricating Power Mosifet Structure Ulitizing Self-Aligned Diffusion and Etching Techniques
Patent: 4,503,598 →
Application: 06/380,170 →
Bipolar Memory Cell
Patent: 4,543,595 →
Application: 06/380,184 →
Deskewing Time-Critical Signals in Automatic Test Equipment
Patent: 4,511,846 →
Application: 06/381,617 →
R. F. Multi-Pin Connector
Patent: 4,534,602 →
Application: 06/382,280 →
Programmable Output Buffer
Patent: 4,481,432 →
Application: 06/386,125 →
Synchronous Sense Amplifier
Patent: 4,484,311 →
Application: 06/387,111 →
Digital Logic Level Comparator Particularly for Digital Test Systems
Patent: 4,523,143 →
Application: 06/389,880 →
Static Ram Cell
Patent: 4,554,644 →
Application: 06/390,082 →
High-Speed Error Correcting Random Access Memory System
Patent: 4,561,095 →
Application: 06/399,670 →
Dynamic Ignition Apparatus
Patent: 4,538,585 →
Application: 06/404,068 →
Adhesion Bond-Breaking of Lift-Off Regions on Semiconductor Structures
Patent: 4,428,796 →
Application: 06/404,108 →
Lift-Off Process for Fabricating Self-Aligned Contacts
Patent: 4,440,804 →
Application: 06/404,109 →
Lift-Off Wafer Processing
Patent: 4,451,971 →
Application: 06/404,110 →
Power Supply Threshold Activation Circuit
Patent: 4,481,430 →
Application: 06/404,318 →
Dynamically Controllable Addressing in Automatic Test Equipment
Patent: 4,480,315 →
Application: 06/408,404 →
Method and System for Selectively Loading Test Data into Test Data Storage Means of Automatic Digital Test Equipment
Patent: 4,493,079 →
Application: 06/409,068 →
Redundant Columns for Byte Wide Memories
Patent: 4,485,459 →
Application: 06/420,200 →
Cover Gas Control of Bonding Ball Formation
Patent: 4,476,365 →
Application: 06/433,448 →
Control of Substrate Injection in Lateral Bipolar Transistors
Patent: 4,507,848 →
Application: 06/443,846 →
Temperature Stabilized Stop-Restart Oscillator
Patent: 4,497,998 →
Application: 06/452,606 →
High Voltage Analog Solid State Switch
Patent: 4,611,123 →
Application: 06/452,607 →
Deskew Circuit for Automatic Test Equipment
Patent: 4,550,405 →
Application: 06/452,608 →
Method of Inducing Flow or Densification of Phosphosilicate Glass for Integrated Circuits
Patent: 4,455,325 →
Application: 06/456,200 →
Controlled Bonding Wire Ball Formation
Patent: 4,476,366 →
Application: 06/463,033 →
Process for Fabricating Precision Optical Spacers for Image Sensor Filters
Patent: 4,515,662 →
Application: 06/464,187 →
Lead Wire Bond Attempt Detection
Patent: 4,555,052 →
Application: 06/470,217 →
Multiple Level Voltage Comparator Circuit
Patent: 4,647,796 →
Application: 06/472,426 →
Participate Register for Parallel Loading Pin-Oriented Registers in Test Equipment
Patent: 4,594,544 →
Application: 06/472,427 →
Formation of Patterned Film Over Semiconductor Structure
Patent: 4,420,365 →
Application: 06/474,866 →
High Speed, Nonvolatile, Electrically Erasable Memory Cell and System
Patent: 4,435,790 →
Application: 06/474,929 →
Ttl Output Stage Having Auxiliary Drive to Pull-Down Transistor
Patent: 4,912,344 →
Application: 06/475,810 →
Microprocessor with Branch Control
Patent: 4,573,118 →
Application: 06/481,061 →
Laser Treatment of Silicon Nitride
Patent: 4,549,064 →
Application: 06/482,122 →
Multilayer Metal Silicide Interconnections for Integrated Circuits
Patent: 4,488,166 →
Application: 06/484,070 →
Method and Apparatus for Simulating Aural Response Information
Patent: 4,536,844 →
Application: 06/488,886 →
Method of Fabricating Integrated Circuit Structures Using Replica Patterning
Patent: 4,572,765 →
Application: 06/490,622 →
Scale-Space Filtering
Patent: 4,658,372 →
Application: 06/494,194 →
Computer with Console Addressable Pla Storing Control Microcode + Microinstructions for Self Test of Internal Registers & Alu
Patent: 4,482,953 →
Application: 06/495,735 →
Impregnation of Aluminum Interconnects with Copper
Patent: 4,489,482 →
Application: 06/501,348 →
Method of Etching Refractory Metal Film on Semiconductor Structures Utilizing Triethylamine H O 2 2
Patent: 4,443,295 →
Application: 06/503,976 →
Apparatus for Maintaining Reserve Bonding Wire
Patent: 4,498,638 →
Application: 06/507,340 →
Redundancy Roll Call Technique
Patent: 4,567,580 →
Application: 06/508,782 →
Wafer Fabrication by Implanting Through Protective Layer
Patent: 4,498,227 →
Application: 06/510,761 →
Process for Fabricating Optical Wave-Guiding Components and Components Made by the Process
Patent: 4,585,299 →
Application: 06/515,112 →
Integrated Circuit Having a Pre-Attched Conductive Mounting Media and Method of Making the Same
Patent: 4,688,075 →
Application: 06/516,019 →
Method and Apparatus for Forming Ball Bonds
Patent: 4,594,493 →
Application: 06/517,190 →
Method of Making an Integrated Injection Logic Cell Having Self- Aligned Collector and Base Reduced Resistance Utilizing Selective Diffusion from Polycrystalline Regions
Patent: 4,512,075 →
Application: 06/517,564 →
Method of Fabricating Polysilicon Resistors in Integrated Circuit Structures
Patent: 4,502,894 →
Application: 06/522,934 →
Process for Fabricating a Lateral Transistor Having Self-Aligned Base and Base Contact
Patent: 4,545,113 →
Application: 06/527,146 →
Method and Apparatus for Measuring the Settling Time of an Analog Signal
Patent: 4,527,907 →
Application: 06/529,301 →
Integrated Circuit Chip Wiring Arrangement Providing Reduced Circuit Inductance and Controlled Voltage Gradients
Patent: 4,583,111 →
Application: 06/530,636 →
Read Only Memory and Decode Circuit
Patent: 4,583,168 →
Application: 06/530,996 →
Logic Structure Utilizing Polycrystalline Silicon Schottky Diodes
Patent: 4,584,594 →
Application: 06/533,033 →
Etching Method
Patent: 4,484,978 →
Application: 06/535,148 →
Double Polysilicon Process for Fabricating Cmos Integrated Circuits
Patent: 4,517,731 →
Application: 06/537,188 →
Method and Apparatus for Analyzing an Analog-to-Digital Converter with a Nonideal Digital-to-Analog Converter
Patent: 4,583,075 →
Application: 06/539,359 →
Robotic Hand and Method for Manipulating Printed Circuit Boards
Patent: 4,616,971 →
Application: 06/540,415 →
Apparatus for Compensating Digital to Analog Converter Errors
Patent: 4,740,776 →
Application: 06/542,286 →
Serial-Parallel-Serial Charged Coupled Device Memory and a Method of Transferring Charge Therein
Patent: 4,493,060 →
Application: 06/543,228 →
Pulse-Width Control of Bonding Ball Formation
Patent: 4,482,794 →
Application: 06/555,696 →
Low Impedance Package for Integrated Circuit Die
Patent: 4,680,613 →
Application: 06/557,119 →
Circuit and Method for Split Bias Enable/Inhibit Memory Operation
Patent: 4,578,594 →
Application: 06/573,532 →
Semiconductor Planarization Process and Structures Made Thereby
Patent: 4,539,744 →
Application: 06/576,665 →
Lead Wire Bonding with Increased Bonded Surface Area
Patent: 4,597,519 →
Application: 06/584,083 →
Variation and Control of Bond Force
Patent: 4,603,802 →
Application: 06/584,084 →
Mos Imaging Device with Monochrome-Color Compatibility and Signal Readout Versatility
Patent: 4,658,287 →
Application: 06/584,855 →
Tri-State Driver Circuit for Automatic Test Equipment
Patent: 4,572,971 →
Application: 06/585,477 →
Mos Battery Backup Controller for Microcomputer Random Access Memory
Patent: 32,200 →
Application: 06/586,172 →
Ttl Tristate Device with Reduced Output Capacitance
Patent: 4,581,550 →
Application: 06/586,671 →
Method and Structure for Inhibiting Dopant Out-Diffusion
Patent: 4,640,004 →
Application: 06/600,163 →
Current Probe Signal Processing Circuit Employing Sample and Hold Technique to Locate Circuit Faults
Patent: 4,517,511 →
Application: 06/610,347 →
Gate Having Temperature - Stabilized Delay
Patent: 4,651,038 →
Application: 06/611,266 →
Method and Apparatus for Applying and Monitoring Programmed Test Signals During Automated Testing of Electronic Circuits
Patent: 4,646,299 →
Application: 06/611,445 →
Formatter for High Speed Test System
Patent: 4,635,256 →
Application: 06/611,446 →
Method and Apparatus for Monitoring Response Signals During Automated Testing of Electronic Circuits
Patent: 4,635,259 →
Application: 06/611,448 →
Method and Apparatus for Monitoring Automated Testing of Electronic Circuits
Patent: 4,637,020 →
Application: 06/611,449 →
Method and Apparatus for Dynamically Controlling the Timing of Signals in Automatic Test Systems
Patent: 4,675,562 →
Application: 06/611,451 →
Multiple-Stage Gate Network Having Independent Reference Voltage Sources
Patent: 4,623,802 →
Application: 06/611,454 →
Method and Apparatus for Testing Integrated Circuits
Patent: 4,764,925 →
Application: 06/620,736 →
Ion Implantation to Increase Emitter Energy Gap in Bipolar Transistors
Patent: 4,559,696 →
Application: 06/629,576 →
Method and Apparatus for Minimizing Digital-to-Analog Converter Correction Trims
Patent: 4,673,917 →
Application: 06/631,958 →
Multiple Phase-Splitter Ttl Output Circuit with Improved Drive Characteristics
Patent: 4,661,727 →
Application: 06/632,433 →
Electric Device or Circuit Testing Method and Apparatus
Patent: 4,686,628 →
Application: 06/632,460 →
Self-Aligned Metal Silicide Process for Integrated Circuits Having Self-Aligned Polycrystalline Silicon Electrodes
Patent: 4,609,568 →
Application: 06/634,936 →
Method for Controlling Lateral Diffusion of Silicon in a Self-Aligned TISI2 Process
Patent: 4,567,058 →
Application: 06/634,937 →
Integrated Circuit Bipolar Memory Cell
Patent: 4,622,575 →
Application: 06/647,315 →
Method for Making a Cmos Circuit Having a Reduced Tendency to Latch by Controlling the Band-Gap of Source and Drain Regions
Patent: 4,603,471 →
Application: 06/647,743 →
Base-Coupled Transistor Logic
Patent: 4,947,230 →
Application: 06/650,660 →
Microprocessor with Compact Mapped Programmable Logic Array
Patent: 4,713,750 →
Application: 06/666,215 →
Memory Cell Power Scavenging Apparatus and Method
Patent: 4,627,034 →
Application: 06/669,929 →
Fabrication Process Employing Special Masks for the Manufacture of High-Speed Bipolar Analog Intergrated Circuits
Patent: 4,648,909 →
Application: 06/675,497 →
Method of Making Precision High-Value Mos Capacitors
Patent: 4,639,274 →
Application: 06/676,033 →
Method of Forming a Dielectric Layer on a Semiconductor Device
Patent: 4,619,839 →
Application: 06/680,878 →
Method and Apparatus for Low Pressure Chemical Vapor Deposition
Patent: 4,619,844 →
Application: 06/693,401 →
A Method of Fabricating Schottky Diodes and Electrical Tnterconnections in Semiconductor Structures
Patent: 4,624,863 →
Application: 06/696,969 →
Apparatus for Feeding Bonding Wire
Patent: 4,685,631 →
Application: 06/697,833 →
Digital Quadrature Amplitude Modulator
Patent: 4,661,948 →
Application: 06/701,036 →
Ttl Circuits Generating Complementary Signals
Patent: 4,649,297 →
Application: 06/704,375 →
Amplifier Active Load
Patent: 4,629,997 →
Application: 06/715,848 →
Photomask Having a Patterned Carbon Light-Blocking Coating
Patent: 4,704,342 →
Application: 06/719,020 →
Black and White Reference and End-of-Scan Indicator for Charge Coupled Devices
Patent: 4,675,549 →
Application: 06/719,657 →
Monolithic Telephone Subscriber Line Interface Circuit
Patent: 4,712,233 →
Application: 06/725,461 →
Emitter Coupled Logic to Transistor Transistor Logic Translator
Patent: 4,677,320 →
Application: 06/729,552 →
Film Carrier for Manufacturing Semiconductor Devices
Patent: 4,600,611 →
Application: 06/730,663 →
Method and Apparatus for Improving the Accuracy and Resolution of an Analog-to-Digital Converter (Adc)
Patent: 4,710,747 →
Application: 06/731,683 →
Transistor Transistor Ligic to Emitter Coupled Logic Translator
Patent: 4,654,549 →
Application: 06/741,007 →
Method of Controlling Dopant Diffusion and Dopant Electrical Activation by Implanted Inert Gas Atoms
Patent: 4,689,667 →
Application: 06/743,556 →
Stress Relieved Intermediate Insulating Layer for Multilayer Metalization
Patent: 4,654,269 →
Application: 06/747,471 →
Self-Aligned Antiblooming Structure for Charge-Coupled Devices
Patent: 4,593,303 →
Application: 06/758,563 →
Pattern Addressable Memory
Patent: 4,747,072 →
Application: 06/765,370 →
Memory Apparatus and Method for Retrieving Sequences of Symbols Including Variable Elements
Patent: 4,748,439 →
Application: 06/765,387 →
Multilayer Glass Passivation Structure and Method for Forming the Same
Patent: 4,972,251 →
Application: 06/765,892 →
Temperature Compensated Sense Amplifier
Patent: 4,727,269 →
Application: 06/766,865 →
Electron Beam Test Probe for Integrated Circuit Testing
Patent: 4,864,228 →
Application: 06/766,905 →
Oxide Isolation Process for Standard Ram/Prom and Lateral Pnp Cell Ram
Patent: 4,624,046 →
Application: 06/770,355 →
Low Temperature Melting Binary Glasses for Leveling Surfaces of Integrated Circuits Containing Isolated Grooves
Patent: 4,630,343 →
Application: 06/773,842 →
Selectable Resolution Line-Scan Image Sensor
Patent: 4,918,506 →
Application: 06/775,668 →
Schottky Shunt Integrated Injection
Patent: 4,629,912 →
Application: 06/776,992 →
Distributed Field Effect Transistor Structure
Patent: 4,636,825 →
Application: 06/784,810 →
Multistatistics Gatherer
Patent: 4,742,551 →
Application: 06/785,352 →
Polycrystalline Silicon Schottky Diode Array
Patent: 4,628,339 →
Application: 06/794,586 →
Submerged Wall Isolation of Silicon Islands
Patent: 4,888,300 →
Application: 06/796,041 →
Signal Ground Planes for Tape Bonded Devices
Patent: 4,674,808 →
Application: 06/797,283 →
Electron Beam Test Probe System for Analyzing Integrated Circuits
Patent: 4,706,019 →
Application: 06/798,592 →
Digital Method for Synthesizing Composite Video Signals
Patent: 4,718,018 →
Application: 06/800,472 →
Low Temperature Plasma Nitridation Process and Applications of Nitride Films Formed Thereby
Patent: 4,762,728 →
Application: 06/801,955 →
Multiplexer with Inhibit for Ecl Gate Array
Patent: 4,686,674 →
Application: 06/807,929 →
Plasma Confinement in a Low Pressure Electrically Grounded R.F. Heated Reactor and Deposition Method
Patent: 4,686,113 →
Application: 06/810,954 →
Apparatus and Method for Reducing Write Recovery Time in a Random Access Memory
Patent: 4,744,059 →
Application: 06/810,955 →
Ecl Circuit with Current-Splitting Network
Patent: 4,686,394 →
Application: 06/832,796 →
Emitter-Coupled Logic Multiplexer
Patent: 4,695,749 →
Application: 06/832,797 →
Semiconductor Structure Having Alpha Particle Resistant Film and Method of Making the Same
Patent: 4,653,175 →
Application: 06/836,038 →
Process for Forming Vias on Integrated Circuits
Patent: 4,670,091 →
Application: 06/843,328 →
Tri-Level Resist Process for Fine Resolution Photolithography
Patent: 4,732,841 →
Application: 06/843,340 →
Single Bonding Shelf, Multi-Row Wire-Bond Finger Layout for Integrated Circuit Package
Patent: 4,890,153 →
Application: 06/848,302 →
Translinear Static Memory Cell with Bipolar and Mos Devices
Patent: 4,821,235 →
Application: 06/853,297 →
Method for Planarizing Semiconductor Substrates
Patent: 4,676,868 →
Application: 06/855,207 →
Switched Impedance Emitter Coupled Logic Gate
Patent: 4,713,560 →
Application: 06/871,639 →
Die Bonding Process
Patent: 4,772,935 →
Application: 06/875,345 →
Solder Finishing Integrated Circuit Package Leads
Patent: 4,720,396 →
Application: 06/878,307 →
Method of Fabricating High Performance Bicmos Structures Having Poly Emitters and Silicided Bases
Patent: 4,727,046 →
Application: 06/887,007 →
Cmos Circuit Having a Reduced Tendency to Latch
Patent: 4,728,998 →
Application: 06/890,459 →
A Process for Making Isolated Semiconductor Structure
Patent: 4,727,048 →
Application: 06/891,792 →
Floating Point Microprocessor with Directable Two Level Microinstructions
Patent: 4,928,223 →
Application: 06/901,446 →
Fabrication of a Bipolar Transistor with a Polysilicon Ribbon
Patent: 4,722,908 →
Application: 06/901,501 →
Modification of Properties of P-Type Dopants with Other P-Type Dopants
Patent: 4,746,964 →
Application: 06/901,502 →
Planarization Method
Patent: 4,806,504 →
Application: 06/906,344 →
Oscillation-Free, Short-Circuit Protection Circuit
Patent: 4,791,314 →
Application: 06/930,593 →
Bipolar Transistor Switching Enhancement Circuit
Patent: 4,791,313 →
Application: 06/930,608 →
High Density Rom in a Cmos Gate Array
Patent: 4,899,308 →
Application: 06/940,363 →
Plastic Package for High Frequency Semiconductor Devices
Patent: 4,791,473 →
Application: 06/943,339 →
Memory Cell with Separate Read and Write Paths and Clamping Transistors
Patent: 5,016,214 →
Application: 07/003,114 →
Process of Forming a Compliant Lead Frame for Array-Type Semiconductor Packages
Patent: 4,751,199 →
Application: 07/005,675 →
Method for Fabricating Improved Oxide Defined Transistors
Patent: 4,757,027 →
Application: 07/009,773 →
Apparatus and Method for Detecting Spot Defects in Integrated Circuits
Patent: 4,835,466 →
Application: 07/011,729 →
Bicmos Process Having Narrow Bipolar Emitter and Implanted Aluminum Isolation
Patent: 4,734,382 →
Application: 07/017,387 →
Bimos Circuit That Provides Low Power Dissipation and High Transient Drive Capability
Patent: 4,868,421 →
Application: 07/017,634 →
Cellular Addressing Permutation Bit Map Raster Graphics Architecture
Patent: 4,882,683 →
Application: 07/026,041 →
Planarization of Metal Pillars on Uneven Substrates
Patent: 4,824,521 →
Application: 07/033,961 →
Bipmos Decoder Circuit
Patent: 4,857,772 →
Application: 07/042,995 →
Microprocessor Having Multiplication Circuitry Implementing a Modified Booth Algorithm
Patent: 4,755,962 →
Application: 07/045,782 →
Bandgap Voltage Reference Circuit with an Npn Current Bypass Circuit
Patent: 4,795,918 →
Application: 07/045,950 →
Integrated Circuit Package with Thermal Path Layers Incorporating Staggered Thermal Vias
Patent: 4,731,701 →
Application: 07/049,725 →
Expandable Multi-Port Random Access Memory
Patent: 4,817,051 →
Application: 07/069,155 →
Control of Signal Timing Apparatus in Automatic Test Systems Using Minimal Memory
Patent: 4,789,835 →
Application: 07/070,130 →
High Temperature Interconnect System for an Integrated Circuit
Patent: 4,920,071 →
Application: 07/086,200 →
Pla Driver with Reconfigurable Drive
Patent: 4,859,874 →
Application: 07/101,210 →
Semiconductor Chip Package Configuration and Method for Facilitating Its Testing and Mounting on a Substrate
Patent: 4,796,080 →
Application: 07/122,545 →
Ttl Circuit with Increased Transient Drive
Patent: 4,868,424 →
Application: 07/124,971 →
Integrated Circuit Die with Resistive Substrate Isolation of Multiple Circuits
Patent: 4,847,672 →
Application: 07/162,049 →
Apparatus and Method for Tape Bonding
Patent: 4,804,810 →
Application: 07/170,564 →
Circulating Context Addressable Memory
Patent: 4,924,435 →
Application: 07/188,640 →
Ttl Current Sinking Circuit with Transient Performance Enhancement During Output Transition from High to Low
Patent: 4,947,058 →
Application: 07/202,237 →
Ttl Totem Pole Anit-Simultaneous Conduction Circuit
Patent: 4,972,104 →
Application: 07/202,971 →
Ceramic Package for High Frequency Semiconductor Devices
Patent: 4,839,717 →
Application: 07/205,040 →
Means for Reducing Signal Propagation Losses in Very Large Scale Integratead Circuits
Patent: 4,833,521 →
Application: 07/218,433 →
Temperature Compensated Bipolar Circuits
Patent: 4,853,646 →
Application: 07/221,322 →
Structure for Inhibiting Dopant Out-Diffusion
Patent: 4,829,363 →
Application: 07/223,684 →
Low Noise Integrated Circuit and Leadframe
Patent: 5,065,224 →
Application: 07/243,195 →
Enhanced Density Modified Isoplanar Process
Patent: 4,849,344 →
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Extended Silicide and External Contact Technology
Patent: 5,045,916 →
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High Performance Interconnect System for an Integrated Circuit
Patent: 4,933,743 →
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Process for Fabricating Complementary Contactless Vertical Bipolar Transistors
Patent: 5,014,107 →
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Small Contactless Ram Cell
Patent: 5,072,275 →
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Method of Fabricating a High Performance Interconnect System for an Integrated Circuit
Patent: 5,000,818 →
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Method of Fabricating a Base-Coupled Transistor Logic
Patent: 5,166,094 →
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High Performance Interconnect System for an Integrated Circuit
Patent: 5,117,276 →
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Transceiver with Isolated Power Rails for Ground Bounce Reduction
Patent: 5,173,621 →
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Method of Making Small Contactless Ram Cell
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Related Assignments (14)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignors Interest. Dec 15, 1980
From: BLASER, LAWRENCE M.; ARGUELLO LEONARD E.
To: FAIRCHILD CAMERA AND INSTRUMENT CORPORATION, A CORP. OF DE.
Reel/Frame 003814/0265 →
Assignment of Assignors Interest. Jun 12, 1981
From: BECHDOLT ROBERT W.
To: FAIRCHILD CAMERA AND INSTRUMENT CORPORATION, A CORP. OF DE.
Reel/Frame 003860/0539 →
Assignment of Assignors Interest. Nov 16, 1987
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: SCHLUMBERGER SYSTEMS AND SERVICES, INC.
Reel/Frame 004821/0860 →
Assignment of Assignors Interest. Oct 28, 1991
From: FAIRCHILD WESTON SYSTEMS INC.
To: LORAL FAIRCHILD CORP.,
Reel/Frame 005881/0402 →
Assignment of Assignors Interest. Mar 8, 1993
From: ROGERS CORPORATION
To: CIRCUIT COMPONENTS, INCORPORATED
Reel/Frame 006445/0854 →
Assignment of Assignors Interest. Apr 5, 1993
From: SCHLUMBERGER TECHNOLOGIES, INC.
To: EVERETT CHARLES TECHNOLOGIES, INC.
Reel/Frame 006484/0210 →
Assignment of Assignor's Interest Mar 21, 1997
From: NATIONAL SEMICONDUCTOR CORPORATION
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 008535/0103 →
Security Interest Mar 21, 1997
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: BANKERS TRUST COMPANY
Reel/Frame 008454/0101 →
Assignment of Assignor's Interest Dec 29, 1997
From: EVERETT CHARLES TECHNOLOGIES, INC.
To: DELAWARE CAPITAL FORMATION, INC.
Reel/Frame 008861/0833 →
Security Agreement Apr 30, 1999
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: CREDIT SUISSE FIRST BOSTON
Reel/Frame 009883/0800 →
Release of Security Interest May 3, 1999
From: BANKERS TRUST COMPANY
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 009901/0528 →
Release Jul 27, 2000
From: CREDIT SUISSE FIRST BOSTON
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 010996/0537 →
Change of Name Apr 2, 2001
From: FAIRCHILD CAMERA AND INSTRUMENT CORPORATION, A DELAWARE CORPORATION
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 011692/0679 →
Assignment of Assignor's Interest Apr 6, 2001
From: FAICHILD SEMICONDUCTOR CORPORATION, A CORP. OF DE
To: FAIRCHILD WESTON SYSTEMS, INC.
Reel/Frame 011712/0169 →